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hathach 2021-10-25 21:20:58 +07:00
parent dbd31895bc
commit 460052c8a0
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2 changed files with 983 additions and 998 deletions
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2
src/portable/synopsys/dwc2/dwc2_gd32.h
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@ -32,8 +32,6 @@
extern "C" {
#endif
// These numbers are the same for the whole GD32VF103 family.
#define DWC2_REG_BASE 0x50000000UL
#define DWC2_EP_MAX 4
#define DWC2_EP_FIFO_SIZE 1280

153
src/portable/synopsys/dwc2/dwc2_type.h
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@ -23,135 +23,123 @@
extern "C" {
#endif
#ifdef __cplusplus
#define __I volatile
#else
#define __I volatile const
#endif
#define __O volatile
#define __IO volatile
#define __IM volatile const
#define __OM volatile
#define __IOM volatile
#if 0
// HS PHY
typedef struct
{
__IO uint32_t HS_PHYC_PLL; /*!< This register is used to control the PLL of the HS PHY. 000h */
__IO uint32_t Reserved04; /*!< Reserved 004h */
__IO uint32_t Reserved08; /*!< Reserved 008h */
__IO uint32_t HS_PHYC_TUNE; /*!< This register is used to control the tuning interface of the High Speed PHY. 00Ch */
__IO uint32_t Reserved10; /*!< Reserved 010h */
__IO uint32_t Reserved14; /*!< Reserved 014h */
__IO uint32_t HS_PHYC_LDO; /*!< This register is used to control the regulator (LDO). 018h */
volatile uint32_t HS_PHYC_PLL; /*!< This register is used to control the PLL of the HS PHY. 000h */
volatile uint32_t Reserved04; /*!< Reserved 004h */
volatile uint32_t Reserved08; /*!< Reserved 008h */
volatile uint32_t HS_PHYC_TUNE; /*!< This register is used to control the tuning interface of the High Speed PHY. 00Ch */
volatile uint32_t Reserved10; /*!< Reserved 010h */
volatile uint32_t Reserved14; /*!< Reserved 014h */
volatile uint32_t HS_PHYC_LDO; /*!< This register is used to control the regulator (LDO). 018h */
} HS_PHYC_GlobalTypeDef;
#endif
// Core
typedef struct
{
__IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
__IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
__IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
__IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
__IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
__IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
__IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
__IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
__IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
__IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
__IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
__IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
volatile uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
volatile uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
volatile uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
volatile uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
volatile uint32_t GRSTCTL; /*!< Core Reset Register 010h */
volatile uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
volatile uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
volatile uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
volatile uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
volatile uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
volatile uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
volatile uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
uint32_t Reserved30[2]; /*!< Reserved 030h */
__IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
__IO uint32_t CID; /*!< User ID Register 03Ch */
__IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
__IO uint32_t GHWCFG1; /* User HW config1 044h*/
__IO uint32_t GHWCFG2; /* User HW config2 048h*/
__IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
volatile uint32_t GCCFG; /*!< General Purpose IO Register 038h */
volatile uint32_t CID; /*!< User ID Register 03Ch */
volatile uint32_t GSNPSID; /* USB_OTG core ID 040h*/
volatile uint32_t GHWCFG1; /* User HW config1 044h*/
volatile uint32_t GHWCFG2; /* User HW config2 048h*/
volatile uint32_t GHWCFG3; /*!< User HW config3 04Ch */
uint32_t Reserved6; /*!< Reserved 050h */
__IO uint32_t GLPMCFG; /*!< LPM Register 054h */
__IO uint32_t GPWRDN; /*!< Power Down Register 058h */
__IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
__IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
volatile uint32_t GLPMCFG; /*!< LPM Register 054h */
volatile uint32_t GPWRDN; /*!< Power Down Register 058h */
volatile uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
volatile uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
__IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
__IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */
volatile uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
volatile uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */
} dwc2_core_t;
// Host
typedef struct
{
__IO uint32_t HCFG; /*!< Host Configuration Register 400h */
__IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
__IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
volatile uint32_t HCFG; /*!< Host Configuration Register 400h */
volatile uint32_t HFIR; /*!< Host Frame Interval Register 404h */
volatile uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
uint32_t Reserved40C; /*!< Reserved 40Ch */
__IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
__IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
__IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
volatile uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
volatile uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
volatile uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
} dwc2_host_t;
// Host Channel
typedef struct
{
__IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
__IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
__IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
__IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
__IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
__IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
volatile uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
volatile uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
volatile uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
volatile uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
volatile uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
volatile uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
uint32_t Reserved[2]; /*!< Reserved */
} dwc2_channel_t;
// Device
typedef struct
{
__IO uint32_t DCFG; /*!< dev Configuration Register 800h */
__IO uint32_t DCTL; /*!< dev Control Register 804h */
__IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
volatile uint32_t DCFG; /*!< dev Configuration Register 800h */
volatile uint32_t DCTL; /*!< dev Control Register 804h */
volatile uint32_t DSTS; /*!< dev Status Register (RO) 808h */
uint32_t Reserved0C; /*!< Reserved 80Ch */
__IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
__IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
__IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
__IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
volatile uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
volatile uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
volatile uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
volatile uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
uint32_t Reserved20; /*!< Reserved 820h */
uint32_t Reserved9; /*!< Reserved 824h */
__IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
__IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
__IO uint32_t DTHRCTL; /*!< dev threshold 830h */
__IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
__IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
__IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
volatile uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
volatile uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
volatile uint32_t DTHRCTL; /*!< dev threshold 830h */
volatile uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
volatile uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
volatile uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
uint32_t Reserved40; /*!< dedicated EP mask 840h */
__IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
volatile uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
__IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
volatile uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
} dwc2_device_t;
// Endpoint IN
typedef struct
{
__IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
volatile uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
__IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
volatile uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
__IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
__IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
__IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
volatile uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
volatile uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
volatile uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
} dwc2_epin_t;
// Endpoint OUT
typedef struct
{
__IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
volatile uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
__IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
volatile uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
__IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
__IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
volatile uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
volatile uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
} dwc2_epout_t;
@ -803,7 +791,6 @@ typedef struct
#define DAINTMSK_OEPM DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
/******************** Bit definition for OTG register ********************/
#define CHNUM_Pos (0U)
#define CHNUM_Msk (0xFUL << CHNUM_Pos) /*!< 0x0000000F */
#define CHNUM CHNUM_Msk /*!< Channel number */
@ -1435,7 +1422,7 @@ typedef struct
#define DIEPTSIZ_MULCNT_Pos (29U)
#define DIEPTSIZ_MULCNT_Msk (0x3UL << DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
#define DIEPTSIZ_MULCNT DIEPTSIZ_MULCNT_Msk /*!< Packet count */
/******************** Bit definition for HCTSIZ register ********************/
/******************** Bit definition for HCTSIZ register ********************/
#define HCTSIZ_XFRSIZ_Pos (0U)
#define HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
#define HCTSIZ_XFRSIZ HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
@ -1461,12 +1448,12 @@ typedef struct
#define HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
#define HCDMA_DMAADDR HCDMA_DMAADDR_Msk /*!< DMA address */
/******************** Bit definition for DTXFSTS register ********************/
/******************** Bit definition for DTXFSTS register ********************/
#define DTXFSTS_INEPTFSAV_Pos (0U)
#define DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
#define DTXFSTS_INEPTFSAV DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
/******************** Bit definition for DIEPTXF register ********************/
/******************** Bit definition for DIEPTXF register ********************/
#define DIEPTXF_INEPTXSA_Pos (0U)
#define DIEPTXF_INEPTXSA_Msk (0xFFFFUL << DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
#define DIEPTXF_INEPTXSA DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */