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stm32f4: Start implementing dcd_edpt_xfer.
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@ -51,10 +51,21 @@
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#define IN_EP_BASE (USB_OTG_INEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE)
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#define FIFO_BASE(_x) (uint32_t *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_FIFO_BASE + _x * USB_OTG_FIFO_SIZE)
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static ATTR_ALIGNED(4) uint32_t _setup_packet[6];
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static uint8_t _setup_offs; // We store up to 3 setup packets.
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typedef struct {
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uint8_t * buffer;
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uint16_t total_len;
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uint16_t queued_len;
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uint8_t max_size;
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} xfer_ctl_t;
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xfer_ctl_t xfer_status[4][2];
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#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
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// Setup the control endpoint 0.
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static void bus_reset(void) {
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USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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@ -210,9 +221,35 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
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{
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(void) rhport;
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//USB_OTG_DeviceTypeDef * dev = DEVICE_BASE;
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//USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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// uint8_t const epnum = edpt_number(ep_addr);
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// uint8_t const dir = edpt_dir(ep_addr);
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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xfer_ctl_t * xfer = XFER_CTL_BASE(epnum, dir);
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xfer->buffer = buffer;
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xfer->total_len = total_bytes;
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xfer->queued_len = 0;
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// IN and OUT endpoint xfers are interrupt-driven, we just schedule them
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// here.
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if(dir == TUSB_DIR_IN) {
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uint8_t short_packet_size = total_bytes % xfer->max_size;
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uint16_t num_packets = (total_bytes / xfer->max_size);
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// Zero-size packet is special case.
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if(short_packet_size > 0 || (total_bytes == 0)) {
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num_packets++;
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}
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in_ep[epnum].DIEPTSIZ = (num_packets << USB_OTG_DIEPTSIZ_PKTCNT_Pos) | \
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((total_bytes & USB_OTG_DIEPTSIZ_XFRSIZ_Msk) << USB_OTG_DIEPTSIZ_XFRSIZ_Pos);
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in_ep[epnum].DIEPCTL |= USB_OTG_DIEPCTL_EPENA | USB_OTG_DIEPCTL_CNAK;
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} else {
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}
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//
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// UsbDeviceDescBank* bank = &sram_registers[epnum][dir];
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// UsbDeviceEndpoint* ep = &USB->DEVICE.DeviceEndpoint[epnum];
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