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hathach 2022-12-04 18:51:52 +07:00
parent 6a2cf67289
commit 43b255f413
13 changed files with 16 additions and 16 deletions
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2
docs/contributing/index.rst
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@ -6,7 +6,7 @@ Contributing can be highly rewarding, but it can also be frustrating at times.
It takes time to review patches, and as this is an open source project, that
sometimes can take a while. The reviewing process depends on the availability
of the maintainers, who may not be always available. Please try to be
understanding throught the process.
understanding through the process.
There a few guidelines you need to keep in mind when contributing. Please have
a look at them as that will make the contribution process easier for all

4
examples/device/hid_generic_inout/hid_test.py
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@ -13,8 +13,8 @@ for vid in USB_VID:
if dev:
while True:
# Get input from console and encode to UTF8 for array of chars.
# hid generic inout is single report therefore by HIDAPI requirement
# it must be preceeded with 0x00 as dummy reportID
# hid generic in/out is single report therefore by HIDAPI requirement
# it must be preceded, with 0x00 as dummy reportID
str_out = b'\x00'
str_out += input("Send text to HID Device : ").encode('utf-8')
dev.write(str_out)

2
hw/bsp/gd32vf103/family.c
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@ -112,7 +112,7 @@ void board_init(void) {
otg_core_regs->GCCFG &= ~GCCFG_VBUSIG;
#endif
/* Enable interrupts globaly */
/* Enable interrupts globally */
__enable_irq();
}

2
hw/bsp/sltb009a/sltb009a.c
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@ -397,7 +397,7 @@ void cmu_init(void)
CMU->HFCLKSEL = CMU_HFCLKSEL_HF_HFXO;
while((CMU->HFCLKSTATUS & _CMU_HFCLKSTATUS_SELECTED_MASK) != CMU_HFCLKSTATUS_SELECTED_HFXO);
// Calibrate HFRCO for 72MHz and enable tunning by PLL
// Calibrate HFRCO for 72MHz and enable tuning by PLL
cmu_hfrco_calib((DEVINFO->HFRCOCAL16) | CMU_HFRCOCTRL_FINETUNINGEN);
// Setup the PLL

4
hw/bsp/stm32g4/boards/stm32g474nucleo/STM32G474RETx_FLASH.ld
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@ -16,7 +16,7 @@
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed “as is,” without any warranty
** Distribution: The file is distributed <EFBFBD>as is,<2C> without any warranty
** of any kind.
**
*****************************************************************************
@ -151,7 +151,7 @@ SECTIONS
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
/* This is used by the startup in order to initialize the .bss section */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)

2
hw/bsp/stm32l4/boards/stm32l412nucleo/STM32L412KBUx_FLASH.ld
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@ -145,7 +145,7 @@ SECTIONS
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
/* This is used by the startup in order to initialize the .bss section */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)

4
hw/bsp/stm32u5/boards/stm32u575eval/board.h
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@ -69,7 +69,7 @@ static inline void board_clock_init(void)
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
/** Initializes the CPU, AHB and APB busses clocks
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
@ -92,7 +92,7 @@ static inline void board_clock_init(void)
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
/** Initializes the CPU, AHB and APB busses clocks
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;

2
src/class/hid/hid_device.h
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@ -182,7 +182,7 @@ static inline bool tud_hid_gamepad_report(uint8_t report_id, int8_t x, int8_t y
HID_COLLECTION ( HID_COLLECTION_APPLICATION ) ,\
/* Report ID if any */\
__VA_ARGS__ \
/* 8 bits Modifier Keys (Shfit, Control, Alt) */ \
/* 8 bits Modifier Keys (Shift, Control, Alt) */ \
HID_USAGE_PAGE ( HID_USAGE_PAGE_KEYBOARD ) ,\
HID_USAGE_MIN ( 224 ) ,\
HID_USAGE_MAX ( 231 ) ,\

2
src/class/usbtmc/usbtmc_device.c
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@ -599,7 +599,7 @@ bool usbtmcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request
// At this point, a transfer MAY be in progress. Based on USB spec, when clearing bulk EP HALT,
// the EP transfer buffer needs to be cleared and DTOG needs to be reset, even if
// the EP is not halted. The only USBD API interface to do this is to stall and then unstall the EP.
// the EP is not halted. The only USBD API interface to do this is to stall and then un-stall the EP.
if(ep_addr == usbtmc_state.ep_bulk_out)
{
criticalEnter();

2
src/portable/dialog/da146xx/dcd_da146xx.c
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@ -243,7 +243,7 @@ static struct
// Converts xfer pointer to epnum (0,1,2,3) regardless of xfer direction
#define XFER_EPNUM(xfer) ((xfer - &_dcd.xfer_status[0][0]) >> 1)
// Converts xfer pinter to EPx_REGS pointer (returns same pointer for IN and OUT with same endpoint number)
// Converts xfer pointer to EPx_REGS pointer (returns same pointer for IN and OUT with same endpoint number)
#define XFER_REGS(xfer) ep_regs[XFER_EPNUM(xfer)]
// Converts epnum (0,1,2,3) to EPx_REGS pointer
#define EPNUM_REGS(epnum) ep_regs[epnum]

2
src/portable/nordic/nrf5x/dcd_nrf5x.c
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@ -170,7 +170,7 @@ static void xact_out_dma(uint8_t epnum)
uint32_t xact_len;
// DMA can't be active during read of SIZE.EPOUT or SIZE.ISOOUT, so try to lock,
// If already running deffer call regardless if it was called from ISR or task,
// If already running defer call regardless if it was called from ISR or task,
if ( atomic_flag_test_and_set(&_dcd.dma_running) )
{
usbd_defer_func((osal_task_func_t)xact_out_dma_wrapper, (void *)(uint32_t)epnum, is_in_isr());

2
src/portable/renesas/usba/hcd_usba.c
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@ -600,7 +600,7 @@ uint32_t hcd_frame_number(uint8_t rhport)
bool hcd_port_connect_status(uint8_t rhport)
{
(void)rhport;
return USB0.INTSTS1.BIT.ATTCH ? true: false;
return USB0.INTSTS1.BIT.ATTCH ? true : false;
}
void hcd_port_reset(uint8_t rhport)

2
src/portable/valentyusb/eptri/dcd_eptri.c
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@ -465,7 +465,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
enable = 1;
usb_out_ctrl_write((0 << CSR_USB_OUT_CTRL_STALL_OFFSET) | (enable << CSR_USB_OUT_CTRL_ENABLE_OFFSET) | tu_edpt_number(ep_addr));
}
// IN endpoints will get unstalled when more data is written.
// IN endpoints will get un-stalled when more data is written.
}
bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes)