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synced 2025-03-19 19:21:05 +00:00
implemented ch34x_set_line_coding() and some code cleanup
This commit is contained in:
IngHK
parent
f221c0fb66
commit
3968a0fff8
@ -1179,7 +1179,7 @@ static void cp210x_process_config(tuh_xfer_t* xfer) {
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enum {
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CONFIG_CH34X_READ_VERSION = 0,
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CONFIG_CH34X_SERIAL_INIT,
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CONFIG_CH34X_SET_LINE_CODING,
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CONFIG_CH34X_SPECIAL_REG_WRITE,
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CONFIG_CH34X_FLOW_CONTROL,
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CONFIG_CH34X_MODEM_CONTROL,
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@ -1292,11 +1292,10 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
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case CH34X_REQ_WRITE_REG:
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// register write request
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switch (value) {
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case (0x1312):
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case 0x1312:
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// baudrate write
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p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
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break;
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default:
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TU_ASSERT(false,); // unexpected register write
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break;
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@ -1310,13 +1309,60 @@ static void ch34x_control_complete(tuh_xfer_t* xfer) {
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} else {
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p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_RTS;
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}
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if (~value & CH34X_BIT_DTR) {
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p_cdc->line_state |= CDC_CONTROL_LINE_STATE_DTR;
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} else {
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p_cdc->line_state &= (uint8_t ) ~CDC_CONTROL_LINE_STATE_DTR;
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}
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break;
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case CH34X_REQ_SERIAL_INIT:
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// serial init request (set line coding incl. baudrate)
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p_cdc->line_coding.bit_rate = p_cdc->baudrate_requested;
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uint8_t lcr = (uint8_t) (value >> 8);
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TU_ASSERT (lcr & CH34X_LCR_ENABLE_RX && lcr & CH34X_LCR_ENABLE_TX,); // both have to be enabled
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switch (lcr & CH34X_LCR_CS_MASK) {
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case CH34X_LCR_CS5:
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p_cdc->line_coding.data_bits = 5;
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break;
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case CH34X_LCR_CS6:
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p_cdc->line_coding.data_bits = 6;
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break;
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case CH34X_LCR_CS7:
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p_cdc->line_coding.data_bits = 7;
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break;
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case CH34X_LCR_CS8:
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p_cdc->line_coding.data_bits = 8;
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break;
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default:
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TU_ASSERT (false,); // unexpected data_bits lcr
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break;
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}
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if (lcr & CH34X_LCR_STOP_BITS_2) {
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p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_2;
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} else {
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p_cdc->line_coding.stop_bits = CDC_LINE_CODING_STOP_BITS_1;
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}
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switch (lcr & CH34X_LCR_PAR_MASK) {
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case 0:
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p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_NONE;
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break;
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case CH34X_LCR_ENABLE_PAR:
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p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_ODD;
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break;
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case CH34X_LCR_ENABLE_PAR | CH34X_LCR_PAR_EVEN:
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p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_EVEN;
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break;
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case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE:
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p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_MARK;
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break;
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case CH34X_LCR_ENABLE_PAR | CH34X_LCR_MARK_SPACE | CH34X_LCR_PAR_EVEN:
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p_cdc->line_coding.parity = CDC_LINE_CODING_PARITY_SPACE;
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break;
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default:
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TU_ASSERT (false,); // unexpected parity lcr
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break;
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}
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break;
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default:
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@ -1378,15 +1424,57 @@ static bool ch34x_get_factor_divisor(uint32_t baval, uint8_t* factor, uint8_t* d
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return true;
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}
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// calc lcr register value (data bits, parity, stop bits)
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static bool ch34x_get_lcr(cdc_line_coding_t const* line_coding, uint8_t *lcr) {
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*lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
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switch (line_coding->data_bits) {
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case 5:
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*lcr |= CH34X_LCR_CS5;
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break;
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case 6:
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*lcr |= CH34X_LCR_CS6;
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break;
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case 7:
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*lcr |= CH34X_LCR_CS7;
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break;
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case 8:
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*lcr |= CH34X_LCR_CS8;
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break;
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default:
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TU_ASSERT (false); // data_bits not supported
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break;
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}
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TU_ASSERT (line_coding->parity == CDC_LINE_CODING_PARITY_NONE || // supported parities
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line_coding->parity == CDC_LINE_CODING_PARITY_ODD || line_coding->parity == CDC_LINE_CODING_PARITY_EVEN ||
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line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE);
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if (line_coding->parity != CDC_LINE_CODING_PARITY_NONE) {
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*lcr |= CH34X_LCR_ENABLE_PAR;
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if (line_coding->parity == CDC_LINE_CODING_PARITY_EVEN || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) {
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*lcr |= CH34X_LCR_PAR_EVEN;
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}
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if (line_coding->parity == CDC_LINE_CODING_PARITY_MARK || line_coding->parity == CDC_LINE_CODING_PARITY_SPACE) {
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*lcr |= CH34X_LCR_MARK_SPACE;
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}
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}
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TU_ASSERT (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_1 ||
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line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2); // not supported 1.5 stop bits
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if (line_coding->stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
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*lcr |= CH34X_LCR_STOP_BITS_2;
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}
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return true;
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}
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static bool ch34x_set_line_coding(cdch_interface_t* p_cdc, cdc_line_coding_t const* line_coding,
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tuh_xfer_cb_t complete_cb, uintptr_t user_data) {
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// TODO implement later
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(void) p_cdc;
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(void) line_coding;
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(void) complete_cb;
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(void) user_data;
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return false;
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p_cdc->baudrate_requested = line_coding->bit_rate;
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p_cdc->user_control_cb = complete_cb;
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uint8_t factor, divisor, lcr;
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TU_ASSERT (ch34x_get_factor_divisor(line_coding->bit_rate, &factor, &divisor));
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TU_ASSERT (ch34x_get_lcr(line_coding, &lcr));
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TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
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complete_cb ? ch34x_control_complete : NULL, user_data));
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return true;
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}
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static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
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@ -1398,7 +1486,6 @@ static bool ch34x_set_baudrate(cdch_interface_t* p_cdc, uint32_t baudrate,
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uint16_t const value = (uint16_t ) (factor << 8 | 0x80 | divisor);
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TU_ASSERT (ch34x_write_reg(p_cdc, 0x1312, value,
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complete_cb ? ch34x_control_complete : NULL, user_data));
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return true;
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}
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@ -1427,82 +1514,36 @@ static void ch34x_process_config(tuh_xfer_t* xfer) {
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TU_ASSERT (p_cdc,);
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switch (state) {
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case CONFIG_CH34X_READ_VERSION: // request version read
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TU_LOG_DRV("[%u] CDCh CH34x attempt to read version\r\n", p_cdc->daddr);
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TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SERIAL_INIT),);
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case CONFIG_CH34X_READ_VERSION:
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// version read request
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TU_LOG_DRV("[%u] CDCh CH34x attempt to read Chip Version\r\n", p_cdc->daddr);
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TU_ASSERT (ch34x_control_in(p_cdc, CH34X_REQ_READ_VERSION, 0, 0, buffer, 2, ch34x_process_config, CONFIG_CH34X_SET_LINE_CODING),);
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break;
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case CONFIG_CH34X_SERIAL_INIT: { // handle version read data, request to init CH34x with line_coding and baudrate
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case CONFIG_CH34X_SET_LINE_CODING:
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// handle version read data, set CH34x line coding (incl. baudrate)
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uint8_t version = xfer->buffer[0];
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TU_LOG_DRV("[%u] CDCh CH34x Chip version = %02x\r\n", p_cdc->daddr, version);
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// only versions >= 0x30 are tested, below 0x30 seems having other programming, see WCH vendor, linux kernel and FreeBSD drivers
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TU_LOG_DRV("[%u] CDCh CH34x Chip Version = %02x\r\n", p_cdc->daddr, version);
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// only versions >= 0x30 are tested, below 0x30 seems having other programming, see drivers from WCH vendor, Linux kernel and FreeBSD
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TU_ASSERT (version >= 0x30,);
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uint8_t factor, divisor;
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TU_ASSERT (ch34x_get_factor_divisor(line_coding.bit_rate, &factor, &divisor),);
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uint8_t lcr = CH34X_LCR_ENABLE_RX | CH34X_LCR_ENABLE_TX;
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switch (line_coding.data_bits) {
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case 5:
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lcr |= CH34X_LCR_CS5;
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TU_ASSERT (ch34x_set_line_coding(p_cdc, &line_coding, ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
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break;
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case 6:
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lcr |= CH34X_LCR_CS6;
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break;
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case 7:
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lcr |= CH34X_LCR_CS7;
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break;
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case 8:
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lcr |= CH34X_LCR_CS8;
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break;
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default:
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TU_ASSERT (false,); // not supported data_bits
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lcr |= CH34X_LCR_CS8;
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break;
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}
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if (line_coding.parity != CDC_LINE_CODING_PARITY_NONE) {
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lcr |= CH34X_LCR_ENABLE_PAR;
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if (line_coding.parity == CDC_LINE_CODING_PARITY_EVEN ||
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line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
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lcr |= CH34X_LCR_PAR_EVEN;
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}
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if (line_coding.parity == CDC_LINE_CODING_PARITY_MARK ||
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line_coding.parity == CDC_LINE_CODING_PARITY_SPACE) {
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lcr |= CH34X_LCR_MARK_SPACE;
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}
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}
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TU_ASSERT (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_1 ||
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line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2,); // 1.5 stop bits not supported
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if (line_coding.stop_bits == CDC_LINE_CODING_STOP_BITS_2) {
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lcr |= CH34X_LCR_STOP_BITS_2;
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}
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TU_ASSERT (ch34x_control_out(p_cdc, CH34X_REQ_SERIAL_INIT, (uint16_t) (lcr << 8 | 0x9c), (uint16_t) (factor << 8 | 0x80 | divisor),
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ch34x_process_config, CONFIG_CH34X_SPECIAL_REG_WRITE),);
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break;
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}
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case CONFIG_CH34X_SPECIAL_REG_WRITE:
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// do special reg write, purpose unknown, overtaken from WCH driver
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TU_ASSERT (ch34x_write_reg(p_cdc, 0x0f2c, 0x0007, ch34x_process_config, CONFIG_CH34X_FLOW_CONTROL),);
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break;
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case CONFIG_CH34X_FLOW_CONTROL:
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// no hardware flow control
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TU_ASSERT (ch34x_write_reg(p_cdc, 0x2727, 0x0000, ch34x_process_config, CONFIG_CH34X_MODEM_CONTROL),);
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break;
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case CONFIG_CH34X_MODEM_CONTROL:
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// !always! set modem controls RTS/DTR (CH34x has no reset state after CH34X_REQ_SERIAL_INIT)
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TU_ASSERT (ch34x_set_modem_ctrl(p_cdc, CFG_TUH_CDC_LINE_CONTROL_ON_ENUM, ch34x_process_config, CONFIG_CH34X_COMPLETE),);
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break;
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case CONFIG_CH34X_COMPLETE:
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p_cdc->line_coding = line_coding; // CONFIG_CH34X_SERIAL_INIT not handled by ch34x_control_complete
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set_config_complete(p_cdc, idx, itf_num);
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break;
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default:
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TU_ASSERT (false,);
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TU_ASSERT (false,); // something gone wrong, should never reached
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break;
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}
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}
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@ -27,9 +27,13 @@
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#ifndef _CH34X_H_
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#define _CH34X_H_
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// For simplicity, only the name CH34X is used here,
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// but specifically only CH340 and CH341 are supported.
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// There is no official documentation for the CH34x chips. Reference can be found
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// - https://github.com/WCHSoftGroup/ch341ser_linux
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// - https://github.com/torvalds/linux/blob/master/drivers/usb/serial/ch341.c
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// - https://github.com/freebsd/freebsd-src/blob/main/sys/dev/usb/serial/uchcom.c
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// set line_coding @ enumeration
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#ifdef CFG_TUH_CDC_LINE_CODING_ON_ENUM
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@ -45,6 +49,7 @@
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#define CH34X_REQ_SERIAL_INIT 0xA1 // dec 161
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#define CH34X_REQ_MODEM_CTRL 0xA4 // dev 164
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// registers
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#define CH34X_REG_BREAK 0x05
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#define CH34X_REG_PRESCALER 0x12
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#define CH34X_REG_DIVISOR 0x13
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@ -64,10 +69,12 @@
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#define CH34X_LCR_MARK_SPACE 0x20
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#define CH34X_LCR_PAR_EVEN 0x10
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#define CH34X_LCR_ENABLE_PAR 0x08
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#define CH34X_LCR_PAR_MASK 0x38 // all parity bits
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#define CH34X_LCR_STOP_BITS_2 0x04
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#define CH34X_LCR_CS8 0x03
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#define CH34X_LCR_CS7 0x02
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#define CH34X_LCR_CS6 0x01
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#define CH34X_LCR_CS5 0x00
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#define CH34X_LCR_CS_MASK 0x03 // all CSx bits
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#endif /* _CH34X_H_ */
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