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https://github.com/hathach/tinyusb.git
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remove analog PHY from musb_regs_t
hil: remove ch32v203 since not reliable enough
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hathach
parent
6152adb17f
commit
33e3ea3645
@ -97,136 +97,94 @@ typedef struct TU_ATTR_PACKED {
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__IO uint8_t rx_csrl; // 0x06: RX CSRL
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__IO uint8_t rx_csrh; // 0x07: RX CSRH
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__IO uint16_t rx_count; // 0x08: RX COUNT
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__IO uint8_t tx_type; // 0x0A: TX TYPE
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union {
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__IO uint8_t type0; // 0x0A: TYPE0 (host only)
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__IO uint8_t tx_type; // 0x0A: TX TYPE
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};
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__IO uint8_t tx_interval; // 0x0B: TX INTERVAL
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__IO uint8_t rx_type; // 0x0C: RX TYPE
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__IO uint8_t rx_interval; // 0x0D: RX INTERVAL
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__IO uint8_t reserved_0x0e; // 0x0E: Reserved
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__IO uint8_t fifo_size; // 0x0F: FIFO_SIZE
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union {
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__IO uint8_t config_data; // 0x0F: CONFIG DATA
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__IO uint8_t fifo_size; // 0x0F: FIFO_SIZE
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};
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} musb_ep_csr_t;
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TU_VERIFY_STATIC(sizeof(musb_ep_csr_t) == 16, "size is not correct");
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typedef struct {
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//------------- Common -------------//
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__IO uint8_t faddr; // 0x00: FADDR
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__IO uint8_t power; // 0x01: POWER
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__IO uint8_t faddr; // 0x00: FADDR
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__IO uint8_t power; // 0x01: POWER
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__IO uint16_t intr_tx; // 0x02: INTR_TX
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__IO uint16_t intr_rx; // 0x04: INTR_RX
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__IO uint16_t intr_tx; // 0x02: INTR_TX
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__IO uint16_t intr_rx; // 0x04: INTR_RX
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__IO uint16_t intr_txen; // 0x06: INTR_TXEN
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__IO uint16_t intr_rxen; // 0x08: INTR_RXEN
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__IO uint16_t intr_txen; // 0x06: INTR_TXEN
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__IO uint16_t intr_rxen; // 0x08: INTR_RXEN
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__IO uint8_t intrusb; // 0x0A: INTRUSB
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__IO uint8_t intrusben; // 0x0B: INTRUSBEN
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__IO uint8_t intrusb; // 0x0A: INTRUSB
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__IO uint8_t intrusben; // 0x0B: INTRUSBEN
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__IO uint16_t frame; // 0x0C: FRAME
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__IO uint8_t index; // 0x0E: INDEX
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__IO uint8_t testmode; // 0x0F: TESTMODE
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__IO uint16_t frame; // 0x0C: FRAME
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__IO uint8_t index; // 0x0E: INDEX
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__IO uint8_t testmode; // 0x0F: TESTMODE
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//------------- Indexed CSR -------------//
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musb_ep_csr_t indexed_csr; // 0x10-0x1F: Indexed CSR 0-15
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//------------- CSR (indexed) -------------//
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musb_ep_csr_t indexed_csr; // 0x10-0x1F: Indexed CSR 0-15
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//------------- FIFOs -------------//
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__IO uint32_t fifo[16]; // 0x20-0x5C: FIFO 0-15
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__IO uint32_t fifo[16]; // 0x20-0x5C: FIFO 0-15
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// Common (2)
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__IO uint8_t devctl; // 0x60: DEVCTL
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__IO uint8_t misc; // 0x61: MISC
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__IO uint8_t devctl; // 0x60: DEVCTL
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__IO uint8_t misc; // 0x61: MISC
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//------------- Dynammic FIFO -------------//
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__IO uint8_t txfifo_sz; // 0x62: TXFIFO_SZ
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__IO uint8_t rxfifo_sz; // 0x63: RXFIFO_SZ
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__IO uint16_t txfifo_addr; // 0x64: TXFIFO_ADDR
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__IO uint16_t rxfifo_addr; // 0x66: RXFIFO_ADDR
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//------------- Dynammic FIFO (indexed) -------------//
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__IO uint8_t txfifo_sz; // 0x62: TXFIFO_SZ
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__IO uint8_t rxfifo_sz; // 0x63: RXFIFO_SZ
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__IO uint16_t txfifo_addr; // 0x64: TXFIFO_ADDR
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__IO uint16_t rxfifo_addr; // 0x66: RXFIFO_ADDR
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//------------- Additional Control/Status -------------//
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union {
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__O uint32_t vcontrol; // 0x68: VCONTROL
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__IO uint32_t vstatus; // 0x68: VSTATUS
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__O uint32_t vcontrol; // 0x68: VCONTROL
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__IO uint32_t vstatus; // 0x68: VSTATUS
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};
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__IO uint16_t hwvers; // 0x6c: HWVERS
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__R uint16_t rsv_0x6e_0x77[5];
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__IO uint16_t hwvers; // 0x6c: HWVERS
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__R uint16_t rsv_0x6e_0x77[5]; // 0x6E-0x77: Reserved
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//------------- Additional Configuration -------------//
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__IO uint8_t epinfo; // 0x78: EPINFO
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__IO uint8_t raminfo; // 0x79: RAMINFO
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__IO uint8_t softreset; // 0x7A: SOFTRESET (Analog), Link info
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__IO uint8_t vplen; // 0x7B: VPLEN
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__IO uint8_t hs_eof1; // 0x7C: HS_EOF1
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__IO uint8_t fs_eof1; // 0x7D: FS_EOF1
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__IO uint8_t ls_eof1; // 0x7E: LS_EOF1
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__IO uint8_t soft_rst; // 0x7F: SOFT_RST
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//------------- Additional Configuration -------------//
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__IO uint8_t epinfo; // 0x78: EPINFO
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__IO uint8_t raminfo; // 0x79: RAMINFO
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__IO uint8_t softreset; // 0x7A: SOFTRESET (Analog), Link info
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__IO uint8_t vplen; // 0x7B: VPLEN
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__IO uint8_t hs_eof1; // 0x7C: HS_EOF1
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__IO uint8_t fs_eof1; // 0x7D: FS_EOF1
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__IO uint8_t ls_eof1; // 0x7E: LS_EOF1
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__IO uint8_t soft_rst; // 0x7F: SOFT_RST
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//------------- Extended -------------//
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__IO uint16_t ctuch; // 0x80: CTUCH
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__IO uint16_t cthsrtn; // 0x82: CTHSRTN
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__R uint32_t rsv_0x84_0xff[31]; // 0x84-0xFF: Reserved
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__IO uint16_t ctuch; // 0x80: CTUCH
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__IO uint16_t cthsrtn; // 0x82: CTHSRTN
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__R uint32_t rsv_0x84_0xff[31]; // 0x84-0xFF: Reserved
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//------------- Absolute CSR (used index to remap to Indexed above) -------------//
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// TI tm4c can access this directly, but should use indexed_csr for portability
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musb_ep_csr_t ep_csr[16]; // 0x100-0x1FF: EP0-15 CSR
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__R uint32_t rsv_0x200_0x3ff[128]; // 0x200-0x3FF: Reserved
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//------------- Analog PHY -------------//
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__IO uint32_t mxm_usb_reg_00; // 0x400: MXM_USB_REG_00
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__IO uint32_t m31_phy_utmi_reset; // 0x404: M31_PHY_UTMI_RESET
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__IO uint32_t m31_phy_utmi_vcontrol; // 0x408: M31_PHY_UTMI_VCONTROL
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__IO uint32_t m31_phy_clk_en; // 0x40C: M31_PHY_CLK_EN
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__IO uint32_t m31_phy_ponrst; // 0x410: M31_PHY_PONRST
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__IO uint32_t m31_phy_noncry_rstb; // 0x414: M31_PHY_NONCRY_RSTB
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__IO uint32_t m31_phy_noncry_en; // 0x418: M31_PHY_NONCRY_EN
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__R uint32_t rsv_0x41c;
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__IO uint32_t m31_phy_u2_compliance_en; // 0x420: M31_PHY_U2_COMPLIANCE_EN
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__IO uint32_t m31_phy_u2_compliance_dac_adj; // 0x424: M31_PHY_U2_COMPLIANCE_DAC_ADJ
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__IO uint32_t m31_phy_u2_compliance_dac_adj_en; // 0x428: M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN
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__IO uint32_t m31_phy_clk_rdy; // 0x42C: M31_PHY_CLK_RDY
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__IO uint32_t m31_phy_pll_en; // 0x430: M31_PHY_PLL_EN
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__IO uint32_t m31_phy_bist_ok; // 0x434: M31_PHY_BIST_OK
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__IO uint32_t m31_phy_data_oe; // 0x438: M31_PHY_DATA_OE
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__IO uint32_t m31_phy_oscouten; // 0x43C: M31_PHY_OSCOUTEN
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__IO uint32_t m31_phy_lpm_alive; // 0x440: M31_PHY_LPM_ALIVE
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__IO uint32_t m31_phy_hs_bist_mode; // 0x444: M31_PHY_HS_BIST_MODE
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__IO uint32_t m31_phy_coreclkin; // 0x448: M31_PHY_CORECLKIN
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__IO uint32_t m31_phy_xtlsel; // 0x44C: M31_PHY_XTLSEL
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__IO uint32_t m31_phy_ls_en; // 0x450: M31_PHY_LS_EN
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__IO uint32_t m31_phy_debug_sel; // 0x454: M31_PHY_DEBUG_SEL
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__IO uint32_t m31_phy_debug_out; // 0x458: M31_PHY_DEBUG_OUT
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__IO uint32_t m31_phy_outclksel; // 0x45C: M31_PHY_OUTCLKSEL
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__IO uint32_t m31_phy_xcfgi_31_0; // 0x460: M31_PHY_XCFGI_31_0
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__IO uint32_t m31_phy_xcfgi_63_32; // 0x464: M31_PHY_XCFGI_63_32
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__IO uint32_t m31_phy_xcfgi_95_64; // 0x468: M31_PHY_XCFGI_95_64
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__IO uint32_t m31_phy_xcfgi_127_96; // 0x46C: M31_PHY_XCFGI_127_96
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__IO uint32_t m31_phy_xcfgi_137_128; // 0x470: M31_PHY_XCFGI_137_128
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__IO uint32_t m31_phy_xcfg_hs_coarse_tune_num; // 0x474: M31_PHY_XCFG_HS_COARSE_TUNE_NUM
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__IO uint32_t m31_phy_xcfg_hs_fine_tune_num; // 0x478: M31_PHY_XCFG_HS_FINE_TUNE_NUM
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__IO uint32_t m31_phy_xcfg_fs_coarse_tune_num; // 0x47C: M31_PHY_XCFG_FS_COARSE_TUNE_NUM
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__IO uint32_t m31_phy_xcfg_fs_fine_tune_num; // 0x480: M31_PHY_XCFG_FS_FINE_TUNE_NUM
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__IO uint32_t m31_phy_xcfg_lock_range_max; // 0x484: M31_PHY_XCFG_LOCK_RANGE_MAX
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__IO uint32_t m31_phy_xcfgi_lock_range_min; // 0x488: M31_PHY_XCFGI_LOCK_RANGE_MIN
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__IO uint32_t m31_phy_xcfg_ob_rsel; // 0x48C: M31_PHY_XCFG_OB_RSEL
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__IO uint32_t m31_phy_xcfg_oc_rsel; // 0x490: M31_PHY_XCFG_OC_RSEL
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__IO uint32_t m31_phy_xcfgo; // 0x494: M31_PHY_XCFGO
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__IO uint32_t mxm_int; // 0x498: MXM_INT
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__IO uint32_t mxm_int_en; // 0x49C: MXM_INT_EN
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__IO uint32_t mxm_suspend; // 0x4A0: MXM_SUSPEND
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__IO uint32_t mxm_reg_a4; // 0x4A4: MXM_REG_A4
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musb_ep_csr_t ep_csr[16]; // 0x100-0x1FF: EP0-15 CSR
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} musb_regs_t;
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TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x4A8, "size is not correct");
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TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x200, "size is not correct");
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//--------------------------------------------------------------------+
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// Helper
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//--------------------------------------------------------------------+
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TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_regs, unsigned epnum) {
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musb_regs->index = epnum;
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return &musb_regs->indexed_csr;
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}
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the USB_O_FADDR register.
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@ -50,13 +50,6 @@
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"flasher": "openocd",
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"flasher_sn": "066FFF495087534867063844",
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"flasher_args": "-f interface/stlink.cfg -f target/stm32g0x.cfg"
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},
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{
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"name": "nanoch32v203",
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"uid": "CDAB277B0FBC03E339E339E3",
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"flasher": "openocd_wch",
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"flasher_sn": "EBCA8F0670AF",
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"flasher_args": ""
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}
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],
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"boards-skip": [
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@ -68,6 +61,13 @@
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"flasher_args": "-device MIMXRT1011xxx5A",
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"comment": "not running reliably in bulk with other boards, probably power, flashing etc .."
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},
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{
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"name": "nanoch32v203",
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"uid": "CDAB277B0FBC03E339E339E3",
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"flasher": "openocd_wch",
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"flasher_sn": "EBCA8F0670AF",
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"flasher_args": ""
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},
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{
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"name": "espressif_s3_devkitm",
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"uid": "84F703C084E4",
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