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use stock core_riscv.h for ch32 v2 v3
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/********************************** (C) COPYRIGHT *******************************
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* File Name : core_riscv.h
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* Author : WCH
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* Version : V1.0.0
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* Date : 2021/06/06
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* Description : RISC-V Core Peripheral Access Layer Header File for CH32V20x
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*********************************************************************************
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* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
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* Attention: This software (modified or not) and binary are used for
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* microcontroller manufactured by Nanjing Qinheng Microelectronics.
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*******************************************************************************/
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#ifndef __CORE_RISCV_H__
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#define __CORE_RISCV_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* IO definitions */
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#ifdef __cplusplus
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#define __I volatile /* defines 'read only' permissions */
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#else
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#define __I volatile const /* defines 'read only' permissions */
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#endif
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#define __O volatile /* defines 'write only' permissions */
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#define __IO volatile /* defines 'read / write' permissions */
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/* Standard Peripheral Library old types (maintained for legacy purpose) */
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typedef __I uint64_t vuc64; /* Read Only */
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typedef __I uint32_t vuc32; /* Read Only */
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typedef __I uint16_t vuc16; /* Read Only */
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typedef __I uint8_t vuc8; /* Read Only */
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typedef const uint64_t uc64; /* Read Only */
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typedef const uint32_t uc32; /* Read Only */
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typedef const uint16_t uc16; /* Read Only */
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typedef const uint8_t uc8; /* Read Only */
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typedef __I int64_t vsc64; /* Read Only */
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typedef __I int32_t vsc32; /* Read Only */
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typedef __I int16_t vsc16; /* Read Only */
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typedef __I int8_t vsc8; /* Read Only */
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typedef const int64_t sc64; /* Read Only */
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typedef const int32_t sc32; /* Read Only */
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typedef const int16_t sc16; /* Read Only */
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typedef const int8_t sc8; /* Read Only */
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typedef __IO uint64_t vu64;
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typedef __IO uint32_t vu32;
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typedef __IO uint16_t vu16;
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typedef __IO uint8_t vu8;
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typedef uint64_t u64;
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typedef uint32_t u32;
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typedef uint16_t u16;
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typedef uint8_t u8;
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typedef __IO int64_t vs64;
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typedef __IO int32_t vs32;
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typedef __IO int16_t vs16;
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typedef __IO int8_t vs8;
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typedef int64_t s64;
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typedef int32_t s32;
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typedef int16_t s16;
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typedef int8_t s8;
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typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
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typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
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#define RV_STATIC_INLINE static inline
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/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
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typedef struct{
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__I uint32_t ISR[8];
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__I uint32_t IPR[8];
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__IO uint32_t ITHRESDR;
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__IO uint32_t RESERVED;
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__IO uint32_t CFGR;
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__I uint32_t GISR;
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__IO uint8_t VTFIDR[4];
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uint8_t RESERVED0[12];
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__IO uint32_t VTFADDR[4];
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uint8_t RESERVED1[0x90];
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__O uint32_t IENR[8];
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uint8_t RESERVED2[0x60];
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__O uint32_t IRER[8];
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uint8_t RESERVED3[0x60];
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__O uint32_t IPSR[8];
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uint8_t RESERVED4[0x60];
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__O uint32_t IPRR[8];
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uint8_t RESERVED5[0x60];
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__IO uint32_t IACTR[8];
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uint8_t RESERVED6[0xE0];
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__IO uint8_t IPRIOR[256];
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uint8_t RESERVED7[0x810];
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__IO uint32_t SCTLR;
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}PFIC_Type;
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/* memory mapped structure for SysTick */
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typedef struct
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{
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__IO uint32_t CTLR;
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__IO uint32_t SR;
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__IO uint64_t CNT;
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__IO uint64_t CMP;
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}SysTick_Type;
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#define PFIC ((PFIC_Type *) 0xE000E000 )
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#define NVIC PFIC
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#define NVIC_KEY1 ((uint32_t)0xFA050000)
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#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
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#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
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#define SysTick ((SysTick_Type *) 0xE000F000)
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/*********************************************************************
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* @fn __enable_irq
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*
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* @brief Enable Global Interrupt
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq(void)
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{
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__asm volatile ("csrw 0x800, %0" : : "r" (0x6088) );
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}
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/*********************************************************************
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* @fn __disable_irq
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*
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* @brief Disable Global Interrupt
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq(void)
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{
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__asm volatile ("csrw 0x800, %0" : : "r" (0x6000) );
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}
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/*********************************************************************
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* @fn __NOP
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*
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* @brief nop
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP(void)
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{
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__asm volatile ("nop");
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}
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/*********************************************************************
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* @fn NVIC_EnableIRQ
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*
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* @brief Disable Interrupt
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
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{
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NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
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}
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/*********************************************************************
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* @fn NVIC_DisableIRQ
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*
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* @brief Disable Interrupt
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
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{
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NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
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}
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/*********************************************************************
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* @fn NVIC_GetStatusIRQ
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*
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* @brief Get Interrupt Enable State
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return 1 - Interrupt Pending Enable
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* 0 - Interrupt Pending Disable
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
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{
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return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
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}
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/*********************************************************************
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* @fn NVIC_GetPendingIRQ
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*
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* @brief Get Interrupt Pending State
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return 1 - Interrupt Pending Enable
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* 0 - Interrupt Pending Disable
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
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{
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return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
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}
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/*********************************************************************
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* @fn NVIC_SetPendingIRQ
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*
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* @brief Set Interrupt Pending
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
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{
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NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
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}
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/*********************************************************************
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* @fn NVIC_ClearPendingIRQ
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*
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* @brief Clear Interrupt Pending
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
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{
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NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
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}
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/*********************************************************************
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* @fn NVIC_GetActive
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*
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* @brief Get Interrupt Active State
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*
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* @param IRQn - Interrupt Numbers
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*
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* @return 1 - Interrupt Active
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* 0 - Interrupt No Active
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
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{
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return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
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}
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/*********************************************************************
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* @fn NVIC_SetPriority
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*
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* @brief Set Interrupt Priority
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*
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* @param IRQn - Interrupt Numbers
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* priority - bit7 - Pre-emption Priority
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* bit[6:5] - Subpriority
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
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{
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NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
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}
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/*********************************************************************
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* @fn __WFI
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*
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* @brief Wait for Interrupt
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
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{
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NVIC->SCTLR &= ~(1<<3); // wfi
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asm volatile ("wfi");
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}
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/*********************************************************************
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* @fn _SEV
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*
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* @brief Set Event
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
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{
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uint32_t t;
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t = NVIC->SCTLR;
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NVIC->SCTLR |= (1<<3)|(1<<5);
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NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
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}
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/*********************************************************************
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* @fn _WFE
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*
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* @brief Wait for Events
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
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{
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NVIC->SCTLR |= (1<<3);
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asm volatile ("wfi");
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}
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/*********************************************************************
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* @fn __WFE
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*
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* @brief Wait for Events
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
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{
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_SEV();
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_WFE();
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_WFE();
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}
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/*********************************************************************
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* @fn SetVTFIRQ
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*
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* @brief Set VTF Interrupt
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*
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* @param addr - VTF interrupt service function base address.
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* IRQn - Interrupt Numbers
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* num - VTF Interrupt Numbers
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* NewState - DISABLE or ENABLE
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
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if(num > 3) return ;
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if (NewState != DISABLE)
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{
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NVIC->VTFIDR[num] = IRQn;
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NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
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}
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else{
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NVIC->VTFIDR[num] = IRQn;
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NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
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}
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}
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/*********************************************************************
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* @fn NVIC_SystemReset
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*
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* @brief Initiate a system reset request
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*
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* @return none
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
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{
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NVIC->CFGR = NVIC_KEY3|(1<<7);
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}
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/*********************************************************************
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* @fn __AMOADD_W
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*
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* @brief Atomic Add with 32bit value
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* Atomically ADD 32bit value with value in memory using amoadd.d.
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*
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* @param addr - Address pointer to data, address need to be 4byte aligned
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* value - value to be ADDed
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*
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* @return return memory value + add value
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
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{
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int32_t result;
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__asm volatile ("amoadd.w %0, %2, %1" : \
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"=r"(result), "+A"(*addr) : "r"(value) : "memory");
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return *addr;
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}
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||||
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||||
/*********************************************************************
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* @fn __AMOAND_W
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*
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* @brief Atomic And with 32bit value
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* Atomically AND 32bit value with value in memory using amoand.d.
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*
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* @param addr - Address pointer to data, address need to be 4byte aligned
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* value - value to be ANDed
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*
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* @return return memory value & and value
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*/
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__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
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{
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int32_t result;
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__asm volatile ("amoand.w %0, %2, %1" : \
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"=r"(result), "+A"(*addr) : "r"(value) : "memory");
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return *addr;
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||||
}
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||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMAX_W
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||||
*
|
||||
* @brief Atomic signed MAX with 32bit value
|
||||
* Atomically signed max compare 32bit value with value in memory using amomax.d.
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||||
*
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||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return the bigger value
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||||
*/
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||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
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||||
{
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||||
int32_t result;
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||||
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__asm volatile ("amomax.w %0, %2, %1" : \
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"=r"(result), "+A"(*addr) : "r"(value) : "memory");
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||||
return *addr;
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||||
}
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||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMAXU_W
|
||||
*
|
||||
* @brief Atomic unsigned MAX with 32bit value
|
||||
* Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return return the bigger value
|
||||
*/
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||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
|
||||
{
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||||
uint32_t result;
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||||
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||||
__asm volatile ("amomaxu.w %0, %2, %1" : \
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"=r"(result), "+A"(*addr) : "r"(value) : "memory");
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||||
return *addr;
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||||
}
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||||
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||||
/*********************************************************************
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||||
* @fn __AMOMIN_W
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||||
*
|
||||
* @brief Atomic signed MIN with 32bit value
|
||||
* Atomically signed min compare 32bit value with value in memory using amomin.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return the smaller value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
|
||||
{
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||||
int32_t result;
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||||
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||||
__asm volatile ("amomin.w %0, %2, %1" : \
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||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMINU_W
|
||||
*
|
||||
* @brief Atomic unsigned MIN with 32bit value
|
||||
* Atomically unsigned min compare 32bit value with value in memory using amominu.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return the smaller value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile ("amominu.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOOR_W
|
||||
*
|
||||
* @brief Atomic OR with 32bit value
|
||||
* Atomically OR 32bit value with value in memory using amoor.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ORed
|
||||
*
|
||||
* @return return memory value | and value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amoor.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOSWAP_W
|
||||
*
|
||||
* @brief Atomically swap new 32bit value into memory using amoswap.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* newval - New value to be stored into the address
|
||||
*
|
||||
* @return return the original value in memory
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile ("amoswap.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(newval) : "memory");
|
||||
return result;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOXOR_W
|
||||
*
|
||||
* @brief Atomic XOR with 32bit value
|
||||
* Atomically XOR 32bit value with value in memory using amoxor.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be XORed
|
||||
*
|
||||
* @return return memory value ^ and value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amoxor.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/* Core_Exported_Functions */
|
||||
extern uint32_t __get_MSTATUS(void);
|
||||
extern void __set_MSTATUS(uint32_t value);
|
||||
extern uint32_t __get_MISA(void);
|
||||
extern void __set_MISA(uint32_t value);
|
||||
extern uint32_t __get_MTVEC(void);
|
||||
extern void __set_MTVEC(uint32_t value);
|
||||
extern uint32_t __get_MSCRATCH(void);
|
||||
extern void __set_MSCRATCH(uint32_t value);
|
||||
extern uint32_t __get_MEPC(void);
|
||||
extern void __set_MEPC(uint32_t value);
|
||||
extern uint32_t __get_MCAUSE(void);
|
||||
extern void __set_MCAUSE(uint32_t value);
|
||||
extern uint32_t __get_MTVAL(void);
|
||||
extern void __set_MTVAL(uint32_t value);
|
||||
extern uint32_t __get_MVENDORID(void);
|
||||
extern uint32_t __get_MARCHID(void);
|
||||
extern uint32_t __get_MIMPID(void);
|
||||
extern uint32_t __get_MHARTID(void);
|
||||
extern uint32_t __get_SP(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
@ -1,6 +1,18 @@
|
||||
#include <stdio.h>
|
||||
|
||||
// https://github.com/openwch/ch32v307/pull/90
|
||||
// https://github.com/openwch/ch32v20x/pull/12
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wstrict-prototypes"
|
||||
#endif
|
||||
|
||||
#include "ch32v20x.h"
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#include "bsp/board_api.h"
|
||||
#include "board.h"
|
||||
|
||||
|
@ -49,6 +49,7 @@ function(add_board_target BOARD_TARGET)
|
||||
${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
|
||||
)
|
||||
target_include_directories(${BOARD_TARGET} PUBLIC
|
||||
${SDK_SRC_DIR}/Core
|
||||
${SDK_SRC_DIR}/Peripheral/inc
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
|
||||
)
|
||||
|
@ -24,6 +24,9 @@ CFLAGS += \
|
||||
-DCH32V20x_${MCU_VARIANT} \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_CH32V20X
|
||||
|
||||
# https://github.com/openwch/ch32v20x/pull/12
|
||||
CFLAGS += -Wno-error=strict-prototypes
|
||||
|
||||
ifeq ($(PORT),0)
|
||||
$(info "Using FSDEV driver")
|
||||
CFLAGS += -DCFG_TUD_WCH_USBIP_FSDEV=1
|
||||
@ -51,6 +54,7 @@ SRC_S += $(SDK_SRC_DIR)/Startup/startup_ch32v20x_${MCU_VARIANT}.S
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(BOARD_PATH) \
|
||||
$(TOP)/$(SDK_SRC_DIR)/Core \
|
||||
$(TOP)/$(SDK_SRC_DIR)/Peripheral/inc \
|
||||
|
||||
FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
|
||||
|
@ -1,379 +0,0 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : core_riscv.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2021/06/06
|
||||
* Description : RISC-V Core Peripheral Access Layer Header File for CH32V30x
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*******************************************************************************/
|
||||
#ifndef __CORE_RISCV_H__
|
||||
#define __CORE_RISCV_H__
|
||||
|
||||
/* IO definitions */
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /* defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /* defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /* defines 'write only' permissions */
|
||||
#define __IO volatile /* defines 'read / write' permissions */
|
||||
|
||||
/* Standard Peripheral Library old types (maintained for legacy purpose) */
|
||||
typedef __I uint64_t vuc64; /* Read Only */
|
||||
typedef __I uint32_t vuc32; /* Read Only */
|
||||
typedef __I uint16_t vuc16; /* Read Only */
|
||||
typedef __I uint8_t vuc8; /* Read Only */
|
||||
|
||||
typedef const uint64_t uc64; /* Read Only */
|
||||
typedef const uint32_t uc32; /* Read Only */
|
||||
typedef const uint16_t uc16; /* Read Only */
|
||||
typedef const uint8_t uc8; /* Read Only */
|
||||
|
||||
typedef __I int64_t vsc64; /* Read Only */
|
||||
typedef __I int32_t vsc32; /* Read Only */
|
||||
typedef __I int16_t vsc16; /* Read Only */
|
||||
typedef __I int8_t vsc8; /* Read Only */
|
||||
|
||||
typedef const int64_t sc64; /* Read Only */
|
||||
typedef const int32_t sc32; /* Read Only */
|
||||
typedef const int16_t sc16; /* Read Only */
|
||||
typedef const int8_t sc8; /* Read Only */
|
||||
|
||||
typedef __IO uint64_t vu64;
|
||||
typedef __IO uint32_t vu32;
|
||||
typedef __IO uint16_t vu16;
|
||||
typedef __IO uint8_t vu8;
|
||||
|
||||
typedef uint64_t u64;
|
||||
typedef uint32_t u32;
|
||||
typedef uint16_t u16;
|
||||
typedef uint8_t u8;
|
||||
|
||||
typedef __IO int64_t vs64;
|
||||
typedef __IO int32_t vs32;
|
||||
typedef __IO int16_t vs16;
|
||||
typedef __IO int8_t vs8;
|
||||
|
||||
typedef int64_t s64;
|
||||
typedef int32_t s32;
|
||||
typedef int16_t s16;
|
||||
typedef int8_t s8;
|
||||
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
|
||||
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
|
||||
|
||||
#define RV_STATIC_INLINE static inline
|
||||
|
||||
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
|
||||
typedef struct{
|
||||
__I uint32_t ISR[8];
|
||||
__I uint32_t IPR[8];
|
||||
__IO uint32_t ITHRESDR;
|
||||
__IO uint32_t RESERVED;
|
||||
__IO uint32_t CFGR;
|
||||
__I uint32_t GISR;
|
||||
uint8_t VTFIDR[4];
|
||||
uint8_t RESERVED0[12];
|
||||
__IO uint32_t VTFADDR[4];
|
||||
uint8_t RESERVED1[0x90];
|
||||
__O uint32_t IENR[8];
|
||||
uint8_t RESERVED2[0x60];
|
||||
__O uint32_t IRER[8];
|
||||
uint8_t RESERVED3[0x60];
|
||||
__O uint32_t IPSR[8];
|
||||
uint8_t RESERVED4[0x60];
|
||||
__O uint32_t IPRR[8];
|
||||
uint8_t RESERVED5[0x60];
|
||||
__IO uint32_t IACTR[8];
|
||||
uint8_t RESERVED6[0xE0];
|
||||
__IO uint8_t IPRIOR[256];
|
||||
uint8_t RESERVED7[0x810];
|
||||
__IO uint32_t SCTLR;
|
||||
}PFIC_Type;
|
||||
|
||||
/* memory mapped structure for SysTick */
|
||||
typedef struct
|
||||
{
|
||||
__IO u32 CTLR;
|
||||
__IO u32 SR;
|
||||
__IO u64 CNT;
|
||||
__IO u64 CMP;
|
||||
}SysTick_Type;
|
||||
|
||||
|
||||
#define PFIC ((PFIC_Type *) 0xE000E000 )
|
||||
#define NVIC PFIC
|
||||
#define NVIC_KEY1 ((uint32_t)0xFA050000)
|
||||
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
|
||||
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
|
||||
|
||||
#define SysTick ((SysTick_Type *) 0xE000F000)
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __enable_irq
|
||||
*
|
||||
* @brief Enable Global Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
RV_STATIC_INLINE void __enable_irq(void)
|
||||
{
|
||||
__asm volatile ("csrw 0x800, %0" : : "r" (0x6088) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __disable_irq
|
||||
*
|
||||
* @brief Disable Global Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
RV_STATIC_INLINE void __disable_irq(void)
|
||||
{
|
||||
__asm volatile ("csrw 0x800, %0" : : "r" (0x6000) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __NOP
|
||||
*
|
||||
* @brief nop
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
RV_STATIC_INLINE void __NOP(void)
|
||||
{
|
||||
__asm volatile ("nop");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_EnableIRQ
|
||||
*
|
||||
* @brief Enable Interrupt
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_DisableIRQ
|
||||
*
|
||||
* @brief Disable Interrupt
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetStatusIRQ
|
||||
*
|
||||
* @brief Get Interrupt Enable State
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Enable
|
||||
* 0 - Interrupt Disable
|
||||
*/
|
||||
RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetPendingIRQ
|
||||
*
|
||||
* @brief Get Interrupt Pending State
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Pending Enable
|
||||
* 0 - Interrupt Pending Disable
|
||||
*/
|
||||
RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPendingIRQ
|
||||
*
|
||||
* @brief Set Interrupt Pending
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_ClearPendingIRQ
|
||||
*
|
||||
* @brief Clear Interrupt Pending
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetActive
|
||||
*
|
||||
* @brief Get Interrupt Active State
|
||||
*
|
||||
* @param IRQn: Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Active
|
||||
* 0 - Interrupt No Active
|
||||
*/
|
||||
RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPriority
|
||||
*
|
||||
* @brief Set Interrupt Priority
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
* priority -
|
||||
* bit7 - pre-emption priority
|
||||
* bit6~bit4 - subpriority
|
||||
* @return None
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
|
||||
{
|
||||
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFI
|
||||
*
|
||||
* @brief Wait for Interrupt
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
NVIC->SCTLR &= ~(1<<3); // wfi
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFE
|
||||
*
|
||||
* @brief Wait for Events
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
uint32_t t;
|
||||
|
||||
t = NVIC->SCTLR;
|
||||
NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev)
|
||||
NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
|
||||
asm volatile ("wfi");
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetVTFIRQ
|
||||
*
|
||||
* @brief Set VTF Interrupt
|
||||
*
|
||||
* @param add - VTF interrupt service function base address.
|
||||
* IRQn -Interrupt Numbers
|
||||
* num - VTF Interrupt Numbers
|
||||
* NewState - DISABLE or ENABLE
|
||||
* @return None
|
||||
*/
|
||||
RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
|
||||
if(num > 3) return ;
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
NVIC->VTFIDR[num] = IRQn;
|
||||
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
|
||||
}
|
||||
else{
|
||||
NVIC->VTFIDR[num] = IRQn;
|
||||
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SystemReset
|
||||
*
|
||||
* @brief Initiate a system reset request
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
RV_STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY3|(1<<7);
|
||||
}
|
||||
|
||||
|
||||
/* Core_Exported_Functions */
|
||||
extern uint32_t __get_FFLAGS(void);
|
||||
extern void __set_FFLAGS(uint32_t value);
|
||||
extern uint32_t __get_FRM(void);
|
||||
extern void __set_FRM(uint32_t value);
|
||||
extern uint32_t __get_FCSR(void);
|
||||
extern void __set_FCSR(uint32_t value);
|
||||
extern uint32_t __get_MSTATUS(void);
|
||||
extern void __set_MSTATUS(uint32_t value);
|
||||
extern uint32_t __get_MISA(void);
|
||||
extern void __set_MISA(uint32_t value);
|
||||
extern uint32_t __get_MIE(void);
|
||||
extern void __set_MIE(uint32_t value);
|
||||
extern uint32_t __get_MTVEC(void);
|
||||
extern void __set_MTVEC(uint32_t value);
|
||||
extern uint32_t __get_MSCRATCH(void);
|
||||
extern void __set_MSCRATCH(uint32_t value);
|
||||
extern uint32_t __get_MEPC(void);
|
||||
extern void __set_MEPC(uint32_t value);
|
||||
extern uint32_t __get_MCAUSE(void);
|
||||
extern void __set_MCAUSE(uint32_t value);
|
||||
extern uint32_t __get_MTVAL(void);
|
||||
extern void __set_MTVAL(uint32_t value);
|
||||
extern uint32_t __get_MIP(void);
|
||||
extern void __set_MIP(uint32_t value);
|
||||
extern uint32_t __get_MCYCLE(void);
|
||||
extern void __set_MCYCLE(uint32_t value);
|
||||
extern uint32_t __get_MCYCLEH(void);
|
||||
extern void __set_MCYCLEH(uint32_t value);
|
||||
extern uint32_t __get_MINSTRET(void);
|
||||
extern void __set_MINSTRET(uint32_t value);
|
||||
extern uint32_t __get_MINSTRETH(void);
|
||||
extern void __set_MINSTRETH(uint32_t value);
|
||||
extern uint32_t __get_MVENDORID(void);
|
||||
extern uint32_t __get_MARCHID(void);
|
||||
extern uint32_t __get_MIMPID(void);
|
||||
extern uint32_t __get_MHARTID(void);
|
||||
extern uint32_t __get_SP(void);
|
||||
|
||||
|
||||
#endif
|
@ -25,8 +25,17 @@
|
||||
*/
|
||||
|
||||
#include "debug_uart.h"
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wstrict-prototypes"
|
||||
#endif
|
||||
|
||||
#include <ch32v30x.h>
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#define UART_RINGBUFFER_SIZE_TX 128
|
||||
#define UART_RINGBUFFER_MASK_TX (UART_RINGBUFFER_SIZE_TX-1)
|
||||
|
@ -25,9 +25,22 @@
|
||||
*/
|
||||
|
||||
#include "stdio.h"
|
||||
|
||||
// https://github.com/openwch/ch32v307/pull/90
|
||||
// https://github.com/openwch/ch32v20x/pull/12
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wstrict-prototypes"
|
||||
#endif
|
||||
|
||||
#include "debug_uart.h"
|
||||
#include "ch32v30x.h"
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#include "bsp/board_api.h"
|
||||
#include "board.h"
|
||||
|
||||
|
@ -49,6 +49,7 @@ function(add_board_target BOARD_TARGET)
|
||||
${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
|
||||
)
|
||||
target_include_directories(${BOARD_TARGET} PUBLIC
|
||||
${SDK_SRC_DIR}/Core
|
||||
${SDK_SRC_DIR}/Peripheral/inc
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}
|
||||
)
|
||||
|
@ -25,6 +25,9 @@ CFLAGS += \
|
||||
-fsigned-char \
|
||||
-DCFG_TUSB_MCU=OPT_MCU_CH32V307 \
|
||||
|
||||
# https://github.com/openwch/ch32v307/pull/90
|
||||
CFLAGS += -Wno-error=strict-prototypes
|
||||
|
||||
ifeq ($(SPEED),high)
|
||||
$(info "Using USBHS driver for HighSpeed mode")
|
||||
CFLAGS += -DCFG_TUD_WCH_USBIP_USBHS=1
|
||||
@ -51,6 +54,7 @@ SRC_S += \
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(BOARD_PATH) \
|
||||
$(TOP)/$(SDK_SRC_DIR)/Core \
|
||||
$(TOP)/$(SDK_SRC_DIR)/Peripheral/inc
|
||||
|
||||
# For freeRTOS port source
|
||||
|
@ -36,13 +36,23 @@
|
||||
|
||||
#include "common/tusb_compiler.h"
|
||||
|
||||
// https://github.com/openwch/ch32v307/pull/90
|
||||
// https://github.com/openwch/ch32v20x/pull/12
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wstrict-prototypes"
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_MCU == OPT_MCU_CH32V20X
|
||||
#include <ch32v20x.h>
|
||||
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_CH32F20X
|
||||
#include <ch32f20x.h>
|
||||
#endif
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
#define FSDEV_PMA_SIZE (512u)
|
||||
|
||||
// volatile 32-bit aligned
|
||||
|
@ -28,6 +28,13 @@
|
||||
#ifndef USB_CH32_USBFS_REG_H
|
||||
#define USB_CH32_USBFS_REG_H
|
||||
|
||||
// https://github.com/openwch/ch32v307/pull/90
|
||||
// https://github.com/openwch/ch32v20x/pull/12
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wstrict-prototypes"
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_MCU == OPT_MCU_CH32V307
|
||||
#include <ch32v30x.h>
|
||||
#define USBHD_IRQn OTG_FS_IRQn
|
||||
@ -39,6 +46,10 @@
|
||||
#include <ch32f20x.h>
|
||||
#endif
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
// CTRL
|
||||
#define USBFS_CTRL_DMA_EN (1 << 0)
|
||||
#define USBFS_CTRL_CLR_ALL (1 << 1)
|
||||
|
@ -28,12 +28,24 @@
|
||||
#ifndef USB_CH32_USBHS_REG_H
|
||||
#define USB_CH32_USBHS_REG_H
|
||||
|
||||
// https://github.com/openwch/ch32v307/pull/90
|
||||
// https://github.com/openwch/ch32v20x/pull/12
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wstrict-prototypes"
|
||||
#endif
|
||||
|
||||
#if CFG_TUSB_MCU == OPT_MCU_CH32V307
|
||||
#include <ch32v30x.h>
|
||||
#elif CFG_TUSB_MCU == OPT_MCU_CH32F20X
|
||||
#include <ch32f20x.h>
|
||||
#endif
|
||||
|
||||
#ifdef __GNUC__
|
||||
#pragma GCC diagnostic pop
|
||||
#endif
|
||||
|
||||
|
||||
/******************* GLOBAL ******************/
|
||||
|
||||
// USB CONTROL
|
||||
|
Loading…
x
Reference in New Issue
Block a user