mirror of
https://github.com/hathach/tinyusb.git
synced 2025-03-23 13:20:54 +00:00
add imxrt1170 evkb
This commit is contained in:
hathach
parent
9ffb20429a
commit
2e924f727f
examples/device/cdc_msc/src
hw/bsp/imxrt
@ -39,7 +39,7 @@
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* - 1000 ms : device mounted
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* - 2500 ms : device is suspended
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*/
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enum {
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enum {
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BLINK_NOT_MOUNTED = 250,
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BLINK_MOUNTED = 1000,
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BLINK_SUSPENDED = 2500,
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@ -51,8 +51,7 @@ void led_blinking_task(void);
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void cdc_task(void);
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/*------------- MAIN -------------*/
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int main(void)
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{
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int main(void) {
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board_init();
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// init device stack on configured roothub port
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@ -62,8 +61,7 @@ int main(void)
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board_init_after_tusb();
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}
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while (1)
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{
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while (1) {
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tud_task(); // tinyusb device task
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led_blinking_task();
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@ -76,29 +74,25 @@ int main(void)
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//--------------------------------------------------------------------+
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// Invoked when device is mounted
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void tud_mount_cb(void)
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{
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void tud_mount_cb(void) {
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blink_interval_ms = BLINK_MOUNTED;
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}
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// Invoked when device is unmounted
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void tud_umount_cb(void)
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{
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void tud_umount_cb(void) {
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blink_interval_ms = BLINK_NOT_MOUNTED;
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}
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// Invoked when usb bus is suspended
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// remote_wakeup_en : if host allow us to perform remote wakeup
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// Within 7ms, device must draw an average of current less than 2.5 mA from bus
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void tud_suspend_cb(bool remote_wakeup_en)
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{
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void tud_suspend_cb(bool remote_wakeup_en) {
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(void) remote_wakeup_en;
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blink_interval_ms = BLINK_SUSPENDED;
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}
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// Invoked when usb bus is resumed
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void tud_resume_cb(void)
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{
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void tud_resume_cb(void) {
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blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED;
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}
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@ -106,15 +100,13 @@ void tud_resume_cb(void)
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//--------------------------------------------------------------------+
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// USB CDC
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//--------------------------------------------------------------------+
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void cdc_task(void)
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{
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void cdc_task(void) {
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// connected() check for DTR bit
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// Most but not all terminal client set this when making connection
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// if ( tud_cdc_connected() )
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{
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// connected and there are data available
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if ( tud_cdc_available() )
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{
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if (tud_cdc_available()) {
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// read data
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char buf[64];
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uint32_t count = tud_cdc_read(buf, sizeof(buf));
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@ -131,37 +123,32 @@ void cdc_task(void)
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}
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// Invoked when cdc when line state changed e.g connected/disconnected
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void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts)
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{
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void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts) {
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(void) itf;
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(void) rts;
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// TODO set some indicator
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if ( dtr )
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{
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if (dtr) {
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// Terminal connected
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}else
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{
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} else {
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// Terminal disconnected
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}
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}
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// Invoked when CDC interface received data from host
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void tud_cdc_rx_cb(uint8_t itf)
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{
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void tud_cdc_rx_cb(uint8_t itf) {
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(void) itf;
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}
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//--------------------------------------------------------------------+
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// BLINKING TASK
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//--------------------------------------------------------------------+
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void led_blinking_task(void)
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{
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void led_blinking_task(void) {
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static uint32_t start_ms = 0;
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static bool led_state = false;
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// Blink every interval ms
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if ( board_millis() - start_ms < blink_interval_ms) return; // not enough time
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if (board_millis() - start_ms < blink_interval_ms) return; // not enough time
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start_ms += blink_interval_ms;
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board_led_write(led_state);
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@ -17,7 +17,7 @@
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******************************************************************************/
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
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__attribute__((section(".boot_hdr.conf")))
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__attribute__((section(".boot_hdr.conf"), used))
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#elif defined(__ICCARM__)
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#pragma location = ".boot_hdr.conf"
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#endif
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17
hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake
Normal file
17
hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake
Normal file
@ -0,0 +1,17 @@
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set(MCU_VARIANT MIMXRT1176)
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set(MCU_CORE _cm7)
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set(JLINK_DEVICE MIMXRT1176xxxA_M7)
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set(PYOCD_TARGET mimxrt1170_cm7)
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set(NXPLINK_DEVICE MIMXRT1176xxxxx:MIMXRT1170-EVK)
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function(update_board TARGET)
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target_sources(${TARGET} PUBLIC
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkbmimxrt1170_flexspi_nor_config.c
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)
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target_compile_definitions(${TARGET} PUBLIC
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CPU_MIMXRT1176DVMAA_cm7
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BOARD_TUD_RHPORT=0
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BOARD_TUH_RHPORT=1
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)
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endfunction()
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55
hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h
Normal file
55
hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h
Normal file
@ -0,0 +1,55 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2019, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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// required since iMX RT10xx SDK include this file for board size
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#define BOARD_FLASH_SIZE (0x1000000U)
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// LED
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#define LED_PINMUX IOMUXC_GPIO_AD_04_GPIO9_IO03
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#define LED_PORT GPIO9
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#define LED_PIN 3
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#define LED_STATE_ON 0
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// SW8 button
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#define BUTTON_PINMUX IOMUXC_WAKEUP_DIG_GPIO13_IO00
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#define BUTTON_PORT GPIO13
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#define BUTTON_PIN 0
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#define BUTTON_STATE_ACTIVE 0
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// UART
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#define UART_PORT LPUART1
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#define UART_RX_PINMUX IOMUXC_GPIO_AD_B0_13_LPUART1_RX
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#define UART_TX_PINMUX IOMUXC_GPIO_AD_B0_12_LPUART1_TX
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static inline uint32_t board_uart_get_clock(void) {
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return CLOCK_GetRootClockFreq(kCLOCK_Root_Lpuart1);
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}
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#endif /* BOARD_H_ */
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15
hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk
Normal file
15
hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk
Normal file
@ -0,0 +1,15 @@
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CFLAGS += -DCPU_MIMXRT1176DVMAA_cm7
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MCU_VARIANT = MIMXRT1176
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MCU_CORE = _cm7
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# For flash-jlink target
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JLINK_DEVICE = MIMXRT1176xxxA_M7
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# For flash-pyocd target
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PYOCD_TARGET = mimxrt1170_cm7
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BOARD_TUD_RHPORT = 0
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BOARD_TUH_RHPORT = 1
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# flash using pyocd
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flash: flash-pyocd
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877
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c
Normal file
877
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c
Normal file
@ -0,0 +1,877 @@
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
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*
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* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
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*
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* 3. Call CLOCK_SetRootClock() to configure corresponding module clock source and divider.
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*
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*/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v11.0
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processor: MIMXRT1176xxxxx
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package_id: MIMXRT1176DVMAA
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mcu_data: ksdk2_0
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processor_version: 13.0.2
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board: MIMXRT1170-EVKB
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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#include "clock_config.h"
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#include "fsl_iomuxc.h"
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#include "fsl_dcdc.h"
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#include "fsl_pmu.h"
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#include "fsl_clock.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockRUN();
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}
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#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
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#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
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/* This function should not run from SDRAM since it will change SEMC configuration. */
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AT_QUICKACCESS_SECTION_CODE(void UpdateSemcClock(void));
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void UpdateSemcClock(void)
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{
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/* Enable self-refresh mode and update semc clock root to 200MHz. */
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SEMC->IPCMD = 0xA55A000D;
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while ((SEMC->INTR & 0x3) == 0)
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;
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SEMC->INTR = 0x3;
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SEMC->DCCR = 0x0B;
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/*
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* Currently we are using SEMC parameter which fit both 166MHz and 200MHz, only
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* need to change the SEMC clock root here. If customer is using their own DCD and
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* want to switch from 166MHz to 200MHz, extra SEMC configuration might need to be
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* adjusted here to fine tune the SDRAM performance
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*/
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CCM->CLOCK_ROOT[kCLOCK_Root_Semc].CONTROL = 0x602;
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}
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#endif
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#endif
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/*******************************************************************************
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********************** Configuration BOARD_BootClockRUN ***********************
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******************************************************************************/
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockRUN
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called_from_default_init: true
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outputs:
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- {id: ACMP_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: ADC1_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: ADC2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: ARM_PLL_CLK.outFreq, value: 996 MHz}
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- {id: ASRC_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: AXI_CLK_ROOT.outFreq, value: 996 MHz}
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- {id: BUS_CLK_ROOT.outFreq, value: 240 MHz}
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- {id: BUS_LPSR_CLK_ROOT.outFreq, value: 160 MHz}
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- {id: CAN1_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: CAN2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: CAN3_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: CCM_CLKO1_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: CCM_CLKO2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: CLK_1M.outFreq, value: 1 MHz}
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- {id: CSI2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: CSI2_ESC_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: CSI2_UI_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: CSI_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: CSSYS_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: CSTRACE_CLK_ROOT.outFreq, value: 132 MHz}
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- {id: ELCDIF_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: EMV1_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: EMV2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: ENET1_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: ENET2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: ENET_1G_TX_CLK.outFreq, value: 24 MHz}
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- {id: ENET_25M_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: ENET_QOS_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: ENET_TIMER1_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: ENET_TIMER2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: ENET_TIMER3_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: FLEXIO1_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: FLEXIO2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: FLEXSPI1_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: GC355_CLK_ROOT.outFreq, value: 492.0000125 MHz}
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- {id: GPT1_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
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- {id: GPT2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
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- {id: GPT3_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: GPT3_ipg_clk_highfreq.outFreq, value: 24 MHz}
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- {id: GPT4_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: GPT4_ipg_clk_highfreq.outFreq, value: 24 MHz}
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- {id: GPT5_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: GPT5_ipg_clk_highfreq.outFreq, value: 24 MHz}
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- {id: GPT6_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: GPT6_ipg_clk_highfreq.outFreq, value: 24 MHz}
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- {id: LCDIFV2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPI2C1_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPI2C2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPI2C3_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPI2C4_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPI2C5_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPI2C6_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPSPI1_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPSPI2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPSPI3_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPSPI4_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPSPI5_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPSPI6_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPUART10_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPUART11_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPUART12_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPUART1_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPUART2_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPUART3_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPUART4_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPUART5_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPUART6_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPUART7_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPUART8_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: LPUART9_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: M4_CLK_ROOT.outFreq, value: 4320/11 MHz}
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- {id: M4_SYSTICK_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: M7_CLK_ROOT.outFreq, value: 996 MHz}
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- {id: M7_SYSTICK_CLK_ROOT.outFreq, value: 100 kHz}
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- {id: MIC_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: MIPI_DSI_TX_CLK_ESC_ROOT.outFreq, value: 24 MHz}
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- {id: MIPI_ESC_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: MIPI_REF_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: MQS_CLK_ROOT.outFreq, value: 24 MHz}
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- {id: MQS_MCLK.outFreq, value: 24 MHz}
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- {id: OSC_24M.outFreq, value: 24 MHz}
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- {id: OSC_32K.outFreq, value: 32.768 kHz}
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- {id: OSC_RC_16M.outFreq, value: 16 MHz}
|
||||
- {id: OSC_RC_400M.outFreq, value: 400 MHz}
|
||||
- {id: OSC_RC_48M.outFreq, value: 48 MHz}
|
||||
- {id: OSC_RC_48M_DIV2.outFreq, value: 24 MHz}
|
||||
- {id: PLL_VIDEO_CLK.outFreq, value: 984.000025 MHz}
|
||||
- {id: SAI1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||
- {id: SAI1_MCLK1.outFreq, value: 24 MHz}
|
||||
- {id: SAI1_MCLK3.outFreq, value: 24 MHz}
|
||||
- {id: SAI2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||
- {id: SAI2_MCLK1.outFreq, value: 24 MHz}
|
||||
- {id: SAI2_MCLK3.outFreq, value: 24 MHz}
|
||||
- {id: SAI3_CLK_ROOT.outFreq, value: 24 MHz}
|
||||
- {id: SAI3_MCLK1.outFreq, value: 24 MHz}
|
||||
- {id: SAI3_MCLK3.outFreq, value: 24 MHz}
|
||||
- {id: SAI4_CLK_ROOT.outFreq, value: 24 MHz}
|
||||
- {id: SAI4_MCLK1.outFreq, value: 24 MHz}
|
||||
- {id: SEMC_CLK_ROOT.outFreq, value: 198 MHz}
|
||||
- {id: SPDIF_CLK_ROOT.outFreq, value: 24 MHz}
|
||||
- {id: SYS_PLL2_CLK.outFreq, value: 528 MHz}
|
||||
- {id: SYS_PLL2_PFD0_CLK.outFreq, value: 352 MHz}
|
||||
- {id: SYS_PLL2_PFD1_CLK.outFreq, value: 594 MHz}
|
||||
- {id: SYS_PLL2_PFD2_CLK.outFreq, value: 396 MHz}
|
||||
- {id: SYS_PLL2_PFD3_CLK.outFreq, value: 297 MHz}
|
||||
- {id: SYS_PLL3_CLK.outFreq, value: 480 MHz}
|
||||
- {id: SYS_PLL3_DIV2_CLK.outFreq, value: 240 MHz}
|
||||
- {id: SYS_PLL3_PFD0_CLK.outFreq, value: 8640/13 MHz}
|
||||
- {id: SYS_PLL3_PFD1_CLK.outFreq, value: 8640/17 MHz}
|
||||
- {id: SYS_PLL3_PFD2_CLK.outFreq, value: 270 MHz}
|
||||
- {id: SYS_PLL3_PFD3_CLK.outFreq, value: 4320/11 MHz}
|
||||
- {id: USDHC1_CLK_ROOT.outFreq, value: 24 MHz}
|
||||
- {id: USDHC2_CLK_ROOT.outFreq, value: 24 MHz}
|
||||
settings:
|
||||
- {id: CoreBusClockRootsInitializationConfig, value: selectedCore}
|
||||
- {id: SOCDomainVoltage, value: OD}
|
||||
- {id: ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG, value: Low}
|
||||
- {id: ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG, value: Enabled}
|
||||
- {id: ANADIG_PLL.PLL_AUDIO_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
|
||||
- {id: ANADIG_PLL.PLL_VIDEO.denom, value: '960000'}
|
||||
- {id: ANADIG_PLL.PLL_VIDEO.div, value: '41'}
|
||||
- {id: ANADIG_PLL.PLL_VIDEO.num, value: '1'}
|
||||
- {id: ANADIG_PLL.SYS_PLL1_BYPASS.sel, value: ANADIG_OSC.OSC_24M}
|
||||
- {id: ANADIG_PLL.SYS_PLL2.denom, value: '268435455'}
|
||||
- {id: ANADIG_PLL.SYS_PLL2.div, value: '22'}
|
||||
- {id: ANADIG_PLL.SYS_PLL2.num, value: '0'}
|
||||
- {id: ANADIG_PLL.SYS_PLL2_SS_DIV.scale, value: '268435455'}
|
||||
- {id: ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale, value: '22', locked: true}
|
||||
- {id: ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale, value: '18', locked: true}
|
||||
- {id: ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG, value: Enabled}
|
||||
- {id: ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG, value: Disabled}
|
||||
- {id: ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG, value: Enabled}
|
||||
- {id: ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG, value: Disabled}
|
||||
- {id: ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG, value: Disabled}
|
||||
- {id: ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG, value: Enabled}
|
||||
- {id: ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG, value: Enabled}
|
||||
- {id: ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG, value: Enabled}
|
||||
- {id: CCM.CLOCK_ROOT0.MUX.sel, value: ANADIG_PLL.ARM_PLL_CLK}
|
||||
- {id: CCM.CLOCK_ROOT1.MUX.sel, value: ANADIG_PLL.SYS_PLL3_PFD3_CLK}
|
||||
- {id: CCM.CLOCK_ROOT2.DIV.scale, value: '2'}
|
||||
- {id: CCM.CLOCK_ROOT2.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
|
||||
- {id: CCM.CLOCK_ROOT25.DIV.scale, value: '22'}
|
||||
- {id: CCM.CLOCK_ROOT25.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
|
||||
- {id: CCM.CLOCK_ROOT26.DIV.scale, value: '22'}
|
||||
- {id: CCM.CLOCK_ROOT26.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
|
||||
- {id: CCM.CLOCK_ROOT3.DIV.scale, value: '3'}
|
||||
- {id: CCM.CLOCK_ROOT3.MUX.sel, value: ANADIG_PLL.SYS_PLL3_CLK}
|
||||
- {id: CCM.CLOCK_ROOT4.DIV.scale, value: '3'}
|
||||
- {id: CCM.CLOCK_ROOT4.MUX.sel, value: ANADIG_PLL.SYS_PLL2_PFD1_CLK}
|
||||
- {id: CCM.CLOCK_ROOT6.DIV.scale, value: '4'}
|
||||
- {id: CCM.CLOCK_ROOT6.MUX.sel, value: ANADIG_PLL.SYS_PLL2_CLK}
|
||||
- {id: CCM.CLOCK_ROOT68.DIV.scale, value: '2'}
|
||||
- {id: CCM.CLOCK_ROOT68.MUX.sel, value: ANADIG_PLL.PLL_VIDEO_CLK}
|
||||
- {id: CCM.CLOCK_ROOT8.DIV.scale, value: '240'}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef SKIP_POWER_ADJUSTMENT
|
||||
#if __CORTEX_M == 7
|
||||
#define BYPASS_LDO_LPSR 1
|
||||
#define SKIP_LDO_ADJUSTMENT 1
|
||||
#elif __CORTEX_M == 4
|
||||
#define SKIP_DCDC_ADJUSTMENT 1
|
||||
#define SKIP_FBB_ENABLE 1
|
||||
#endif
|
||||
#endif
|
||||
|
||||
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.postDivider = kCLOCK_PllPostDiv2, /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */
|
||||
.loopDivider = 166, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */
|
||||
};
|
||||
|
||||
const clock_sys_pll2_config_t sysPll2Config_BOARD_BootClockRUN =
|
||||
{
|
||||
.mfd = 268435455, /* Denominator of spread spectrum */
|
||||
.ss = NULL, /* Spread spectrum parameter */
|
||||
.ssEnable = false, /* Enable spread spectrum or not */
|
||||
};
|
||||
|
||||
const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
|
||||
{
|
||||
.loopDivider = 41, /* PLL Loop divider, valid range for DIV_SELECT divider value: 27 ~ 54. */
|
||||
.postDivider = 0, /* Divider after PLL, should only be 1, 2, 4, 8, 16, 32 */
|
||||
.numerator = 1, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||
.denominator = 960000, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
|
||||
.ss = NULL, /* Spread spectrum parameter */
|
||||
.ssEnable = false, /* Enable spread spectrum or not */
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockRUN(void)
|
||||
{
|
||||
clock_root_config_t rootCfg = {0};
|
||||
|
||||
/* Set DCDC to DCM mode to improve the efficiency for light loading in run mode and transient performance with a big loading step. */
|
||||
DCDC_BootIntoDCM(DCDC);
|
||||
|
||||
#if !defined(SKIP_DCDC_ADJUSTMENT) || (!SKIP_DCDC_ADJUSTMENT)
|
||||
if((OCOTP->FUSEN[16].FUSE == 0x57AC5969U) && ((OCOTP->FUSEN[17].FUSE & 0xFFU) == 0x0BU))
|
||||
{
|
||||
DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set 1.125V for production samples to align with data sheet requirement */
|
||||
DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P125V);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(SKIP_FBB_ENABLE) || (!SKIP_FBB_ENABLE)
|
||||
/* Check if FBB need to be enabled in OverDrive(OD) mode */
|
||||
if(((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1)
|
||||
{
|
||||
PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true);
|
||||
}
|
||||
else
|
||||
{
|
||||
PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(BYPASS_LDO_LPSR) && BYPASS_LDO_LPSR
|
||||
PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true);
|
||||
PMU_StaticEnableLpsrDigLdoBypassMode(ANADIG_LDO_SNVS, true);
|
||||
#endif
|
||||
|
||||
#if !defined(SKIP_LDO_ADJUSTMENT) || (!SKIP_LDO_ADJUSTMENT)
|
||||
pmu_static_lpsr_ana_ldo_config_t lpsrAnaConfig;
|
||||
pmu_static_lpsr_dig_config_t lpsrDigConfig;
|
||||
|
||||
if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_ANA & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK) == 0UL)
|
||||
{
|
||||
PMU_StaticGetLpsrAnaLdoDefaultConfig(&lpsrAnaConfig);
|
||||
PMU_StaticLpsrAnaLdoInit(ANADIG_LDO_SNVS, &lpsrAnaConfig);
|
||||
}
|
||||
|
||||
if((ANADIG_LDO_SNVS->PMU_LDO_LPSR_DIG & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK) == 0UL)
|
||||
{
|
||||
PMU_StaticGetLpsrDigLdoDefaultConfig(&lpsrDigConfig);
|
||||
lpsrDigConfig.targetVoltage = kPMU_LpsrDigTargetStableVoltage1P117V;
|
||||
PMU_StaticLpsrDigLdoInit(ANADIG_LDO_SNVS, &lpsrDigConfig);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Config CLK_1M */
|
||||
CLOCK_OSC_Set1MHzOutputBehavior(kCLOCK_1MHzOutEnableFreeRunning1Mhz);
|
||||
|
||||
/* Init OSC RC 16M */
|
||||
ANADIG_OSC->OSC_16M_CTRL |= ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK;
|
||||
|
||||
/* Init OSC RC 400M */
|
||||
CLOCK_OSC_EnableOscRc400M();
|
||||
CLOCK_OSC_GateOscRc400M(true);
|
||||
|
||||
/* Init OSC RC 48M */
|
||||
CLOCK_OSC_EnableOsc48M(true);
|
||||
CLOCK_OSC_EnableOsc48MDiv2(true);
|
||||
|
||||
/* Config OSC 24M */
|
||||
ANADIG_OSC->OSC_24M_CTRL |= ANADIG_OSC_OSC_24M_CTRL_OSC_EN(1) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(0) | ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(0) | ANADIG_OSC_OSC_24M_CTRL_LP_EN(1) | ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(0);
|
||||
/* Wait for 24M OSC to be stable. */
|
||||
while (ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK !=
|
||||
(ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK))
|
||||
{
|
||||
}
|
||||
|
||||
/* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */
|
||||
#if __CORTEX_M == 7
|
||||
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
|
||||
|
||||
rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
|
||||
#endif
|
||||
|
||||
#if __CORTEX_M == 4
|
||||
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
|
||||
|
||||
rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* if DCD is used, please make sure the clock source of SEMC is not changed in the following PLL/PFD configuration code.
|
||||
*/
|
||||
/* Init Arm Pll. */
|
||||
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
|
||||
|
||||
/* Bypass Sys Pll1. */
|
||||
CLOCK_SetPllBypass(kCLOCK_PllSys1, true);
|
||||
|
||||
/* DeInit Sys Pll1. */
|
||||
CLOCK_DeinitSysPll1();
|
||||
|
||||
/* Init Sys Pll2. */
|
||||
CLOCK_InitSysPll2(&sysPll2Config_BOARD_BootClockRUN);
|
||||
|
||||
/* Init System Pll2 pfd0. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd0, 27);
|
||||
|
||||
/* Init System Pll2 pfd1. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd1, 16);
|
||||
|
||||
/* Init System Pll2 pfd2. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd2, 24);
|
||||
|
||||
/* Init System Pll2 pfd3. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys2, kCLOCK_Pfd3, 32);
|
||||
|
||||
/* Init Sys Pll3. */
|
||||
CLOCK_InitSysPll3();
|
||||
|
||||
/* Init System Pll3 pfd0. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd0, 13);
|
||||
|
||||
/* Init System Pll3 pfd1. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd1, 17);
|
||||
|
||||
/* Init System Pll3 pfd2. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd2, 32);
|
||||
|
||||
/* Init System Pll3 pfd3. */
|
||||
CLOCK_InitPfd(kCLOCK_PllSys3, kCLOCK_Pfd3, 22);
|
||||
|
||||
/* Bypass Audio Pll. */
|
||||
CLOCK_SetPllBypass(kCLOCK_PllAudio, true);
|
||||
|
||||
/* DeInit Audio Pll. */
|
||||
CLOCK_DeinitAudioPll();
|
||||
|
||||
/* Init Video Pll. */
|
||||
CLOCK_InitVideoPll(&videoPllConfig_BOARD_BootClockRUN);
|
||||
|
||||
/* Module clock root configurations. */
|
||||
/* Configure M7 using ARM_PLL_CLK */
|
||||
#if __CORTEX_M == 7
|
||||
rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg);
|
||||
#endif
|
||||
|
||||
/* Configure M4 using SYS_PLL3_PFD3_CLK */
|
||||
#if __CORTEX_M == 4
|
||||
rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg);
|
||||
#endif
|
||||
|
||||
/* Configure BUS using SYS_PLL3_CLK */
|
||||
rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out;
|
||||
rootCfg.div = 2;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg);
|
||||
|
||||
/* Configure BUS_LPSR using SYS_PLL3_CLK */
|
||||
rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out;
|
||||
rootCfg.div = 3;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg);
|
||||
|
||||
/* Configure SEMC using SYS_PLL2_PFD1_CLK */
|
||||
#ifndef SKIP_SEMC_INIT
|
||||
rootCfg.mux = kCLOCK_SEMC_ClockRoot_MuxSysPll2Pfd1;
|
||||
rootCfg.div = 3;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Semc, &rootCfg);
|
||||
#endif
|
||||
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
|
||||
UpdateSemcClock();
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Configure CSSYS using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_CSSYS_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Cssys, &rootCfg);
|
||||
|
||||
/* Configure CSTRACE using SYS_PLL2_CLK */
|
||||
rootCfg.mux = kCLOCK_CSTRACE_ClockRoot_MuxSysPll2Out;
|
||||
rootCfg.div = 4;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg);
|
||||
|
||||
/* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */
|
||||
#if __CORTEX_M == 4
|
||||
rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg);
|
||||
#endif
|
||||
|
||||
/* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */
|
||||
#if __CORTEX_M == 7
|
||||
rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 240;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
|
||||
#endif
|
||||
|
||||
/* Configure ADC1 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_ADC1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Adc1, &rootCfg);
|
||||
|
||||
/* Configure ADC2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_ADC2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Adc2, &rootCfg);
|
||||
|
||||
/* Configure ACMP using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
|
||||
|
||||
/* Configure FLEXIO1 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_FLEXIO1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Flexio1, &rootCfg);
|
||||
|
||||
/* Configure FLEXIO2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_FLEXIO2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Flexio2, &rootCfg);
|
||||
|
||||
/* Configure GPT1 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_GPT1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Gpt1, &rootCfg);
|
||||
|
||||
/* Configure GPT2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_GPT2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Gpt2, &rootCfg);
|
||||
|
||||
/* Configure GPT3 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_GPT3_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Gpt3, &rootCfg);
|
||||
|
||||
/* Configure GPT4 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_GPT4_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Gpt4, &rootCfg);
|
||||
|
||||
/* Configure GPT5 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_GPT5_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Gpt5, &rootCfg);
|
||||
|
||||
/* Configure GPT6 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_GPT6_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Gpt6, &rootCfg);
|
||||
|
||||
/* Configure FLEXSPI1 using OSC_RC_48M_DIV2 */
|
||||
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) || defined(FLEXSPI_IN_USE))
|
||||
rootCfg.mux = kCLOCK_FLEXSPI1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
|
||||
#endif
|
||||
|
||||
/* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
|
||||
|
||||
/* Configure CAN1 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_CAN1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Can1, &rootCfg);
|
||||
|
||||
/* Configure CAN2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_CAN2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Can2, &rootCfg);
|
||||
|
||||
/* Configure CAN3 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_CAN3_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Can3, &rootCfg);
|
||||
|
||||
/* Configure LPUART1 using SYS_PLL2_CLK */
|
||||
rootCfg.mux = kCLOCK_LPUART1_ClockRoot_MuxSysPll2Out;
|
||||
rootCfg.div = 22;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart1, &rootCfg);
|
||||
|
||||
/* Configure LPUART2 using SYS_PLL2_CLK */
|
||||
rootCfg.mux = kCLOCK_LPUART2_ClockRoot_MuxSysPll2Out;
|
||||
rootCfg.div = 22;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart2, &rootCfg);
|
||||
|
||||
/* Configure LPUART3 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPUART3_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart3, &rootCfg);
|
||||
|
||||
/* Configure LPUART4 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPUART4_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart4, &rootCfg);
|
||||
|
||||
/* Configure LPUART5 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPUART5_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart5, &rootCfg);
|
||||
|
||||
/* Configure LPUART6 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPUART6_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart6, &rootCfg);
|
||||
|
||||
/* Configure LPUART7 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPUART7_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart7, &rootCfg);
|
||||
|
||||
/* Configure LPUART8 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPUART8_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart8, &rootCfg);
|
||||
|
||||
/* Configure LPUART9 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPUART9_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart9, &rootCfg);
|
||||
|
||||
/* Configure LPUART10 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPUART10_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart10, &rootCfg);
|
||||
|
||||
/* Configure LPUART11 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPUART11_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart11, &rootCfg);
|
||||
|
||||
/* Configure LPUART12 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPUART12_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpuart12, &rootCfg);
|
||||
|
||||
/* Configure LPI2C1 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPI2C1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c1, &rootCfg);
|
||||
|
||||
/* Configure LPI2C2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPI2C2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c2, &rootCfg);
|
||||
|
||||
/* Configure LPI2C3 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPI2C3_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c3, &rootCfg);
|
||||
|
||||
/* Configure LPI2C4 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPI2C4_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c4, &rootCfg);
|
||||
|
||||
/* Configure LPI2C5 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPI2C5_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c5, &rootCfg);
|
||||
|
||||
/* Configure LPI2C6 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPI2C6_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
|
||||
|
||||
/* Configure LPSPI1 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
|
||||
|
||||
/* Configure LPSPI2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPSPI2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpspi2, &rootCfg);
|
||||
|
||||
/* Configure LPSPI3 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPSPI3_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpspi3, &rootCfg);
|
||||
|
||||
/* Configure LPSPI4 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPSPI4_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpspi4, &rootCfg);
|
||||
|
||||
/* Configure LPSPI5 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPSPI5_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpspi5, &rootCfg);
|
||||
|
||||
/* Configure LPSPI6 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LPSPI6_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lpspi6, &rootCfg);
|
||||
|
||||
/* Configure EMV1 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_EMV1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Emv1, &rootCfg);
|
||||
|
||||
/* Configure EMV2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_EMV2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Emv2, &rootCfg);
|
||||
|
||||
/* Configure ENET1 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
|
||||
|
||||
/* Configure ENET2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_ENET2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
|
||||
|
||||
/* Configure ENET_QOS using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_ENET_QOS_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Enet_Qos, &rootCfg);
|
||||
|
||||
/* Configure ENET_25M using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_ENET_25M_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Enet_25m, &rootCfg);
|
||||
|
||||
/* Configure ENET_TIMER1 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer1, &rootCfg);
|
||||
|
||||
/* Configure ENET_TIMER2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_ENET_TIMER2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer2, &rootCfg);
|
||||
|
||||
/* Configure ENET_TIMER3 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_ENET_TIMER3_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Enet_Timer3, &rootCfg);
|
||||
|
||||
/* Configure USDHC1 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
|
||||
|
||||
/* Configure USDHC2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
|
||||
|
||||
/* Configure ASRC using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_ASRC_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Asrc, &rootCfg);
|
||||
|
||||
/* Configure MQS using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_MQS_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Mqs, &rootCfg);
|
||||
|
||||
/* Configure MIC using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_MIC_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Mic, &rootCfg);
|
||||
|
||||
/* Configure SPDIF using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_SPDIF_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Spdif, &rootCfg);
|
||||
|
||||
/* Configure SAI1 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_SAI1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Sai1, &rootCfg);
|
||||
|
||||
/* Configure SAI2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_SAI2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Sai2, &rootCfg);
|
||||
|
||||
/* Configure SAI3 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_SAI3_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Sai3, &rootCfg);
|
||||
|
||||
/* Configure SAI4 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_SAI4_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Sai4, &rootCfg);
|
||||
|
||||
/* Configure GC355 using PLL_VIDEO_CLK */
|
||||
rootCfg.mux = kCLOCK_GC355_ClockRoot_MuxVideoPllOut;
|
||||
rootCfg.div = 2;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Gc355, &rootCfg);
|
||||
|
||||
/* Configure LCDIF using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LCDIF_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lcdif, &rootCfg);
|
||||
|
||||
/* Configure LCDIFV2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_LCDIFV2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Lcdifv2, &rootCfg);
|
||||
|
||||
/* Configure MIPI_REF using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_MIPI_REF_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Mipi_Ref, &rootCfg);
|
||||
|
||||
/* Configure MIPI_ESC using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_MIPI_ESC_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Mipi_Esc, &rootCfg);
|
||||
|
||||
/* Configure CSI2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_CSI2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Csi2, &rootCfg);
|
||||
|
||||
/* Configure CSI2_ESC using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_CSI2_ESC_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Csi2_Esc, &rootCfg);
|
||||
|
||||
/* Configure CSI2_UI using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_CSI2_UI_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Csi2_Ui, &rootCfg);
|
||||
|
||||
/* Configure CSI using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_CSI_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Csi, &rootCfg);
|
||||
|
||||
/* Configure CKO1 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_CKO1_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Cko1, &rootCfg);
|
||||
|
||||
/* Configure CKO2 using OSC_RC_48M_DIV2 */
|
||||
rootCfg.mux = kCLOCK_CKO2_ClockRoot_MuxOscRc48MDiv2;
|
||||
rootCfg.div = 1;
|
||||
CLOCK_SetRootClock(kCLOCK_Root_Cko2, &rootCfg);
|
||||
|
||||
/* Set SAI1 MCLK1 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
|
||||
/* Set SAI1 MCLK2 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 3);
|
||||
/* Set SAI1 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
|
||||
/* Set SAI2 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
|
||||
/* Set SAI3 MCLK3 clock source. */
|
||||
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
|
||||
|
||||
/* Set MQS configuration. */
|
||||
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
|
||||
/* Set ENET Ref clock source. */
|
||||
IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK;
|
||||
/* Set ENET_1G Tx clock source. */
|
||||
IOMUXC_GPR->GPR5 = ((IOMUXC_GPR->GPR5 & ~IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK) | IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK);
|
||||
/* Set ENET_1G Ref clock source. */
|
||||
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK;
|
||||
/* Set ENET_QOS Tx clock source. */
|
||||
IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK;
|
||||
/* Set ENET_QOS Ref clock source. */
|
||||
IOMUXC_GPR->GPR6 &= ~IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK;
|
||||
/* Set GPT1 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR22 &= ~IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK;
|
||||
/* Set GPT2 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR23 &= ~IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK;
|
||||
/* Set GPT3 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR24 &= ~IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK;
|
||||
/* Set GPT4 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR25 &= ~IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK;
|
||||
/* Set GPT5 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR26 &= ~IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK;
|
||||
/* Set GPT6 High frequency reference clock source. */
|
||||
IOMUXC_GPR->GPR27 &= ~IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK;
|
||||
|
||||
#if __CORTEX_M == 7
|
||||
SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M7);
|
||||
#else
|
||||
SystemCoreClock = CLOCK_GetRootClockFreq(kCLOCK_Root_M4);
|
||||
#endif
|
||||
}
|
||||
202
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h
Normal file
202
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h
Normal file
@ -0,0 +1,202 @@
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
|
||||
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
********************** Configuration BOARD_BootClockRUN ***********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if __CORTEX_M == 7
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 996000000UL /*!< CM7 Core clock frequency: 996000000Hz */
|
||||
#else
|
||||
#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 392727272UL /*!< CM4 Core clock frequency: 392727272Hz */
|
||||
#endif
|
||||
|
||||
/* Clock outputs (values are in Hz): */
|
||||
#define BOARD_BOOTCLOCKRUN_ACMP_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ADC1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ADC2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CAN3_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CCM_CLKO1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CCM_CLKO2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CSI2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CSI2_ESC_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CSI2_UI_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CSSYS_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_CSTRACE_CLK_ROOT 132000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ELCDIF_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_EMV1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_EMV2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_1G_REF_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_1G_TX_CLK 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_25M_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_QOS_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_QOS_REF_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_QOS_TX_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_TIMER1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_TIMER2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_TIMER3_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GC355_CLK_ROOT 492000012UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT3_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT3_IPG_CLK_HIGHFREQ 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT4_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT4_IPG_CLK_HIGHFREQ 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT5_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT5_IPG_CLK_HIGHFREQ 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT6_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_GPT6_IPG_CLK_HIGHFREQ 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LCDIFV2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C3_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C4_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C5_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPI2C6_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI3_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI4_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI5_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPSPI6_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART10_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART11_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART12_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART3_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART4_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART5_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART6_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART7_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART8_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_LPUART9_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_M4_CLK_ROOT 392727272UL
|
||||
#define BOARD_BOOTCLOCKRUN_M4_SYSTICK_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_M7_CLK_ROOT 996000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_M7_SYSTICK_CLK_ROOT 100000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MIC_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MIPI_DSI_TX_CLK_ESC_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MIPI_ESC_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MIPI_REF_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MQS_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_MQS_MCLK 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_24M 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_32K 32768UL
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_RC_16M 16000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_RC_400M 400000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M 48000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_OSC_RC_48M_DIV2 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_MODULATION 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_AUDIO_SS_RANGE 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_CLK 984000025UL
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_MODULATION 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_PLL_VIDEO_SS_RANGE 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK1 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SAI4_MCLK2 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 198000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SPDIF_EXTCLK_OUT 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV2_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_DIV5_CLK 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_MODULATION 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL1_SS_RANGE 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_CLK 528000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD0_CLK 352000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD1_CLK 594000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD2_CLK 396000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_PFD3_CLK 297000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_MODULATION 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL2_SS_RANGE 0UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_CLK 480000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_DIV2_CLK 240000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD0_CLK 664615384UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD1_CLK 508235294UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD2_CLK 270000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_SYS_PLL3_PFD3_CLK 392727272UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 24000000UL
|
||||
#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 24000000UL
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockRUN configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockRUN(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
110
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c
Normal file
110
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c
Normal file
@ -0,0 +1,110 @@
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v13.1
|
||||
processor: MIMXRT1176xxxxx
|
||||
package_id: MIMXRT1176DVMAA
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 13.0.2
|
||||
board: MIMXRT1170-EVKB
|
||||
external_user_signals: {}
|
||||
pin_labels:
|
||||
- {pin_num: M13, pin_signal: GPIO_AD_04, label: 'SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7]', identifier: SIM1_PD;LED}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_iomuxc.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void) {
|
||||
BOARD_InitPins();
|
||||
}
|
||||
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
|
||||
open_drain: Disable, drive_strength: High, slew_rate: Slow}
|
||||
- {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper,
|
||||
open_drain: Disable, drive_strength: High, slew_rate: Slow}
|
||||
- {pin_num: M13, peripheral: GPIO9, signal: 'gpio_io, 03', pin_signal: GPIO_AD_04, identifier: LED, pull_up_down_config: Pull_Down}
|
||||
- {pin_num: T8, peripheral: GPIO13, signal: 'gpio_io, 00', pin_signal: WAKEUP, pull_up_down_config: Pull_Up}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins, assigned for the Cortex-M7F core.
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitPins(void) {
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */
|
||||
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 is configured as GPIO9_IO03 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinMux(
|
||||
IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG is configured as GPIO13_IO00 */
|
||||
0U); /* Software Input On Field: Input Path is determined by functionality */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 PAD functional properties : */
|
||||
0x06U); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: high drive strength
|
||||
Pull / Keep Select Field: Pull Enable
|
||||
Pull Up / Down Config. Field: Weak pull down
|
||||
Open Drain Field: Disabled
|
||||
Domain write protection: Both cores are allowed
|
||||
Domain write protection lock: Neither of DWP bits is locked */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */
|
||||
0x02U); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: high drive strength
|
||||
Pull / Keep Select Field: Pull Disable, Highz
|
||||
Pull Up / Down Config. Field: Weak pull down
|
||||
Open Drain Field: Disabled
|
||||
Domain write protection: Both cores are allowed
|
||||
Domain write protection lock: Neither of DWP bits is locked */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */
|
||||
0x02U); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: high drive strength
|
||||
Pull / Keep Select Field: Pull Disable, Highz
|
||||
Pull Up / Down Config. Field: Weak pull down
|
||||
Open Drain Field: Disabled
|
||||
Domain write protection: Both cores are allowed
|
||||
Domain write protection lock: Neither of DWP bits is locked */
|
||||
IOMUXC_SetPinConfig(
|
||||
IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG PAD functional properties : */
|
||||
0x0EU); /* Slew Rate Field: Slow Slew Rate
|
||||
Drive Strength Field: high driver
|
||||
Pull / Keep Select Field: Pull Enable
|
||||
Pull Up / Down Config. Field: Weak pull up
|
||||
Open Drain SNVS Field: Disabled
|
||||
Domain write protection: Both cores are allowed
|
||||
Domain write protection lock: Neither of DWP bits is locked */
|
||||
}
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
77
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h
Normal file
77
hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h
Normal file
@ -0,0 +1,77 @@
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/* GPIO_AD_25 (coord M15), LPUART1_RXD */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITPINS_LPUART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */
|
||||
#define BOARD_INITPINS_LPUART1_RXD_SIGNAL RXD /*!< Signal name */
|
||||
|
||||
/* GPIO_AD_24 (coord L13), LPUART1_TXD */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITPINS_LPUART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */
|
||||
#define BOARD_INITPINS_LPUART1_TXD_SIGNAL TXD /*!< Signal name */
|
||||
|
||||
/* GPIO_AD_04 (coord M13), SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7] */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITPINS_LED_PERIPHERAL GPIO9 /*!< Peripheral name */
|
||||
#define BOARD_INITPINS_LED_SIGNAL gpio_io /*!< Signal name */
|
||||
#define BOARD_INITPINS_LED_CHANNEL 3U /*!< Signal channel */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITPINS_LED_GPIO GPIO9 /*!< GPIO peripheral base pointer */
|
||||
#define BOARD_INITPINS_LED_GPIO_PIN 3U /*!< GPIO pin number */
|
||||
#define BOARD_INITPINS_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */
|
||||
|
||||
/* WAKEUP (coord T8), USER_BUTTON */
|
||||
/* Routed pin properties */
|
||||
#define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO13 /*!< Peripheral name */
|
||||
#define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */
|
||||
#define BOARD_INITPINS_USER_BUTTON_CHANNEL 0U /*!< Signal channel */
|
||||
|
||||
/* Symbols to be used with GPIO driver */
|
||||
#define BOARD_INITPINS_USER_BUTTON_GPIO GPIO13 /*!< GPIO peripheral base pointer */
|
||||
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN 0U /*!< GPIO pin number */
|
||||
#define BOARD_INITPINS_USER_BUTTON_GPIO_PIN_MASK (1U << 0U) /*!< GPIO pin mask */
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void); /* Function assigned for the Cortex-M7F */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
@ -0,0 +1,71 @@
|
||||
/*
|
||||
* Copyright 2018-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include "evkbmimxrt1170_flexspi_nor_config.h"
|
||||
|
||||
/* Component ID definition, used by tools. */
|
||||
#ifndef FSL_COMPONENT_ID
|
||||
#define FSL_COMPONENT_ID "platform.drivers.xip_board"
|
||||
#endif
|
||||
|
||||
/*******************************************************************************
|
||||
* Code
|
||||
******************************************************************************/
|
||||
#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
|
||||
#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
|
||||
__attribute__((section(".boot_hdr.conf"), used))
|
||||
#elif defined(__ICCARM__)
|
||||
#pragma location = ".boot_hdr.conf"
|
||||
#endif
|
||||
|
||||
const flexspi_nor_config_t qspiflash_config = {
|
||||
.memConfig =
|
||||
{
|
||||
.tag = FLEXSPI_CFG_BLK_TAG,
|
||||
.version = FLEXSPI_CFG_BLK_VERSION,
|
||||
.readSampleClkSrc = kFlexSPIReadSampleClk_LoopbackFromDqsPad,
|
||||
.csHoldTime = 3u,
|
||||
.csSetupTime = 3u,
|
||||
// Enable DDR mode, Wordaddassable, Safe configuration, Differential clock
|
||||
.controllerMiscOption = 0x10,
|
||||
.deviceType = kFlexSpiDeviceType_SerialNOR,
|
||||
.sflashPadType = kSerialFlash_4Pads,
|
||||
.serialClkFreq = kFlexSpiSerialClk_133MHz,
|
||||
.sflashA1Size = 64u * 1024u * 1024u,
|
||||
.lookupTable =
|
||||
{
|
||||
// Read LUTs
|
||||
[0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xEC, RADDR_SDR, FLEXSPI_4PAD, 0x20),
|
||||
[1] = FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06, READ_SDR, FLEXSPI_4PAD, 0x04),
|
||||
|
||||
// Read Status LUTs
|
||||
[4 * 1 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x04),
|
||||
|
||||
// Write Enable LUTs
|
||||
[4 * 3 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),
|
||||
|
||||
// Erase Sector LUTs
|
||||
[4 * 5 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x21, RADDR_SDR, FLEXSPI_1PAD, 0x20),
|
||||
|
||||
// Erase Block LUTs
|
||||
[4 * 8 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8, RADDR_SDR, FLEXSPI_1PAD, 0x18),
|
||||
|
||||
// Pape Program LUTs
|
||||
[4 * 9 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x12, RADDR_SDR, FLEXSPI_1PAD, 0x20),
|
||||
[4 * 9 + 1] = FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x04, STOP, FLEXSPI_1PAD, 0x0),
|
||||
|
||||
// Erase Chip LUTs
|
||||
[4 * 11 + 0] = FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x60, STOP, FLEXSPI_1PAD, 0x0),
|
||||
},
|
||||
},
|
||||
.pageSize = 256u,
|
||||
.sectorSize = 4u * 1024u,
|
||||
.ipcmdSerialClkFreq = 0x1,
|
||||
.blockSize = 64u * 1024u,
|
||||
.isUniformBlockSize = false,
|
||||
};
|
||||
#endif /* XIP_BOOT_HEADER_ENABLE */
|
||||
@ -0,0 +1,270 @@
|
||||
/*
|
||||
* Copyright 2018-2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__
|
||||
#define __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief XIP_BOARD driver version 2.0.1. */
|
||||
#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
|
||||
/*@}*/
|
||||
|
||||
/* FLEXSPI memory config block related definitions */
|
||||
#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) // ascii "FCFB" Big Endian
|
||||
#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) // V1.4.0
|
||||
#define FLEXSPI_CFG_BLK_SIZE (512)
|
||||
|
||||
/* FLEXSPI Feature related definitions */
|
||||
#define FLEXSPI_FEATURE_HAS_PARALLEL_MODE 1
|
||||
|
||||
/* Lookup table related definitions */
|
||||
#define CMD_INDEX_READ 0
|
||||
#define CMD_INDEX_READSTATUS 1
|
||||
#define CMD_INDEX_WRITEENABLE 2
|
||||
#define CMD_INDEX_WRITE 4
|
||||
|
||||
#define CMD_LUT_SEQ_IDX_READ 0
|
||||
#define CMD_LUT_SEQ_IDX_READSTATUS 1
|
||||
#define CMD_LUT_SEQ_IDX_WRITEENABLE 3
|
||||
#define CMD_LUT_SEQ_IDX_WRITE 9
|
||||
|
||||
#define CMD_SDR 0x01
|
||||
#define CMD_DDR 0x21
|
||||
#define RADDR_SDR 0x02
|
||||
#define RADDR_DDR 0x22
|
||||
#define CADDR_SDR 0x03
|
||||
#define CADDR_DDR 0x23
|
||||
#define MODE1_SDR 0x04
|
||||
#define MODE1_DDR 0x24
|
||||
#define MODE2_SDR 0x05
|
||||
#define MODE2_DDR 0x25
|
||||
#define MODE4_SDR 0x06
|
||||
#define MODE4_DDR 0x26
|
||||
#define MODE8_SDR 0x07
|
||||
#define MODE8_DDR 0x27
|
||||
#define WRITE_SDR 0x08
|
||||
#define WRITE_DDR 0x28
|
||||
#define READ_SDR 0x09
|
||||
#define READ_DDR 0x29
|
||||
#define LEARN_SDR 0x0A
|
||||
#define LEARN_DDR 0x2A
|
||||
#define DATSZ_SDR 0x0B
|
||||
#define DATSZ_DDR 0x2B
|
||||
#define DUMMY_SDR 0x0C
|
||||
#define DUMMY_DDR 0x2C
|
||||
#define DUMMY_RWDS_SDR 0x0D
|
||||
#define DUMMY_RWDS_DDR 0x2D
|
||||
#define JMP_ON_CS 0x1F
|
||||
#define STOP 0
|
||||
|
||||
#define FLEXSPI_1PAD 0
|
||||
#define FLEXSPI_2PAD 1
|
||||
#define FLEXSPI_4PAD 2
|
||||
#define FLEXSPI_8PAD 3
|
||||
|
||||
#define FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
|
||||
(FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
|
||||
FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
|
||||
|
||||
//!@brief Definitions for FlexSPI Serial Clock Frequency
|
||||
typedef enum _FlexSpiSerialClockFreq
|
||||
{
|
||||
kFlexSpiSerialClk_30MHz = 1,
|
||||
kFlexSpiSerialClk_50MHz = 2,
|
||||
kFlexSpiSerialClk_60MHz = 3,
|
||||
kFlexSpiSerialClk_80MHz = 4,
|
||||
kFlexSpiSerialClk_100MHz = 5,
|
||||
kFlexSpiSerialClk_120MHz = 6,
|
||||
kFlexSpiSerialClk_133MHz = 7,
|
||||
kFlexSpiSerialClk_166MHz = 8,
|
||||
kFlexSpiSerialClk_200MHz = 9,
|
||||
} flexspi_serial_clk_freq_t;
|
||||
|
||||
//!@brief FlexSPI clock configuration type
|
||||
enum
|
||||
{
|
||||
kFlexSpiClk_SDR, //!< Clock configure for SDR mode
|
||||
kFlexSpiClk_DDR, //!< Clock configurat for DDR mode
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Read Sample Clock Source definition
|
||||
typedef enum _FlashReadSampleClkSource
|
||||
{
|
||||
kFlexSPIReadSampleClk_LoopbackInternally = 0,
|
||||
kFlexSPIReadSampleClk_LoopbackFromDqsPad = 1,
|
||||
kFlexSPIReadSampleClk_LoopbackFromSckPad = 2,
|
||||
kFlexSPIReadSampleClk_ExternalInputFromDqsPad = 3,
|
||||
} flexspi_read_sample_clk_t;
|
||||
|
||||
//!@brief Misc feature bit definitions
|
||||
enum
|
||||
{
|
||||
kFlexSpiMiscOffset_DiffClkEnable = 0, //!< Bit for Differential clock enable
|
||||
kFlexSpiMiscOffset_Ck2Enable = 1, //!< Bit for CK2 enable
|
||||
kFlexSpiMiscOffset_ParallelEnable = 2, //!< Bit for Parallel mode enable
|
||||
kFlexSpiMiscOffset_WordAddressableEnable = 3, //!< Bit for Word Addressable enable
|
||||
kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, //!< Bit for Safe Configuration Frequency enable
|
||||
kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, //!< Bit for Pad setting override enable
|
||||
kFlexSpiMiscOffset_DdrModeEnable = 6, //!< Bit for DDR clock confiuration indication.
|
||||
};
|
||||
|
||||
//!@brief Flash Type Definition
|
||||
enum
|
||||
{
|
||||
kFlexSpiDeviceType_SerialNOR = 1, //!< Flash devices are Serial NOR
|
||||
kFlexSpiDeviceType_SerialNAND = 2, //!< Flash devices are Serial NAND
|
||||
kFlexSpiDeviceType_SerialRAM = 3, //!< Flash devices are Serial RAM/HyperFLASH
|
||||
kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND
|
||||
kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, //!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs
|
||||
};
|
||||
|
||||
//!@brief Flash Pad Definitions
|
||||
enum
|
||||
{
|
||||
kSerialFlash_1Pad = 1,
|
||||
kSerialFlash_2Pads = 2,
|
||||
kSerialFlash_4Pads = 4,
|
||||
kSerialFlash_8Pads = 8,
|
||||
};
|
||||
|
||||
//!@brief FlexSPI LUT Sequence structure
|
||||
typedef struct _lut_sequence
|
||||
{
|
||||
uint8_t seqNum; //!< Sequence Number, valid number: 1-16
|
||||
uint8_t seqId; //!< Sequence Index, valid number: 0-15
|
||||
uint16_t reserved;
|
||||
} flexspi_lut_seq_t;
|
||||
|
||||
//!@brief Flash Configuration Command Type
|
||||
enum
|
||||
{
|
||||
kDeviceConfigCmdType_Generic, //!< Generic command, for example: configure dummy cycles, drive strength, etc
|
||||
kDeviceConfigCmdType_QuadEnable, //!< Quad Enable command
|
||||
kDeviceConfigCmdType_Spi2Xpi, //!< Switch from SPI to DPI/QPI/OPI mode
|
||||
kDeviceConfigCmdType_Xpi2Spi, //!< Switch from DPI/QPI/OPI to SPI mode
|
||||
kDeviceConfigCmdType_Spi2NoCmd, //!< Switch to 0-4-4/0-8-8 mode
|
||||
kDeviceConfigCmdType_Reset, //!< Reset device command
|
||||
};
|
||||
|
||||
//!@brief FlexSPI Memory Configuration Block
|
||||
typedef struct _FlexSPIConfig
|
||||
{
|
||||
uint32_t tag; //!< [0x000-0x003] Tag, fixed value 0x42464346UL
|
||||
uint32_t version; //!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix
|
||||
uint32_t reserved0; //!< [0x008-0x00b] Reserved for future use
|
||||
uint8_t readSampleClkSrc; //!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3
|
||||
uint8_t csHoldTime; //!< [0x00d-0x00d] CS hold time, default value: 3
|
||||
uint8_t csSetupTime; //!< [0x00e-0x00e] CS setup time, default value: 3
|
||||
uint8_t columnAddressWidth; //!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
|
||||
//! Serial NAND, need to refer to datasheet
|
||||
uint8_t deviceModeCfgEnable; //!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable
|
||||
uint8_t deviceModeType; //!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
|
||||
//! Generic configuration, etc.
|
||||
uint16_t waitTimeCfgCommands; //!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
|
||||
//! DPI/QPI/OPI switch or reset command
|
||||
flexspi_lut_seq_t deviceModeSeq; //!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
|
||||
//! sequence number, [31:16] Reserved
|
||||
uint32_t deviceModeArg; //!< [0x018-0x01b] Argument/Parameter for device configuration
|
||||
uint8_t configCmdEnable; //!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable
|
||||
uint8_t configModeType[3]; //!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe
|
||||
flexspi_lut_seq_t
|
||||
configCmdSeqs[3]; //!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq
|
||||
uint32_t reserved1; //!< [0x02c-0x02f] Reserved for future use
|
||||
uint32_t configCmdArgs[3]; //!< [0x030-0x03b] Arguments/Parameters for device Configuration commands
|
||||
uint32_t reserved2; //!< [0x03c-0x03f] Reserved for future use
|
||||
uint32_t controllerMiscOption; //!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
|
||||
//! details
|
||||
uint8_t deviceType; //!< [0x044-0x044] Device Type: See Flash Type Definition for more details
|
||||
uint8_t sflashPadType; //!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal
|
||||
uint8_t serialClkFreq; //!< [0x046-0x046] Serial Flash Frequency, device specific definitions, See System Boot
|
||||
//! Chapter for more details
|
||||
uint8_t lutCustomSeqEnable; //!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
|
||||
//! be done using 1 LUT sequence, currently, only applicable to HyperFLASH
|
||||
uint32_t reserved3[2]; //!< [0x048-0x04f] Reserved for future use
|
||||
uint32_t sflashA1Size; //!< [0x050-0x053] Size of Flash connected to A1
|
||||
uint32_t sflashA2Size; //!< [0x054-0x057] Size of Flash connected to A2
|
||||
uint32_t sflashB1Size; //!< [0x058-0x05b] Size of Flash connected to B1
|
||||
uint32_t sflashB2Size; //!< [0x05c-0x05f] Size of Flash connected to B2
|
||||
uint32_t csPadSettingOverride; //!< [0x060-0x063] CS pad setting override value
|
||||
uint32_t sclkPadSettingOverride; //!< [0x064-0x067] SCK pad setting override value
|
||||
uint32_t dataPadSettingOverride; //!< [0x068-0x06b] data pad setting override value
|
||||
uint32_t dqsPadSettingOverride; //!< [0x06c-0x06f] DQS pad setting override value
|
||||
uint32_t timeoutInMs; //!< [0x070-0x073] Timeout threshold for read status command
|
||||
uint32_t commandInterval; //!< [0x074-0x077] CS deselect interval between two commands
|
||||
uint16_t dataValidTime[2]; //!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns
|
||||
uint16_t busyOffset; //!< [0x07c-0x07d] Busy offset, valid value: 0-31
|
||||
uint16_t busyBitPolarity; //!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
|
||||
//! busy flag is 0 when flash device is busy
|
||||
uint32_t lookupTable[64]; //!< [0x080-0x17f] Lookup table holds Flash command sequences
|
||||
flexspi_lut_seq_t lutCustomSeq[12]; //!< [0x180-0x1af] Customizable LUT Sequences
|
||||
uint32_t reserved4[4]; //!< [0x1b0-0x1bf] Reserved for future use
|
||||
} flexspi_mem_config_t;
|
||||
|
||||
/* */
|
||||
#define NOR_CMD_INDEX_READ CMD_INDEX_READ //!< 0
|
||||
#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS //!< 1
|
||||
#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE //!< 2
|
||||
#define NOR_CMD_INDEX_ERASESECTOR 3 //!< 3
|
||||
#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE //!< 4
|
||||
#define NOR_CMD_INDEX_CHIPERASE 5 //!< 5
|
||||
#define NOR_CMD_INDEX_DUMMY 6 //!< 6
|
||||
#define NOR_CMD_INDEX_ERASEBLOCK 7 //!< 7
|
||||
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ CMD_LUT_SEQ_IDX_READ //!< 0 READ LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
|
||||
CMD_LUT_SEQ_IDX_READSTATUS //!< 1 Read Status LUT sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
|
||||
2 //!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
|
||||
CMD_LUT_SEQ_IDX_WRITEENABLE //!< 3 Write Enable sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
|
||||
4 //!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 //!< 5 Erase Sector sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 //!< 8 Erase Block sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
|
||||
CMD_LUT_SEQ_IDX_WRITE //!< 9 Program sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 //!< 11 Chip Erase sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 //!< 13 Read SFDP sequence in lookupTable id stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
|
||||
14 //!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block
|
||||
#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
|
||||
15 //!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk
|
||||
|
||||
/*
|
||||
* Serial NOR configuration block
|
||||
*/
|
||||
typedef struct _flexspi_nor_config
|
||||
{
|
||||
flexspi_mem_config_t memConfig; //!< Common memory configuration info via FlexSPI
|
||||
uint32_t pageSize; //!< Page size of Serial NOR
|
||||
uint32_t sectorSize; //!< Sector size of Serial NOR
|
||||
uint8_t ipcmdSerialClkFreq; //!< Clock frequency for IP command
|
||||
uint8_t isUniformBlockSize; //!< Sector/Block size is the same
|
||||
uint8_t isDataOrderSwapped; //!< The data order is swapped in OPI DDR mode
|
||||
uint8_t reserved0; //!< Reserved for future use
|
||||
uint8_t serialNorType; //!< Serial NOR Flash type: 0/1/2/3
|
||||
uint8_t needExitNoCmdMode; //!< Need to exit NoCmd mode before other IP command
|
||||
uint8_t halfClkForNonReadCmd; //!< Half the Serial Clock for non-read command: true/false
|
||||
uint8_t needRestoreNoCmdMode; //!< Need to Restore NoCmd mode after IP command execution
|
||||
uint32_t blockSize; //!< Block size
|
||||
uint32_t FlashStateCtx; //!< Flash State Context after being configured
|
||||
uint32_t reserve2[10]; //!< Reserved for future use
|
||||
} flexspi_nor_config_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __EVKMIMXRT1170_FLEXSPI_NOR_CONFIG__ */
|
||||
656
hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex
Normal file
656
hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex
Normal file
@ -0,0 +1,656 @@
|
||||
<?xml version="1.0" encoding= "UTF-8" ?>
|
||||
<configuration name="MIMXRT1176xxxxx" xsi:schemaLocation="http://mcuxpresso.nxp.com/XSD/mex_configuration_13 http://mcuxpresso.nxp.com/XSD/mex_configuration_13.xsd" uuid="060646c1-2247-47a8-b52d-03c1968b4426" version="13" xmlns="http://mcuxpresso.nxp.com/XSD/mex_configuration_13" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<common>
|
||||
<processor>MIMXRT1176xxxxx</processor>
|
||||
<package>MIMXRT1176DVMAA</package>
|
||||
<board>MIMXRT1170-EVKB</board>
|
||||
<mcu_data>ksdk2_0</mcu_data>
|
||||
<cores selected="cm7">
|
||||
<core name="Cortex-M4F" id="cm4" description=""/>
|
||||
<core name="Cortex-M7F" id="cm7" description=""/>
|
||||
</cores>
|
||||
<description>Configuration imported from evkbmimxrt1170_dev_cdc_vcom_lite_bm_cm7</description>
|
||||
</common>
|
||||
<preferences>
|
||||
<validate_boot_init_only>true</validate_boot_init_only>
|
||||
<generate_extended_information>false</generate_extended_information>
|
||||
<generate_code_modified_registers_only>false</generate_code_modified_registers_only>
|
||||
<update_include_paths>true</update_include_paths>
|
||||
<generate_registers_defines>false</generate_registers_defines>
|
||||
</preferences>
|
||||
<tools>
|
||||
<pins name="Pins" version="13.1" enabled="true" update_project_code="true">
|
||||
<generated_project_files>
|
||||
<file path="board/pin_mux.c" update_enabled="true"/>
|
||||
<file path="board/pin_mux.h" update_enabled="true"/>
|
||||
</generated_project_files>
|
||||
<pins_profile>
|
||||
<processor_version>13.0.2</processor_version>
|
||||
<pin_labels>
|
||||
<pin_label pin_num="M13" pin_signal="GPIO_AD_04" label="SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7]" identifier="SIM1_PD;LED"/>
|
||||
</pin_labels>
|
||||
<external_user_signals>
|
||||
<properties/>
|
||||
</external_user_signals>
|
||||
<power_domains/>
|
||||
</pins_profile>
|
||||
<functions_list>
|
||||
<function name="BOARD_InitPins">
|
||||
<description>Configures pin routing and optionally pin electrical features.</description>
|
||||
<options>
|
||||
<callFromInitBoot>true</callFromInitBoot>
|
||||
<coreID>cm7</coreID>
|
||||
<enableClock>true</enableClock>
|
||||
</options>
|
||||
<dependencies>
|
||||
<dependency resourceType="Peripheral" resourceId="LPUART1" description="Peripheral LPUART1 is not initialized" problem_level="1" source="Pins:BOARD_InitPins">
|
||||
<feature name="initialized" evaluation="equal">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Pins initialization requires the COMMON Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm7">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Pins initialization requires the IOMUXC Driver in the project." problem_level="2" source="Pins:BOARD_InitPins">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm7">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<pins>
|
||||
<pin peripheral="LPUART1" signal="RXD" pin_num="M15" pin_signal="GPIO_AD_25">
|
||||
<pin_features>
|
||||
<pin_feature name="software_input_on" value="Disable"/>
|
||||
<pin_feature name="pull_up_down_config" value="Pull_Down"/>
|
||||
<pin_feature name="pull_keeper_select" value="Keeper"/>
|
||||
<pin_feature name="open_drain" value="Disable"/>
|
||||
<pin_feature name="drive_strength" value="High"/>
|
||||
<pin_feature name="slew_rate" value="Slow"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="LPUART1" signal="TXD" pin_num="L13" pin_signal="GPIO_AD_24">
|
||||
<pin_features>
|
||||
<pin_feature name="software_input_on" value="Disable"/>
|
||||
<pin_feature name="pull_up_down_config" value="Pull_Down"/>
|
||||
<pin_feature name="pull_keeper_select" value="Keeper"/>
|
||||
<pin_feature name="open_drain" value="Disable"/>
|
||||
<pin_feature name="drive_strength" value="High"/>
|
||||
<pin_feature name="slew_rate" value="Slow"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="GPIO9" signal="gpio_io, 03" pin_num="M13" pin_signal="GPIO_AD_04">
|
||||
<pin_features>
|
||||
<pin_feature name="identifier" value="LED"/>
|
||||
<pin_feature name="pull_up_down_config" value="Pull_Down"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
<pin peripheral="GPIO13" signal="gpio_io, 00" pin_num="T8" pin_signal="WAKEUP">
|
||||
<pin_features>
|
||||
<pin_feature name="pull_up_down_config" value="Pull_Up"/>
|
||||
</pin_features>
|
||||
</pin>
|
||||
</pins>
|
||||
</function>
|
||||
</functions_list>
|
||||
</pins>
|
||||
<clocks name="Clocks" version="11.0" enabled="true" update_project_code="true">
|
||||
<generated_project_files>
|
||||
<file path="board/clock_config.c" update_enabled="true"/>
|
||||
<file path="board/clock_config.h" update_enabled="true"/>
|
||||
</generated_project_files>
|
||||
<clocks_profile>
|
||||
<processor_version>13.0.2</processor_version>
|
||||
</clocks_profile>
|
||||
<clock_configurations>
|
||||
<clock_configuration name="BOARD_BootClockRUN" id_prefix="" prefix_user_defined="false">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtali" description="'XTALI' (Pins tool id: ANADIG.xtali, Clocks tool id: ANADIG_OSC.XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtali" description="'XTALI' (Pins tool id: ANADIG.xtali, Clocks tool id: ANADIG_OSC.XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>INPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtalo" description="'XTALO' (Pins tool id: ANADIG.xtalo, Clocks tool id: ANADIG_OSC.XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.xtalo" description="'XTALO' (Pins tool id: ANADIG.xtalo, Clocks tool id: ANADIG_OSC.XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>OUTPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtali" description="'RTC_XTALI' (Pins tool id: ANADIG.rtc_xtali, Clocks tool id: ANADIG_OSC.RTC_XTALI) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtali" description="'RTC_XTALI' (Pins tool id: ANADIG.rtc_xtali, Clocks tool id: ANADIG_OSC.RTC_XTALI) needs to have 'INPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>INPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: ANADIG.rtc_xtalo, Clocks tool id: ANADIG_OSC.RTC_XTALO) needs to be routed" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="routed" evaluation="">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="ANADIG.rtc_xtalo" description="'RTC_XTALO' (Pins tool id: ANADIG.rtc_xtalo, Clocks tool id: ANADIG_OSC.RTC_XTALO) needs to have 'OUTPUT' direction" problem_level="1" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="direction" evaluation="">
|
||||
<data>OUTPUT</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm4">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.common" description="Clocks initialization requires the COMMON Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm7">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm4">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.iomuxc" description="Clocks initialization requires the IOMUXC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm7">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.dcdc_soc" description="Clocks initialization requires the DCDC_SOC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm4">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.dcdc_soc" description="Clocks initialization requires the DCDC_SOC Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm7">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.pmu_1" description="Clocks initialization requires the PMU_1 Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm4">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.pmu_1" description="Clocks initialization requires the PMU_1 Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm7">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm4">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.clock" description="Clocks initialization requires the CLOCK Driver in the project." problem_level="2" source="Clocks:BOARD_BootClockRUN">
|
||||
<feature name="enabled" evaluation="equal" configuration="cm7">
|
||||
<data>true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<clock_sources/>
|
||||
<clock_outputs>
|
||||
<clock_output id="ACMP_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ADC1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ADC2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ARM_PLL_CLK.outFreq" value="996 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ASRC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="AXI_CLK_ROOT.outFreq" value="996 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="BUS_CLK_ROOT.outFreq" value="240 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="BUS_LPSR_CLK_ROOT.outFreq" value="160 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CAN1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CAN2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CAN3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CCM_CLKO1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CCM_CLKO2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CLK_1M.outFreq" value="1 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CSI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CSI2_ESC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CSI2_UI_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CSI_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CSSYS_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="CSTRACE_CLK_ROOT.outFreq" value="132 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ELCDIF_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="EMV1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="EMV2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET_1G_TX_CLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET_25M_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET_QOS_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET_TIMER1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET_TIMER2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="ENET_TIMER3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXIO1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXIO2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXSPI1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="FLEXSPI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GC355_CLK_ROOT.outFreq" value="492.0000125 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT1_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT2_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT3_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT4_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT5_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT5_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT6_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="GPT6_ipg_clk_highfreq.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LCDIFV2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPI2C1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPI2C2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPI2C3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPI2C4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPI2C5_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPI2C6_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPSPI1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPSPI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPSPI3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPSPI4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPSPI5_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPSPI6_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPUART10_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPUART11_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPUART12_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPUART1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPUART2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPUART3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPUART4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPUART5_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPUART6_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPUART7_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPUART8_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="LPUART9_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="M4_CLK_ROOT.outFreq" value="4320/11 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="M4_SYSTICK_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="M7_CLK_ROOT.outFreq" value="996 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="M7_SYSTICK_CLK_ROOT.outFreq" value="100 kHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MIC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MIPI_DSI_TX_CLK_ESC_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MIPI_ESC_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MIPI_REF_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MQS_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="MQS_MCLK.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="OSC_24M.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="OSC_32K.outFreq" value="32.768 kHz" locked="false" accuracy=""/>
|
||||
<clock_output id="OSC_RC_16M.outFreq" value="16 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="OSC_RC_400M.outFreq" value="400 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="OSC_RC_48M.outFreq" value="48 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="OSC_RC_48M_DIV2.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="PLL_VIDEO_CLK.outFreq" value="984.000025 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI1_MCLK3.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI2_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI2_MCLK3.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI3_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI3_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI3_MCLK3.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI4_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SAI4_MCLK1.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SEMC_CLK_ROOT.outFreq" value="198 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SPDIF_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SYS_PLL2_CLK.outFreq" value="528 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SYS_PLL2_PFD0_CLK.outFreq" value="352 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SYS_PLL2_PFD1_CLK.outFreq" value="594 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SYS_PLL2_PFD2_CLK.outFreq" value="396 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SYS_PLL2_PFD3_CLK.outFreq" value="297 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SYS_PLL3_CLK.outFreq" value="480 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SYS_PLL3_DIV2_CLK.outFreq" value="240 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SYS_PLL3_PFD0_CLK.outFreq" value="8640/13 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SYS_PLL3_PFD1_CLK.outFreq" value="8640/17 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SYS_PLL3_PFD2_CLK.outFreq" value="270 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="SYS_PLL3_PFD3_CLK.outFreq" value="4320/11 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="USDHC1_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
<clock_output id="USDHC2_CLK_ROOT.outFreq" value="24 MHz" locked="false" accuracy=""/>
|
||||
</clock_outputs>
|
||||
<clock_settings>
|
||||
<setting id="CoreBusClockRootsInitializationConfig" value="selectedCore" locked="false"/>
|
||||
<setting id="SOCDomainVoltage" value="OD" locked="false"/>
|
||||
<setting id="ANADIG_OSC_OSC_24M_CTRL_LP_EN_CFG" value="Low" locked="false"/>
|
||||
<setting id="ANADIG_OSC_OSC_24M_CTRL_OSC_EN_CFG" value="Enabled" locked="false"/>
|
||||
<setting id="ANADIG_PLL.PLL_AUDIO_BYPASS.sel" value="ANADIG_OSC.OSC_24M" locked="false"/>
|
||||
<setting id="ANADIG_PLL.PLL_VIDEO.denom" value="960000" locked="false"/>
|
||||
<setting id="ANADIG_PLL.PLL_VIDEO.div" value="41" locked="false"/>
|
||||
<setting id="ANADIG_PLL.PLL_VIDEO.num" value="1" locked="false"/>
|
||||
<setting id="ANADIG_PLL.SYS_PLL1_BYPASS.sel" value="ANADIG_OSC.OSC_24M" locked="false"/>
|
||||
<setting id="ANADIG_PLL.SYS_PLL2.denom" value="268435455" locked="false"/>
|
||||
<setting id="ANADIG_PLL.SYS_PLL2.div" value="22" locked="false"/>
|
||||
<setting id="ANADIG_PLL.SYS_PLL2.num" value="0" locked="false"/>
|
||||
<setting id="ANADIG_PLL.SYS_PLL2_SS_DIV.scale" value="268435455" locked="false"/>
|
||||
<setting id="ANADIG_PLL.SYS_PLL3_PFD3_DIV.scale" value="22" locked="true"/>
|
||||
<setting id="ANADIG_PLL.SYS_PLL3_PFD3_MUL.scale" value="18" locked="true"/>
|
||||
<setting id="ANADIG_PLL_ARM_PLL_CTRL_POWERUP_CFG" value="Enabled" locked="false"/>
|
||||
<setting id="ANADIG_PLL_PLL_AUDIO_CTRL_GATE_CFG" value="Disabled" locked="false"/>
|
||||
<setting id="ANADIG_PLL_PLL_VIDEO_CTRL0_POWERUP_CFG" value="Enabled" locked="false"/>
|
||||
<setting id="ANADIG_PLL_SYS_PLL1_CTRL0_POWERUP_CFG" value="Disabled" locked="false"/>
|
||||
<setting id="ANADIG_PLL_SYS_PLL1_CTRL_GATE_CFG" value="Disabled" locked="false"/>
|
||||
<setting id="ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_CFG" value="Enabled" locked="false"/>
|
||||
<setting id="ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_CFG" value="Enabled" locked="false"/>
|
||||
<setting id="ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CFG" value="Enabled" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT0.MUX.sel" value="ANADIG_PLL.ARM_PLL_CLK" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT1.MUX.sel" value="ANADIG_PLL.SYS_PLL3_PFD3_CLK" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT2.DIV.scale" value="2" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT2.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT25.DIV.scale" value="22" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT25.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT26.DIV.scale" value="22" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT26.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT3.DIV.scale" value="3" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT3.MUX.sel" value="ANADIG_PLL.SYS_PLL3_CLK" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT4.DIV.scale" value="3" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT4.MUX.sel" value="ANADIG_PLL.SYS_PLL2_PFD1_CLK" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT6.DIV.scale" value="4" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT6.MUX.sel" value="ANADIG_PLL.SYS_PLL2_CLK" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT68.DIV.scale" value="2" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT68.MUX.sel" value="ANADIG_PLL.PLL_VIDEO_CLK" locked="false"/>
|
||||
<setting id="CCM.CLOCK_ROOT8.DIV.scale" value="240" locked="false"/>
|
||||
</clock_settings>
|
||||
<called_from_default_init>true</called_from_default_init>
|
||||
</clock_configuration>
|
||||
</clock_configurations>
|
||||
</clocks>
|
||||
<dcdx name="DCDx" version="3.0" enabled="true" update_project_code="true">
|
||||
<generated_project_files>
|
||||
<file path="board/dcd.c" update_enabled="true"/>
|
||||
<file path="board/dcd.h" update_enabled="true"/>
|
||||
</generated_project_files>
|
||||
<dcdx_profile>
|
||||
<processor_version>13.0.2</processor_version>
|
||||
<output_format>c_array</output_format>
|
||||
</dcdx_profile>
|
||||
<dcdx_configurations>
|
||||
<dcdx_configuration name="Device_configuration">
|
||||
<description></description>
|
||||
<options/>
|
||||
<command_groups>
|
||||
<command_group name="Imported Commands" enabled="true">
|
||||
<commands>
|
||||
<command type="write_value" address="CCM_CLOCK_ROOT4_CONTROL" value="0x703" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39" value="0x10" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17" value="0x08" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_MCR" value="0x10000004" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BMCR0" value="0x81" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BMCR1" value="0x81" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_BR0" value="0x8000001D" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_SDRAMCR0" value="0xF32" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_SDRAMCR1" value="0x772A22" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_SDRAMCR2" value="0x10A0D" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_SDRAMCR3" value="0x21210408" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCR0" value="0x80000000" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCR1" value="0x02" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCR2" value="0x00" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCMD" value="0xA55A000F" value_width="4"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCMD" value="0xA55A000C" value_width="4"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCMD" value="0xA55A000C" value_width="4"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPTXDAT" value="0x33" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_IPCMD" value="0xA55A000A" value_width="4"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="nop"/>
|
||||
<command type="write_value" address="SEMC_INTR" value="0x03" value_width="4"/>
|
||||
<command type="write_value" address="SEMC_SDRAMCR3" value="0x21210409" value_width="4"/>
|
||||
</commands>
|
||||
</command_group>
|
||||
</command_groups>
|
||||
</dcdx_configuration>
|
||||
</dcdx_configurations>
|
||||
</dcdx>
|
||||
<periphs name="Peripherals" version="12.0" enabled="false" update_project_code="true">
|
||||
<dependencies>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="LPUART Driver not found in the toolchain/IDE project. Project will not compile!" problem_level="2" source="Peripherals">
|
||||
<feature name="enabled" evaluation="equal">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="SWComponent" resourceId="platform.drivers.lpuart" description="Unsupported version of the LPUART Driver in the toolchain/IDE project. Required: ${required_value}, actual: ${actual_value}. Project might not compile correctly." problem_level="1" source="Peripherals">
|
||||
<feature name="version" evaluation="equivalent">
|
||||
<data type="Version">2.5.1</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<generated_project_files/>
|
||||
<peripherals_profile>
|
||||
<processor_version>13.0.2</processor_version>
|
||||
</peripherals_profile>
|
||||
<functional_groups>
|
||||
<functional_group name="BOARD_InitPeripherals" uuid="5580249f-8696-4d01-87fa-efd84baaea95" called_from_default_init="true" id_prefix="" core="cm7">
|
||||
<description></description>
|
||||
<options/>
|
||||
<dependencies>
|
||||
<dependency resourceType="ClockOutput" resourceId="LPUART1_CLK_ROOT" description="LPUART1 clock root is inactive." problem_level="2" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="frequency" evaluation="greaterThan">
|
||||
<data type="Frequency" unit="Hz">0</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_tx" description="Signal TX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="routed" evaluation="equal">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
<dependency resourceType="PeripheralUnifiedSignal" resourceId="LPUART1.uart_rx" description="Signal RX is not routed." problem_level="1" source="Peripherals:BOARD_InitPeripherals">
|
||||
<feature name="routed" evaluation="equal">
|
||||
<data type="Boolean">true</data>
|
||||
</feature>
|
||||
</dependency>
|
||||
</dependencies>
|
||||
<instances>
|
||||
<instance name="NVIC" uuid="27e59fb2-3864-4b83-bf0e-a683a8582c73" type="nvic" type_id="nvic_57b5eef3774cc60acaede6f5b8bddc67" mode="general" peripheral="NVIC" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
||||
<config_set name="nvic">
|
||||
<array name="interrupt_table"/>
|
||||
<array name="interrupts"/>
|
||||
</config_set>
|
||||
</instance>
|
||||
<instance name="LPUART1" uuid="78f9b1b2-5105-4480-a25a-29d8172b6270" type="lpuart" type_id="lpuart_bf01db7d964092f3cf860852cba17f7e" mode="polling" peripheral="LPUART1" enabled="true" comment="" custom_name_enabled="false" editing_lock="false">
|
||||
<config_set name="lpuartConfig_t" quick_selection="QuickSelection1">
|
||||
<struct name="lpuartConfig">
|
||||
<setting name="clockSource" value="LpuartClock"/>
|
||||
<setting name="lpuartSrcClkFreq" value="ClocksTool_DefaultInit"/>
|
||||
<setting name="baudRate_Bps" value="115200"/>
|
||||
<setting name="parityMode" value="kLPUART_ParityDisabled"/>
|
||||
<setting name="dataBitsCount" value="kLPUART_EightDataBits"/>
|
||||
<setting name="isMsb" value="false"/>
|
||||
<setting name="stopBitCount" value="kLPUART_OneStopBit"/>
|
||||
<setting name="enableMatchAddress1" value="false"/>
|
||||
<setting name="matchAddress1" value="0"/>
|
||||
<setting name="enableMatchAddress2" value="false"/>
|
||||
<setting name="matchAddress2" value="0"/>
|
||||
<setting name="txFifoWatermark" value="0"/>
|
||||
<setting name="rxFifoWatermark" value="1"/>
|
||||
<setting name="enableRxRTS" value="false"/>
|
||||
<setting name="enableTxCTS" value="false"/>
|
||||
<setting name="txCtsSource" value="kLPUART_CtsSourcePin"/>
|
||||
<setting name="txCtsConfig" value="kLPUART_CtsSampleAtStart"/>
|
||||
<setting name="rxIdleType" value="kLPUART_IdleTypeStartBit"/>
|
||||
<setting name="rxIdleConfig" value="kLPUART_IdleCharacter1"/>
|
||||
<setting name="enableTx" value="true"/>
|
||||
<setting name="enableRx" value="true"/>
|
||||
</struct>
|
||||
</config_set>
|
||||
</instance>
|
||||
</instances>
|
||||
</functional_group>
|
||||
</functional_groups>
|
||||
<components>
|
||||
<component name="system" uuid="cd2726b0-9595-440c-9375-bb6a010a1d55" type_id="system_54b53072540eeeb8f8e9343e71f28176">
|
||||
<config_set_global name="global_system_definitions">
|
||||
<setting name="user_definitions" value=""/>
|
||||
<setting name="user_includes" value=""/>
|
||||
</config_set_global>
|
||||
</component>
|
||||
<component name="msg" uuid="2491c39d-c21a-45f3-a984-57be0f6a77b5" type_id="msg_6e2baaf3b97dbeef01c0043275f9a0e7">
|
||||
<config_set_global name="global_messages"/>
|
||||
</component>
|
||||
<component name="gpio_adapter_common" uuid="fefc514e-ed7f-48ad-a874-de332dd5eb13" type_id="gpio_adapter_common_57579b9ac814fe26bf95df0a384c36b6">
|
||||
<config_set_global name="global_gpio_adapter_common" quick_selection="default"/>
|
||||
</component>
|
||||
<component name="generic_uart" uuid="1dc54607-ada6-4731-ad75-479a19616c00" type_id="generic_uart_8cae00565451cf2346eb1b8c624e73a6">
|
||||
<config_set_global name="global_uart"/>
|
||||
</component>
|
||||
<component name="generic_can" uuid="88660053-1bc1-49b8-884c-a12532e98a7a" type_id="generic_can_1bfdd78b1af214566c1f23cf6a582d80">
|
||||
<config_set_global name="global_can"/>
|
||||
</component>
|
||||
<component name="uart_cmsis_common" uuid="9d37100d-c1fb-4f7e-b235-a952c5b03275" type_id="uart_cmsis_common_9cb8e302497aa696fdbb5a4fd622c2a8">
|
||||
<config_set_global name="global_USART_CMSIS_common" quick_selection="default"/>
|
||||
</component>
|
||||
<component name="generic_enet" uuid="ad9ccf5d-6535-4f75-bb23-abb7e6fcc950" type_id="generic_enet_74db5c914f0ddbe47d86af40cb77a619">
|
||||
<config_set_global name="global_enet"/>
|
||||
</component>
|
||||
</components>
|
||||
</periphs>
|
||||
<tee name="TEE" version="4.0" enabled="false" update_project_code="true">
|
||||
<generated_project_files/>
|
||||
<tee_profile>
|
||||
<processor_version>N/A</processor_version>
|
||||
</tee_profile>
|
||||
</tee>
|
||||
</tools>
|
||||
</configuration>
|
||||
@ -25,7 +25,6 @@
|
||||
*/
|
||||
|
||||
#include "bsp/board_api.h"
|
||||
#include "board.h"
|
||||
|
||||
// Suppress warning caused by mcu driver
|
||||
#ifdef __GNUC__
|
||||
@ -44,6 +43,9 @@
|
||||
#endif
|
||||
|
||||
#include "clock_config.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
#include "board.h"
|
||||
|
||||
#if defined(BOARD_TUD_RHPORT) && CFG_TUD_ENABLED
|
||||
#define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n)
|
||||
@ -58,8 +60,7 @@
|
||||
#endif
|
||||
|
||||
// needed by fsl_flexspi_nor_boot
|
||||
TU_ATTR_USED
|
||||
const uint8_t dcd_data[] = { 0x00 };
|
||||
TU_ATTR_USED const uint8_t dcd_data[] = { 0x00 };
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
//
|
||||
@ -87,23 +88,20 @@ void board_init(void)
|
||||
if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) SCB_EnableDCache();
|
||||
#endif
|
||||
|
||||
// Init clock
|
||||
BOARD_InitPins();
|
||||
BOARD_BootClockRUN();
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
#ifdef TRACE_ETM
|
||||
// RT1011 ETM pins
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_11_ARM_TRACE3, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_12_ARM_TRACE2, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_13_ARM_TRACE1, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0U);
|
||||
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0U);
|
||||
CLOCK_EnableClock(kCLOCK_Trace);
|
||||
// IOMUXC_SetPinMux(IOMUXC_GPIO_11_ARM_TRACE3, 0U);
|
||||
// IOMUXC_SetPinMux(IOMUXC_GPIO_12_ARM_TRACE2, 0U);
|
||||
// IOMUXC_SetPinMux(IOMUXC_GPIO_13_ARM_TRACE1, 0U);
|
||||
// IOMUXC_SetPinMux(IOMUXC_GPIO_AD_00_ARM_TRACE0, 0U);
|
||||
// IOMUXC_SetPinMux(IOMUXC_GPIO_AD_02_ARM_TRACE_CLK, 0U);
|
||||
// CLOCK_EnableClock(kCLOCK_Trace);
|
||||
#endif
|
||||
|
||||
// Enable IOCON clock
|
||||
CLOCK_EnableClock(kCLOCK_Iomuxc);
|
||||
|
||||
#if CFG_TUSB_OS == OPT_OS_NONE
|
||||
// 1ms tick timer
|
||||
SysTick_Config(SystemCoreClock / 1000);
|
||||
@ -117,24 +115,24 @@ void board_init(void)
|
||||
#endif
|
||||
|
||||
// LED
|
||||
IOMUXC_SetPinMux( LED_PINMUX, 0U);
|
||||
IOMUXC_SetPinConfig( LED_PINMUX, 0x10B0U);
|
||||
// IOMUXC_SetPinMux( LED_PINMUX, 0U);
|
||||
// IOMUXC_SetPinConfig( LED_PINMUX, 0x10B0U);
|
||||
|
||||
gpio_pin_config_t led_config = { kGPIO_DigitalOutput, 0, kGPIO_NoIntmode };
|
||||
GPIO_PinInit(LED_PORT, LED_PIN, &led_config);
|
||||
board_led_write(true);
|
||||
|
||||
// Button
|
||||
IOMUXC_SetPinMux( BUTTON_PINMUX, 0U);
|
||||
IOMUXC_SetPinConfig(BUTTON_PINMUX, 0x01B0A0U);
|
||||
gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0, kGPIO_IntRisingEdge, };
|
||||
// IOMUXC_SetPinMux( BUTTON_PINMUX, 0U);
|
||||
// IOMUXC_SetPinConfig(BUTTON_PINMUX, 0x01B0A0U);
|
||||
gpio_pin_config_t button_config = { kGPIO_DigitalInput, 0, kGPIO_NoIntmode};
|
||||
GPIO_PinInit(BUTTON_PORT, BUTTON_PIN, &button_config);
|
||||
|
||||
// UART
|
||||
IOMUXC_SetPinMux( UART_TX_PINMUX, 0U);
|
||||
IOMUXC_SetPinMux( UART_RX_PINMUX, 0U);
|
||||
IOMUXC_SetPinConfig( UART_TX_PINMUX, 0x10B0u);
|
||||
IOMUXC_SetPinConfig( UART_RX_PINMUX, 0x10B0u);
|
||||
// IOMUXC_SetPinMux( UART_TX_PINMUX, 0U);
|
||||
// IOMUXC_SetPinMux( UART_RX_PINMUX, 0U);
|
||||
// IOMUXC_SetPinConfig( UART_TX_PINMUX, 0x10B0u);
|
||||
// IOMUXC_SetPinConfig( UART_RX_PINMUX, 0x10B0u);
|
||||
|
||||
lpuart_config_t uart_config;
|
||||
LPUART_GetDefaultConfig(&uart_config);
|
||||
@ -142,15 +140,12 @@ void board_init(void)
|
||||
uart_config.enableTx = true;
|
||||
uart_config.enableRx = true;
|
||||
|
||||
uint32_t freq;
|
||||
if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
|
||||
{
|
||||
freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
}
|
||||
else
|
||||
{
|
||||
freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
}
|
||||
uint32_t freq = board_uart_get_clock();
|
||||
// if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */ {
|
||||
// freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
// } else {
|
||||
// freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
|
||||
// }
|
||||
|
||||
if ( kStatus_Success != LPUART_Init(UART_PORT, &uart_config, freq) ) {
|
||||
// failed to init uart, probably baudrate is not supported
|
||||
@ -181,25 +176,23 @@ void board_init(void)
|
||||
//--------------------------------------------------------------------+
|
||||
// USB Interrupt Handler
|
||||
//--------------------------------------------------------------------+
|
||||
void USB_OTG1_IRQHandler(void)
|
||||
{
|
||||
void USB_OTG1_IRQHandler(void) {
|
||||
#if PORT_SUPPORT_DEVICE(0)
|
||||
tud_int_handler(0);
|
||||
tud_int_handler(0);
|
||||
#endif
|
||||
|
||||
#if PORT_SUPPORT_HOST(0)
|
||||
tuh_int_handler(0, true);
|
||||
tuh_int_handler(0, true);
|
||||
#endif
|
||||
}
|
||||
|
||||
void USB_OTG2_IRQHandler(void)
|
||||
{
|
||||
void USB_OTG2_IRQHandler(void) {
|
||||
#if PORT_SUPPORT_DEVICE(1)
|
||||
tud_int_handler(1);
|
||||
tud_int_handler(1);
|
||||
#endif
|
||||
|
||||
#if PORT_SUPPORT_HOST(1)
|
||||
tuh_int_handler(1, true);
|
||||
tuh_int_handler(1, true);
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -207,35 +200,29 @@ void USB_OTG2_IRQHandler(void)
|
||||
// Board porting API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
void board_led_write(bool state)
|
||||
{
|
||||
GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1-LED_STATE_ON));
|
||||
void board_led_write(bool state) {
|
||||
GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON));
|
||||
}
|
||||
|
||||
uint32_t board_button_read(void)
|
||||
{
|
||||
// active low
|
||||
uint32_t board_button_read(void) {
|
||||
return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN);
|
||||
}
|
||||
|
||||
int board_uart_read(uint8_t* buf, int len)
|
||||
{
|
||||
int board_uart_read(uint8_t* buf, int len) {
|
||||
int count = 0;
|
||||
|
||||
while( count < len )
|
||||
{
|
||||
while (count < len) {
|
||||
uint8_t const rx_count = LPUART_GetRxFifoCount(UART_PORT);
|
||||
if (!rx_count)
|
||||
{
|
||||
if (!rx_count) {
|
||||
// clear all error flag if any
|
||||
uint32_t status_flags = LPUART_GetStatusFlags(UART_PORT);
|
||||
status_flags &= (kLPUART_RxOverrunFlag | kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag | kLPUART_NoiseErrorFlag);
|
||||
status_flags &= (kLPUART_RxOverrunFlag | kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag |
|
||||
kLPUART_NoiseErrorFlag);
|
||||
LPUART_ClearStatusFlags(UART_PORT, status_flags);
|
||||
break;
|
||||
}
|
||||
|
||||
for(int i=0; i<rx_count; i++)
|
||||
{
|
||||
for (int i = 0; i < rx_count; i++) {
|
||||
buf[count] = LPUART_ReadByte(UART_PORT);
|
||||
count++;
|
||||
}
|
||||
|
||||
@ -9,6 +9,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5)
|
||||
|
||||
# include board specific
|
||||
include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
|
||||
set(MCU_VARIANT_WITH_CORE ${MCU_VARIANT}${MCU_CORE})
|
||||
|
||||
# toolchain set up
|
||||
set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor")
|
||||
@ -16,7 +17,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/tools/cmake/toolchain/arm_${TOOLCHAIN}.cmake)
|
||||
|
||||
set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "")
|
||||
|
||||
|
||||
#------------------------------------
|
||||
# BOARD_TARGET
|
||||
#------------------------------------
|
||||
@ -28,15 +28,25 @@ function(add_board_target BOARD_TARGET)
|
||||
|
||||
add_library(${BOARD_TARGET} STATIC
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/clock_config.c
|
||||
#${SDK_DIR}/drivers/adc_12b1msps_sar/fsl_adc.c
|
||||
${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board/pin_mux.c
|
||||
${SDK_DIR}/drivers/common/fsl_common.c
|
||||
${SDK_DIR}/drivers/common/fsl_common_arm.c
|
||||
${SDK_DIR}/drivers/igpio/fsl_gpio.c
|
||||
${SDK_DIR}/drivers/lpspi/fsl_lpspi.c
|
||||
${SDK_DIR}/drivers/lpuart/fsl_lpuart.c
|
||||
${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT}.c
|
||||
${SDK_DIR}/devices/${MCU_VARIANT}/system_${MCU_VARIANT_WITH_CORE}.c
|
||||
${SDK_DIR}/devices/${MCU_VARIANT}/xip/fsl_flexspi_nor_boot.c
|
||||
${SDK_DIR}/devices/${MCU_VARIANT}/drivers/fsl_clock.c
|
||||
)
|
||||
|
||||
# Optional drivers: only available for some mcus: rt1160, rt1170
|
||||
set(OPTIONAL_DRIVER fsl_dcdc.c fsl_pmu.c fsl_anatop_ai.c)
|
||||
foreach(FILE IN LISTS OPTIONAL_DRIVER)
|
||||
if(EXISTS ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/${FILE})
|
||||
target_sources(${BOARD_TARGET} PRIVATE ${SDK_DIR}/devices/${MCU_VARIANT}/drivers/${FILE})
|
||||
endif()
|
||||
endforeach()
|
||||
|
||||
target_compile_definitions(${BOARD_TARGET} PUBLIC
|
||||
__ARMVFP__=0
|
||||
__ARMFPV5__=0
|
||||
@ -60,13 +70,13 @@ function(add_board_target BOARD_TARGET)
|
||||
|
||||
# LD_FILE and STARTUP_FILE can be defined in board.cmake
|
||||
if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID})
|
||||
set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
|
||||
set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.ld)
|
||||
#set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld)
|
||||
endif ()
|
||||
|
||||
if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID})
|
||||
set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
|
||||
#set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT}.S)
|
||||
set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S)
|
||||
#set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S)
|
||||
endif ()
|
||||
|
||||
target_sources(${BOARD_TARGET} PUBLIC
|
||||
|
||||
@ -6,6 +6,8 @@ include $(TOP)/$(BOARD_PATH)/board.mk
|
||||
|
||||
CPU_CORE ?= cortex-m7
|
||||
|
||||
MCU_VARIANT_WITH_CORE = ${MCU_VARIANT}${MCU_CORE}
|
||||
|
||||
CFLAGS += \
|
||||
-D__ARMVFP__=0 \
|
||||
-D__ARMFPV5__=0 \
|
||||
@ -27,7 +29,7 @@ CFLAGS += -Wno-error=unused-parameter -Wno-error=implicit-fallthrough -Wno-error
|
||||
MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT)
|
||||
|
||||
# All source paths should be relative to the top level.
|
||||
LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx_flexspi_nor.ld
|
||||
LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx${MCU_CORE}_flexspi_nor.ld
|
||||
|
||||
# TODO for net_lwip_webserver example, but may not needed !!
|
||||
LDFLAGS += \
|
||||
@ -37,14 +39,24 @@ SRC_C += \
|
||||
src/portable/chipidea/ci_hs/dcd_ci_hs.c \
|
||||
src/portable/chipidea/ci_hs/hcd_ci_hs.c \
|
||||
src/portable/ehci/ehci.c \
|
||||
$(MCU_DIR)/system_$(MCU_VARIANT).c \
|
||||
${BOARD_PATH}/board/clock_config.c \
|
||||
${BOARD_PATH}/board/pin_mux.c \
|
||||
$(MCU_DIR)/system_$(MCU_VARIANT_WITH_CORE).c \
|
||||
$(MCU_DIR)/xip/fsl_flexspi_nor_boot.c \
|
||||
$(MCU_DIR)/project_template/clock_config.c \
|
||||
$(MCU_DIR)/drivers/fsl_clock.c \
|
||||
$(SDK_DIR)/drivers/common/fsl_common.c \
|
||||
$(SDK_DIR)/drivers/common/fsl_common_arm.c \
|
||||
$(SDK_DIR)/drivers/igpio/fsl_gpio.c \
|
||||
$(SDK_DIR)/drivers/lpuart/fsl_lpuart.c
|
||||
|
||||
# Optional drivers: only available for some mcus: rt1160, rt1170
|
||||
ifneq (,$(wildcard ${TOP}/${MCU_DIR}/drivers/fsl_dcdc.c))
|
||||
SRC_C += \
|
||||
${MCU_DIR}/drivers/fsl_dcdc.c \
|
||||
${MCU_DIR}/drivers/fsl_pmu.c \
|
||||
${MCU_DIR}/drivers/fsl_anatop_ai.c
|
||||
endif
|
||||
|
||||
INC += \
|
||||
$(TOP)/$(BOARD_PATH) \
|
||||
$(TOP)/lib/CMSIS_5/CMSIS/Core/Include \
|
||||
@ -55,7 +67,7 @@ INC += \
|
||||
$(TOP)/$(SDK_DIR)/drivers/igpio \
|
||||
$(TOP)/$(SDK_DIR)/drivers/lpuart
|
||||
|
||||
SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT).S
|
||||
SRC_S += $(MCU_DIR)/gcc/startup_$(MCU_VARIANT_WITH_CORE).S
|
||||
|
||||
# UF2 generation, iMXRT need to strip to text only before conversion
|
||||
APPLICATION_ADDR = 0x6000C000
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user