mirror of
https://github.com/hathach/tinyusb.git
synced 2025-02-15 21:40:18 +00:00
fix freertos build with iar, format/indent link_type
This commit is contained in:
hathach
parent
05e0205ad0
commit
2cf092464b
@ -1 +1,4 @@
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return USB0.INTSTS1.BIT.ATTCH ? true : false;
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return LINK_REG->INTSTS1_b.ATTCH ? true : false;
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volatile uint16_t ATTCH : 1; /* [11..11] ATTCH Interrupt Status */
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#define LINK_REG_INTSTS1_ATTCH_Pos (11UL) /* ATTCH (Bit 11) */
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#define LINK_REG_INTSTS1_ATTCH_Msk (0x800UL) /* ATTCH (Bitfield-Mask: 0x01) */
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@ -30,7 +30,7 @@ SRC_C += \
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$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.c))
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SRC_S += \
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$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
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$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.s))
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# include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1
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# SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c
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@ -29,7 +29,7 @@ SRC_C += \
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$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.c))
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SRC_S += \
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$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s))
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$(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORT)/*.s))
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# include heap manage if configSUPPORT_DYNAMIC_ALLOCATION = 1
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# SRC_C += $(FREERTOS_SRC)/portable/MemMang/heap_1.c
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@ -62,8 +62,6 @@ typedef struct TU_ATTR_PACKED {
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};
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} LINK_REG_PIPE_TR_t; /* Size = 4 (0x4) */
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TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size");
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/* LINK_REG Structure */
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typedef struct TU_ATTR_PACKED {
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union {
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@ -88,8 +86,7 @@ typedef struct TU_ATTR_PACKED {
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volatile uint16_t BUSWAIT; /* (@ 0x00000002) CPU Bus Wait Register */
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struct {
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volatile uint16_t
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BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
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volatile uint16_t BWAIT : 4; /* [3..0] CPU Bus Access Wait Specification BWAIT waits (BWAIT+2 access cycles) */
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uint16_t : 12;
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} BUSWAIT_b;
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};
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@ -105,8 +102,7 @@ typedef struct TU_ATTR_PACKED {
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SOFEA : 1; /* [5..5] SOF Active Monitor While Host Controller Function is Selected. */
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volatile const uint16_t HTACT : 1; /* [6..6] USB Host Sequencer Status Monitor */
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uint16_t : 7;
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volatile const uint16_t
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OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
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volatile const uint16_t OVCMON : 2; /* [15..14] External USB0_OVRCURA/ USB0_OVRCURB Input Pin Monitor */
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} SYSSTS0_b;
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};
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@ -230,8 +226,7 @@ typedef struct TU_ATTR_PACKED {
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volatile uint16_t CFIFOCTR; /* (@ 0x00000022) CFIFO Port Control Register */
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struct {
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volatile const uint16_t
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DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
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volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
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uint16_t : 1;
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volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
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volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
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@ -250,8 +245,7 @@ typedef struct TU_ATTR_PACKED {
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uint16_t : 1;
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volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */
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volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
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volatile uint16_t
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DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
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volatile uint16_t DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
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volatile uint16_t REW : 1; /* [14..14] Buffer Pointer RewindNote: Only 0 can be read. */
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volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
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} D0FIFOSEL_b;
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@ -261,8 +255,7 @@ typedef struct TU_ATTR_PACKED {
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volatile uint16_t D0FIFOCTR; /* (@ 0x0000002A) D0FIFO Port Control Register */
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struct {
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volatile const uint16_t
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DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
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volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
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uint16_t : 1;
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volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
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volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
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@ -280,8 +273,7 @@ typedef struct TU_ATTR_PACKED {
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uint16_t : 1;
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volatile uint16_t MBW : 2; /* [11..10] FIFO Port Access Bit Width */
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volatile uint16_t DREQE : 1; /* [12..12] DMA/DTC Transfer Request Enable */
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volatile uint16_t
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DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
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volatile uint16_t DCLRM : 1; /* [13..13] Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read */
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volatile uint16_t REW : 1; /* [14..14] Buffer Pointer Rewind */
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volatile uint16_t RCNT : 1; /* [15..15] Read Count Mode */
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} D1FIFOSEL_b;
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@ -291,8 +283,7 @@ typedef struct TU_ATTR_PACKED {
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volatile uint16_t D1FIFOCTR; /* (@ 0x0000002E) D1FIFO Port Control Register */
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struct {
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volatile const uint16_t
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DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
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volatile const uint16_t DTLN : 12; /* [11..0] Receive Data LengthIndicates the length of the receive data. */
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uint16_t : 1;
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volatile const uint16_t FRDY : 1; /* [13..13] FIFO Port Ready */
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volatile uint16_t BCLR : 1; /* [14..14] CPU Buffer ClearNote: Only 0 can be read. */
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@ -553,8 +544,7 @@ typedef struct TU_ATTR_PACKED {
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volatile uint16_t USBREQ; /* (@ 0x00000054) USB Request Type Register */
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struct {
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volatile uint16_t
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BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */
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volatile uint16_t BMREQUESTTYPE : 8; /* [7..0] Request TypeThese bits store the USB request bmRequestType value. */
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volatile uint16_t BREQUEST : 8; /* [15..8] RequestThese bits store the USB request bRequest value. */
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} USBREQ_b;
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};
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@ -815,8 +805,7 @@ typedef struct TU_ATTR_PACKED {
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volatile uint16_t L1RESPEN : 1; /* [0..0] L1 Response Enable */
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volatile uint16_t L1RESPMD : 2; /* [2..1] L1 Response Mode */
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volatile uint16_t L1NEGOMD : 1; /* [3..3] L1 Response Negotiation Control. */
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volatile const uint16_t
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DVSQ : 4; /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */
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volatile const uint16_t DVSQ : 4; /* [7..4] DVSQ Extension.DVSQ[3] is Mirror of DVSQ[2:0] in INTSTS0. */
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volatile uint16_t HIRDTHR : 4; /* [11..8] L1 Response Negotiation Threshold Value */
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uint16_t : 2;
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volatile uint16_t L1EXTMD : 1; /* [14..14] PHY Control Mode at L1 Return */
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@ -864,13 +853,10 @@ typedef struct TU_ATTR_PACKED {
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struct {
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uint32_t : 20;
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volatile const uint32_t
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DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
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volatile const uint32_t
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DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
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volatile const uint32_t DOVCAHM : 1; /* [20..20] OVRCURA InputIndicates OVRCURA input signal on the HS side of USB port. */
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volatile const uint32_t DOVCBHM : 1; /* [21..21] OVRCURB InputIndicates OVRCURB input signal on the HS side of USB port. */
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uint32_t : 1;
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volatile const uint32_t
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DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
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volatile const uint32_t DVBSTSHM : 1; /* [23..23] VBUS InputIndicates VBUS input signal on the HS side of USB port. */
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uint32_t : 8;
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} DPUSR0R_b;
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};
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@ -900,10 +886,8 @@ typedef struct TU_ATTR_PACKED {
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volatile const uint16_t DPINT : 1; /* [0..0] Indication of Return from DP Interrupt Source */
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volatile const uint16_t DMINT : 1; /* [1..1] Indication of Return from DM Interrupt Source */
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uint16_t : 2;
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volatile const uint16_t
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DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */
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volatile const uint16_t
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DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */
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volatile const uint16_t DPVAL : 1; /* [4..4] DP InputIndicates DP input signal on the HS side of USB port. */
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volatile const uint16_t DMVAL : 1; /* [5..5] DM InputIndicates DM input signal on the HS side of USB port. */
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uint16_t : 2;
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volatile uint16_t DPINTE : 1; /* [8..8] DP Interrupt Enable Clear */
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volatile uint16_t DMINTE : 1; /* [9..9] DM Interrupt Enable Clear */
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@ -936,13 +920,10 @@ typedef struct TU_ATTR_PACKED {
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volatile const uint32_t DP0 : 1; /* [16..16] USB0 D+ InputIndicates the D+ input signal of the USB. */
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volatile const uint32_t DM0 : 1; /* [17..17] USB D-InputIndicates the D- input signal of the USB. */
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uint32_t : 2;
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volatile const uint32_t
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DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */
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volatile const uint32_t
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DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
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volatile const uint32_t DOVCA0 : 1; /* [20..20] USB OVRCURA InputIndicates the OVRCURA input signal of the USB. */
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volatile const uint32_t DOVCB0 : 1; /* [21..21] USB OVRCURB InputIndicates the OVRCURB input signal of the USB. */
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uint32_t : 1;
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volatile const uint32_t
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DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
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volatile const uint32_t DVBSTS0 : 1; /* [23..23] USB VBUS InputIndicates the VBUS input signal of the USB. */
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uint32_t : 8;
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} DPUSR0R_FS_b;
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};
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@ -971,68 +952,6 @@ typedef struct TU_ATTR_PACKED {
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};
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} LINK_REG_t; /* Size = 1032 (0x408) */
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG) == 0x00000000, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, BUSWAIT) == 0x00000002, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSSTS0) == 0x00000004, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, PLLSTA) == 0x00000006, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, DVSTCTR0) == 0x00000008, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, TESTMODE) == 0x0000000C, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFO) == 0x00000014, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFO) == 0x00000018, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFO) == 0x0000001C, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOSEL) == 0x00000020, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOCTR) == 0x00000022, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOSEL) == 0x00000028, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOCTR) == 0x0000002A, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOSEL) == 0x0000002C, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOCTR) == 0x0000002E, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB0) == 0x00000030, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB1) == 0x00000032, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYENB) == 0x00000036, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYENB) == 0x00000038, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPENB) == 0x0000003A, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, SOFCFG) == 0x0000003C, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSET) == 0x0000003E, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS0) == 0x00000040, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS1) == 0x00000042, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYSTS) == 0x00000046, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYSTS) == 0x00000048, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPSTS) == 0x0000004A, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, FRMNUM) == 0x0000004C, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, UFRMNUM) == 0x0000004E, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBADDR) == 0x00000050, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBREQ) == 0x00000054, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBVAL) == 0x00000056, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBINDX) == 0x00000058, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBLENG) == 0x0000005A, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCFG) == 0x0000005C, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPMAXP) == 0x0000005E, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCTR) == 0x00000060, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPESEL) == 0x00000064, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPECFG) == 0x00000068, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEMAXP) == 0x0000006C, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEPERI) == 0x0000006E, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_CTR) == 0x00000070, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_TR) == 0x00000090, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBBCCTRL0) == 0x000000B0, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, UCKSEL) == 0x000000C4, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBMC) == 0x000000CC, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, DEVADD) == 0x000000D0, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSLEW) == 0x000000F0, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPCTRL) == 0x00000100, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPSTS) == 0x00000102, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, BCCTRL) == 0x00000140, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL1) == 0x00000144, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL2) == 0x00000146, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL1) == 0x00000148, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL2) == 0x0000014A, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R) == 0x00000160, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R) == 0x00000164, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR2R) == 0x00000168, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSRCR) == 0x0000016A, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS) == 0x00000400, "incorrect offset");
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TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS) == 0x00000404, "incorrect offset");
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TU_ATTR_PACKED_END /* End of definition of packed structs (used by the CCRX toolchain) */
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TU_ATTR_BIT_FIELD_ORDER_END
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@ -1040,18 +959,20 @@ TU_ATTR_BIT_FIELD_ORDER_END
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/* Register Bit Definitions */
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/*--------------------------------------------------------------------*/
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/* PIPE_TR */
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/* E */
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// PIPE_TR
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// E
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#define LINK_REG_PIPE_TR_E_TRENB_Pos (9UL) /* TRENB (Bit 9) */
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#define LINK_REG_PIPE_TR_E_TRENB_Msk (0x200UL) /* TRENB (Bitfield-Mask: 0x01) */
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#define LINK_REG_PIPE_TR_E_TRCLR_Pos (8UL) /* TRCLR (Bit 8) */
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#define LINK_REG_PIPE_TR_E_TRCLR_Msk (0x100UL) /* TRCLR (Bitfield-Mask: 0x01) */
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/* N */
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// N
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#define LINK_REG_PIPE_TR_N_TRNCNT_Pos (0UL) /* TRNCNT (Bit 0) */
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#define LINK_REG_PIPE_TR_N_TRNCNT_Msk (0xffffUL) /* TRNCNT (Bitfield-Mask: 0xffff) */
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/* LINK_REG */
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/* SYSCFG */
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// LINK_REG
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// SYSCFG
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#define LINK_REG_SYSCFG_SCKE_Pos (10UL) /* SCKE (Bit 10) */
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#define LINK_REG_SYSCFG_SCKE_Msk (0x400UL) /* SCKE (Bitfield-Mask: 0x01) */
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#define LINK_REG_SYSCFG_CNEN_Pos (8UL) /* CNEN (Bit 8) */
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@ -1066,10 +987,12 @@ TU_ATTR_BIT_FIELD_ORDER_END
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#define LINK_REG_SYSCFG_DMRPU_Msk (0x8UL) /* DMRPU (Bitfield-Mask: 0x01) */
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#define LINK_REG_SYSCFG_USBE_Pos (0UL) /* USBE (Bit 0) */
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#define LINK_REG_SYSCFG_USBE_Msk (0x1UL) /* USBE (Bitfield-Mask: 0x01) */
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/* BUSWAIT */
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// BUSWAIT
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#define LINK_REG_BUSWAIT_BWAIT_Pos (0UL) /* BWAIT (Bit 0) */
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#define LINK_REG_BUSWAIT_BWAIT_Msk (0xfUL) /* BWAIT (Bitfield-Mask: 0x0f) */
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/* SYSSTS0 */
|
||||
|
||||
// SYSSTS0
|
||||
#define LINK_REG_SYSSTS0_OVCMON_Pos (14UL) /* OVCMON (Bit 14) */
|
||||
#define LINK_REG_SYSSTS0_OVCMON_Msk (0xc000UL) /* OVCMON (Bitfield-Mask: 0x03) */
|
||||
#define LINK_REG_SYSSTS0_HTACT_Pos (6UL) /* HTACT (Bit 6) */
|
||||
@ -1080,10 +1003,12 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_SYSSTS0_IDMON_Msk (0x4UL) /* IDMON (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_SYSSTS0_LNST_Pos (0UL) /* LNST (Bit 0) */
|
||||
#define LINK_REG_SYSSTS0_LNST_Msk (0x3UL) /* LNST (Bitfield-Mask: 0x03) */
|
||||
/* PLLSTA */
|
||||
|
||||
// PLLSTA
|
||||
#define LINK_REG_PLLSTA_PLLLOCK_Pos (0UL) /* PLLLOCK (Bit 0) */
|
||||
#define LINK_REG_PLLSTA_PLLLOCK_Msk (0x1UL) /* PLLLOCK (Bitfield-Mask: 0x01) */
|
||||
/* DVSTCTR0 */
|
||||
|
||||
// DVSTCTR0
|
||||
#define LINK_REG_DVSTCTR0_HNPBTOA_Pos (11UL) /* HNPBTOA (Bit 11) */
|
||||
#define LINK_REG_DVSTCTR0_HNPBTOA_Msk (0x800UL) /* HNPBTOA (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DVSTCTR0_EXICEN_Pos (10UL) /* EXICEN (Bit 10) */
|
||||
@ -1102,10 +1027,12 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_DVSTCTR0_UACT_Msk (0x10UL) /* UACT (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DVSTCTR0_RHST_Pos (0UL) /* RHST (Bit 0) */
|
||||
#define LINK_REG_DVSTCTR0_RHST_Msk (0x7UL) /* RHST (Bitfield-Mask: 0x07) */
|
||||
/* TESTMODE */
|
||||
|
||||
// TESTMODE
|
||||
#define LINK_REG_TESTMODE_UTST_Pos (0UL) /* UTST (Bit 0) */
|
||||
#define LINK_REG_TESTMODE_UTST_Msk (0xfUL) /* UTST (Bitfield-Mask: 0x0f) */
|
||||
/* CFIFOSEL */
|
||||
|
||||
// CFIFOSEL
|
||||
#define LINK_REG_CFIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */
|
||||
#define LINK_REG_CFIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_CFIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */
|
||||
@ -1118,7 +1045,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_CFIFOSEL_ISEL_Msk (0x20UL) /* ISEL (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_CFIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */
|
||||
#define LINK_REG_CFIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */
|
||||
/* CFIFOCTR */
|
||||
|
||||
// CFIFOCTR
|
||||
#define LINK_REG_CFIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */
|
||||
#define LINK_REG_CFIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_CFIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */
|
||||
@ -1127,7 +1055,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_CFIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_CFIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */
|
||||
#define LINK_REG_CFIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */
|
||||
/* D0FIFOSEL */
|
||||
|
||||
// D0FIFOSEL
|
||||
#define LINK_REG_D0FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */
|
||||
#define LINK_REG_D0FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_D0FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */
|
||||
@ -1142,7 +1071,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_D0FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_D0FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */
|
||||
#define LINK_REG_D0FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */
|
||||
/* D0FIFOCTR */
|
||||
|
||||
// D0FIFOCTR
|
||||
#define LINK_REG_D0FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */
|
||||
#define LINK_REG_D0FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_D0FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */
|
||||
@ -1151,7 +1081,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_D0FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_D0FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */
|
||||
#define LINK_REG_D0FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */
|
||||
/* D1FIFOSEL */
|
||||
|
||||
// D1FIFOSEL
|
||||
#define LINK_REG_D1FIFOSEL_RCNT_Pos (15UL) /* RCNT (Bit 15) */
|
||||
#define LINK_REG_D1FIFOSEL_RCNT_Msk (0x8000UL) /* RCNT (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_D1FIFOSEL_REW_Pos (14UL) /* REW (Bit 14) */
|
||||
@ -1166,7 +1097,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_D1FIFOSEL_BIGEND_Msk (0x100UL) /* BIGEND (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_D1FIFOSEL_CURPIPE_Pos (0UL) /* CURPIPE (Bit 0) */
|
||||
#define LINK_REG_D1FIFOSEL_CURPIPE_Msk (0xfUL) /* CURPIPE (Bitfield-Mask: 0x0f) */
|
||||
/* D1FIFOCTR */
|
||||
|
||||
// D1FIFOCTR
|
||||
#define LINK_REG_D1FIFOCTR_BVAL_Pos (15UL) /* BVAL (Bit 15) */
|
||||
#define LINK_REG_D1FIFOCTR_BVAL_Msk (0x8000UL) /* BVAL (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_D1FIFOCTR_BCLR_Pos (14UL) /* BCLR (Bit 14) */
|
||||
@ -1175,7 +1107,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_D1FIFOCTR_FRDY_Msk (0x2000UL) /* FRDY (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_D1FIFOCTR_DTLN_Pos (0UL) /* DTLN (Bit 0) */
|
||||
#define LINK_REG_D1FIFOCTR_DTLN_Msk (0xfffUL) /* DTLN (Bitfield-Mask: 0xfff) */
|
||||
/* INTENB0 */
|
||||
|
||||
// INTENB0
|
||||
#define LINK_REG_INTENB0_VBSE_Pos (15UL) /* VBSE (Bit 15) */
|
||||
#define LINK_REG_INTENB0_VBSE_Msk (0x8000UL) /* VBSE (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_INTENB0_RSME_Pos (14UL) /* RSME (Bit 14) */
|
||||
@ -1192,7 +1125,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_INTENB0_NRDYE_Msk (0x200UL) /* NRDYE (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_INTENB0_BRDYE_Pos (8UL) /* BRDYE (Bit 8) */
|
||||
#define LINK_REG_INTENB0_BRDYE_Msk (0x100UL) /* BRDYE (Bitfield-Mask: 0x01) */
|
||||
/* INTENB1 */
|
||||
|
||||
// INTENB1
|
||||
#define LINK_REG_INTENB1_OVRCRE_Pos (15UL) /* OVRCRE (Bit 15) */
|
||||
#define LINK_REG_INTENB1_OVRCRE_Msk (0x8000UL) /* OVRCRE (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_INTENB1_BCHGE_Pos (14UL) /* BCHGE (Bit 14) */
|
||||
@ -1209,16 +1143,20 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_INTENB1_SACKE_Msk (0x10UL) /* SACKE (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_INTENB1_PDDETINTE0_Pos (0UL) /* PDDETINTE0 (Bit 0) */
|
||||
#define LINK_REG_INTENB1_PDDETINTE0_Msk (0x1UL) /* PDDETINTE0 (Bitfield-Mask: 0x01) */
|
||||
/* BRDYENB */
|
||||
|
||||
// BRDYENB
|
||||
#define LINK_REG_BRDYENB_PIPEBRDYE_Pos (0UL) /* PIPEBRDYE (Bit 0) */
|
||||
#define LINK_REG_BRDYENB_PIPEBRDYE_Msk (0x1UL) /* PIPEBRDYE (Bitfield-Mask: 0x01) */
|
||||
/* NRDYENB */
|
||||
|
||||
// NRDYENB
|
||||
#define LINK_REG_NRDYENB_PIPENRDYE_Pos (0UL) /* PIPENRDYE (Bit 0) */
|
||||
#define LINK_REG_NRDYENB_PIPENRDYE_Msk (0x1UL) /* PIPENRDYE (Bitfield-Mask: 0x01) */
|
||||
/* BEMPENB */
|
||||
|
||||
// BEMPENB
|
||||
#define LINK_REG_BEMPENB_PIPEBEMPE_Pos (0UL) /* PIPEBEMPE (Bit 0) */
|
||||
#define LINK_REG_BEMPENB_PIPEBEMPE_Msk (0x1UL) /* PIPEBEMPE (Bitfield-Mask: 0x01) */
|
||||
/* SOFCFG */
|
||||
|
||||
// SOFCFG
|
||||
#define LINK_REG_SOFCFG_TRNENSEL_Pos (8UL) /* TRNENSEL (Bit 8) */
|
||||
#define LINK_REG_SOFCFG_TRNENSEL_Msk (0x100UL) /* TRNENSEL (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_SOFCFG_BRDYM_Pos (6UL) /* BRDYM (Bit 6) */
|
||||
@ -1227,7 +1165,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_SOFCFG_INTL_Msk (0x20UL) /* INTL (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_SOFCFG_EDGESTS_Pos (4UL) /* EDGESTS (Bit 4) */
|
||||
#define LINK_REG_SOFCFG_EDGESTS_Msk (0x10UL) /* EDGESTS (Bitfield-Mask: 0x01) */
|
||||
/* PHYSET */
|
||||
|
||||
// PHYSET
|
||||
#define LINK_REG_PHYSET_HSEB_Pos (15UL) /* HSEB (Bit 15) */
|
||||
#define LINK_REG_PHYSET_HSEB_Msk (0x8000UL) /* HSEB (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_PHYSET_REPSTART_Pos (11UL) /* REPSTART (Bit 11) */
|
||||
@ -1242,7 +1181,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_PHYSET_PLLRESET_Msk (0x2UL) /* PLLRESET (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_PHYSET_DIRPD_Pos (0UL) /* DIRPD (Bit 0) */
|
||||
#define LINK_REG_PHYSET_DIRPD_Msk (0x1UL) /* DIRPD (Bitfield-Mask: 0x01) */
|
||||
/* INTSTS0 */
|
||||
|
||||
// INTSTS0
|
||||
#define LINK_REG_INTSTS0_VBINT_Pos (15UL) /* VBINT (Bit 15) */
|
||||
#define LINK_REG_INTSTS0_VBINT_Msk (0x8000UL) /* VBINT (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_INTSTS0_RESM_Pos (14UL) /* RESM (Bit 14) */
|
||||
@ -1267,7 +1207,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_INTSTS0_VALID_Msk (0x8UL) /* VALID (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_INTSTS0_CTSQ_Pos (0UL) /* CTSQ (Bit 0) */
|
||||
#define LINK_REG_INTSTS0_CTSQ_Msk (0x7UL) /* CTSQ (Bitfield-Mask: 0x07) */
|
||||
/* INTSTS1 */
|
||||
|
||||
// INTSTS1
|
||||
#define LINK_REG_INTSTS1_OVRCR_Pos (15UL) /* OVRCR (Bit 15) */
|
||||
#define LINK_REG_INTSTS1_OVRCR_Msk (0x8000UL) /* OVRCR (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_INTSTS1_BCHG_Pos (14UL) /* BCHG (Bit 14) */
|
||||
@ -1288,59 +1229,72 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_INTSTS1_SACK_Msk (0x10UL) /* SACK (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_INTSTS1_PDDETINT0_Pos (0UL) /* PDDETINT0 (Bit 0) */
|
||||
#define LINK_REG_INTSTS1_PDDETINT0_Msk (0x1UL) /* PDDETINT0 (Bitfield-Mask: 0x01) */
|
||||
/* BRDYSTS */
|
||||
|
||||
// BRDYSTS
|
||||
#define LINK_REG_BRDYSTS_PIPEBRDY_Pos (0UL) /* PIPEBRDY (Bit 0) */
|
||||
#define LINK_REG_BRDYSTS_PIPEBRDY_Msk (0x1UL) /* PIPEBRDY (Bitfield-Mask: 0x01) */
|
||||
/* NRDYSTS */
|
||||
|
||||
// NRDYSTS
|
||||
#define LINK_REG_NRDYSTS_PIPENRDY_Pos (0UL) /* PIPENRDY (Bit 0) */
|
||||
#define LINK_REG_NRDYSTS_PIPENRDY_Msk (0x1UL) /* PIPENRDY (Bitfield-Mask: 0x01) */
|
||||
/* BEMPSTS */
|
||||
|
||||
// BEMPSTS
|
||||
#define LINK_REG_BEMPSTS_PIPEBEMP_Pos (0UL) /* PIPEBEMP (Bit 0) */
|
||||
#define LINK_REG_BEMPSTS_PIPEBEMP_Msk (0x1UL) /* PIPEBEMP (Bitfield-Mask: 0x01) */
|
||||
/* FRMNUM */
|
||||
|
||||
// FRMNUM
|
||||
#define LINK_REG_FRMNUM_OVRN_Pos (15UL) /* OVRN (Bit 15) */
|
||||
#define LINK_REG_FRMNUM_OVRN_Msk (0x8000UL) /* OVRN (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_FRMNUM_CRCE_Pos (14UL) /* CRCE (Bit 14) */
|
||||
#define LINK_REG_FRMNUM_CRCE_Msk (0x4000UL) /* CRCE (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_FRMNUM_FRNM_Pos (0UL) /* FRNM (Bit 0) */
|
||||
#define LINK_REG_FRMNUM_FRNM_Msk (0x7ffUL) /* FRNM (Bitfield-Mask: 0x7ff) */
|
||||
/* UFRMNUM */
|
||||
|
||||
// UFRMNUM
|
||||
#define LINK_REG_UFRMNUM_DVCHG_Pos (15UL) /* DVCHG (Bit 15) */
|
||||
#define LINK_REG_UFRMNUM_DVCHG_Msk (0x8000UL) /* DVCHG (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_UFRMNUM_UFRNM_Pos (0UL) /* UFRNM (Bit 0) */
|
||||
#define LINK_REG_UFRMNUM_UFRNM_Msk (0x7UL) /* UFRNM (Bitfield-Mask: 0x07) */
|
||||
/* USBADDR */
|
||||
|
||||
// USBADDR
|
||||
#define LINK_REG_USBADDR_STSRECOV0_Pos (8UL) /* STSRECOV0 (Bit 8) */
|
||||
#define LINK_REG_USBADDR_STSRECOV0_Msk (0x700UL) /* STSRECOV0 (Bitfield-Mask: 0x07) */
|
||||
#define LINK_REG_USBADDR_USBADDR_Pos (0UL) /* USBADDR (Bit 0) */
|
||||
#define LINK_REG_USBADDR_USBADDR_Msk (0x7fUL) /* USBADDR (Bitfield-Mask: 0x7f) */
|
||||
/* USBREQ */
|
||||
|
||||
// USBREQ
|
||||
#define LINK_REG_USBREQ_BREQUEST_Pos (8UL) /* BREQUEST (Bit 8) */
|
||||
#define LINK_REG_USBREQ_BREQUEST_Msk (0xff00UL) /* BREQUEST (Bitfield-Mask: 0xff) */
|
||||
#define LINK_REG_USBREQ_BMREQUESTTYPE_Pos (0UL) /* BMREQUESTTYPE (Bit 0) */
|
||||
#define LINK_REG_USBREQ_BMREQUESTTYPE_Msk (0xffUL) /* BMREQUESTTYPE (Bitfield-Mask: 0xff) */
|
||||
/* USBVAL */
|
||||
|
||||
// USBVAL
|
||||
#define LINK_REG_USBVAL_WVALUE_Pos (0UL) /* WVALUE (Bit 0) */
|
||||
#define LINK_REG_USBVAL_WVALUE_Msk (0xffffUL) /* WVALUE (Bitfield-Mask: 0xffff) */
|
||||
/* USBINDX */
|
||||
|
||||
// USBINDX
|
||||
#define LINK_REG_USBINDX_WINDEX_Pos (0UL) /* WINDEX (Bit 0) */
|
||||
#define LINK_REG_USBINDX_WINDEX_Msk (0xffffUL) /* WINDEX (Bitfield-Mask: 0xffff) */
|
||||
/* USBLENG */
|
||||
|
||||
// USBLENG
|
||||
#define LINK_REG_USBLENG_WLENGTH_Pos (0UL) /* WLENGTH (Bit 0) */
|
||||
#define LINK_REG_USBLENG_WLENGTH_Msk (0xffffUL) /* WLENGTH (Bitfield-Mask: 0xffff) */
|
||||
/* DCPCFG */
|
||||
|
||||
// DCPCFG
|
||||
#define LINK_REG_DCPCFG_CNTMD_Pos (8UL) /* CNTMD (Bit 8) */
|
||||
#define LINK_REG_DCPCFG_CNTMD_Msk (0x100UL) /* CNTMD (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DCPCFG_SHTNAK_Pos (7UL) /* SHTNAK (Bit 7) */
|
||||
#define LINK_REG_DCPCFG_SHTNAK_Msk (0x80UL) /* SHTNAK (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DCPCFG_DIR_Pos (4UL) /* DIR (Bit 4) */
|
||||
#define LINK_REG_DCPCFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */
|
||||
/* DCPMAXP */
|
||||
|
||||
// DCPMAXP
|
||||
#define LINK_REG_DCPMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */
|
||||
#define LINK_REG_DCPMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */
|
||||
#define LINK_REG_DCPMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */
|
||||
#define LINK_REG_DCPMAXP_MXPS_Msk (0x7fUL) /* MXPS (Bitfield-Mask: 0x7f) */
|
||||
/* DCPCTR */
|
||||
|
||||
// DCPCTR
|
||||
#define LINK_REG_DCPCTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */
|
||||
#define LINK_REG_DCPCTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DCPCTR_SUREQ_Pos (14UL) /* SUREQ (Bit 14) */
|
||||
@ -1359,10 +1313,12 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_DCPCTR_CCPL_Msk (0x4UL) /* CCPL (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DCPCTR_PID_Pos (0UL) /* PID (Bit 0) */
|
||||
#define LINK_REG_DCPCTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */
|
||||
/* PIPESEL */
|
||||
|
||||
// PIPESEL
|
||||
#define LINK_REG_PIPESEL_PIPESEL_Pos (0UL) /* PIPESEL (Bit 0) */
|
||||
#define LINK_REG_PIPESEL_PIPESEL_Msk (0xfUL) /* PIPESEL (Bitfield-Mask: 0x0f) */
|
||||
/* PIPECFG */
|
||||
|
||||
// PIPECFG
|
||||
#define LINK_REG_PIPECFG_TYPE_Pos (14UL) /* TYPE (Bit 14) */
|
||||
#define LINK_REG_PIPECFG_TYPE_Msk (0xc000UL) /* TYPE (Bitfield-Mask: 0x03) */
|
||||
#define LINK_REG_PIPECFG_BFRE_Pos (10UL) /* BFRE (Bit 10) */
|
||||
@ -1375,17 +1331,20 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_PIPECFG_DIR_Msk (0x10UL) /* DIR (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_PIPECFG_EPNUM_Pos (0UL) /* EPNUM (Bit 0) */
|
||||
#define LINK_REG_PIPECFG_EPNUM_Msk (0xfUL) /* EPNUM (Bitfield-Mask: 0x0f) */
|
||||
/* PIPEMAXP */
|
||||
|
||||
// PIPEMAXP
|
||||
#define LINK_REG_PIPEMAXP_DEVSEL_Pos (12UL) /* DEVSEL (Bit 12) */
|
||||
#define LINK_REG_PIPEMAXP_DEVSEL_Msk (0xf000UL) /* DEVSEL (Bitfield-Mask: 0x0f) */
|
||||
#define LINK_REG_PIPEMAXP_MXPS_Pos (0UL) /* MXPS (Bit 0) */
|
||||
#define LINK_REG_PIPEMAXP_MXPS_Msk (0x1ffUL) /* MXPS (Bitfield-Mask: 0x1ff) */
|
||||
/* PIPEPERI */
|
||||
|
||||
// PIPEPERI
|
||||
#define LINK_REG_PIPEPERI_IFIS_Pos (12UL) /* IFIS (Bit 12) */
|
||||
#define LINK_REG_PIPEPERI_IFIS_Msk (0x1000UL) /* IFIS (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_PIPEPERI_IITV_Pos (0UL) /* IITV (Bit 0) */
|
||||
#define LINK_REG_PIPEPERI_IITV_Msk (0x7UL) /* IITV (Bitfield-Mask: 0x07) */
|
||||
/* PIPE_CTR */
|
||||
|
||||
// PIPE_CTR
|
||||
#define LINK_REG_PIPE_CTR_BSTS_Pos (15UL) /* BSTS (Bit 15) */
|
||||
#define LINK_REG_PIPE_CTR_BSTS_Msk (0x8000UL) /* BSTS (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_PIPE_CTR_INBUFM_Pos (14UL) /* INBUFM (Bit 14) */
|
||||
@ -1408,14 +1367,16 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_PIPE_CTR_PBUSY_Msk (0x20UL) /* PBUSY (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_PIPE_CTR_PID_Pos (0UL) /* PID (Bit 0) */
|
||||
#define LINK_REG_PIPE_CTR_PID_Msk (0x3UL) /* PID (Bitfield-Mask: 0x03) */
|
||||
/* DEVADD */
|
||||
|
||||
// DEVADD
|
||||
#define LINK_REG_DEVADD_UPPHUB_Pos (11UL) /* UPPHUB (Bit 11) */
|
||||
#define LINK_REG_DEVADD_UPPHUB_Msk (0x7800UL) /* UPPHUB (Bitfield-Mask: 0x0f) */
|
||||
#define LINK_REG_DEVADD_HUBPORT_Pos (8UL) /* HUBPORT (Bit 8) */
|
||||
#define LINK_REG_DEVADD_HUBPORT_Msk (0x700UL) /* HUBPORT (Bitfield-Mask: 0x07) */
|
||||
#define LINK_REG_DEVADD_USBSPD_Pos (6UL) /* USBSPD (Bit 6) */
|
||||
#define LINK_REG_DEVADD_USBSPD_Msk (0xc0UL) /* USBSPD (Bitfield-Mask: 0x03) */
|
||||
/* USBBCCTRL0 */
|
||||
|
||||
// USBBCCTRL0
|
||||
#define LINK_REG_USBBCCTRL0_PDDETSTS0_Pos (9UL) /* PDDETSTS0 (Bit 9) */
|
||||
#define LINK_REG_USBBCCTRL0_PDDETSTS0_Msk (0x200UL) /* PDDETSTS0 (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_USBBCCTRL0_CHGDETSTS0_Pos (8UL) /* CHGDETSTS0 (Bit 8) */
|
||||
@ -1434,15 +1395,18 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_USBBCCTRL0_IDPSRCE0_Msk (0x2UL) /* IDPSRCE0 (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_USBBCCTRL0_RPDME0_Pos (0UL) /* RPDME0 (Bit 0) */
|
||||
#define LINK_REG_USBBCCTRL0_RPDME0_Msk (0x1UL) /* RPDME0 (Bitfield-Mask: 0x01) */
|
||||
/* UCKSEL */
|
||||
|
||||
// UCKSEL
|
||||
#define LINK_REG_UCKSEL_UCKSELC_Pos (0UL) /* UCKSELC (Bit 0) */
|
||||
#define LINK_REG_UCKSEL_UCKSELC_Msk (0x1UL) /* UCKSELC (Bitfield-Mask: 0x01) */
|
||||
/* USBMC */
|
||||
|
||||
// USBMC
|
||||
#define LINK_REG_USBMC_VDCEN_Pos (7UL) /* VDCEN (Bit 7) */
|
||||
#define LINK_REG_USBMC_VDCEN_Msk (0x80UL) /* VDCEN (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_USBMC_VDDUSBE_Pos (0UL) /* VDDUSBE (Bit 0) */
|
||||
#define LINK_REG_USBMC_VDDUSBE_Msk (0x1UL) /* VDDUSBE (Bitfield-Mask: 0x01) */
|
||||
/* PHYSLEW */
|
||||
|
||||
// PHYSLEW
|
||||
#define LINK_REG_PHYSLEW_SLEWF01_Pos (3UL) /* SLEWF01 (Bit 3) */
|
||||
#define LINK_REG_PHYSLEW_SLEWF01_Msk (0x8UL) /* SLEWF01 (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_PHYSLEW_SLEWF00_Pos (2UL) /* SLEWF00 (Bit 2) */
|
||||
@ -1451,13 +1415,16 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_PHYSLEW_SLEWR01_Msk (0x2UL) /* SLEWR01 (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_PHYSLEW_SLEWR00_Pos (0UL) /* SLEWR00 (Bit 0) */
|
||||
#define LINK_REG_PHYSLEW_SLEWR00_Msk (0x1UL) /* SLEWR00 (Bitfield-Mask: 0x01) */
|
||||
/* LPCTRL */
|
||||
|
||||
// LPCTRL
|
||||
#define LINK_REG_LPCTRL_HWUPM_Pos (7UL) /* HWUPM (Bit 7) */
|
||||
#define LINK_REG_LPCTRL_HWUPM_Msk (0x80UL) /* HWUPM (Bitfield-Mask: 0x01) */
|
||||
/* LPSTS */
|
||||
|
||||
// LPSTS
|
||||
#define LINK_REG_LPSTS_SUSPENDM_Pos (14UL) /* SUSPENDM (Bit 14) */
|
||||
#define LINK_REG_LPSTS_SUSPENDM_Msk (0x4000UL) /* SUSPENDM (Bitfield-Mask: 0x01) */
|
||||
/* BCCTRL */
|
||||
|
||||
// BCCTRL
|
||||
#define LINK_REG_BCCTRL_PDDETSTS_Pos (9UL) /* PDDETSTS (Bit 9) */
|
||||
#define LINK_REG_BCCTRL_PDDETSTS_Msk (0x200UL) /* PDDETSTS (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_BCCTRL_CHGDETSTS_Pos (8UL) /* CHGDETSTS (Bit 8) */
|
||||
@ -1474,7 +1441,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_BCCTRL_IDMSINKE_Msk (0x2UL) /* IDMSINKE (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_BCCTRL_IDPSRCE_Pos (0UL) /* IDPSRCE (Bit 0) */
|
||||
#define LINK_REG_BCCTRL_IDPSRCE_Msk (0x1UL) /* IDPSRCE (Bitfield-Mask: 0x01) */
|
||||
/* PL1CTRL1 */
|
||||
|
||||
// PL1CTRL1
|
||||
#define LINK_REG_PL1CTRL1_L1EXTMD_Pos (14UL) /* L1EXTMD (Bit 14) */
|
||||
#define LINK_REG_PL1CTRL1_L1EXTMD_Msk (0x4000UL) /* L1EXTMD (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_PL1CTRL1_HIRDTHR_Pos (8UL) /* HIRDTHR (Bit 8) */
|
||||
@ -1487,17 +1455,20 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_PL1CTRL1_L1RESPMD_Msk (0x6UL) /* L1RESPMD (Bitfield-Mask: 0x03) */
|
||||
#define LINK_REG_PL1CTRL1_L1RESPEN_Pos (0UL) /* L1RESPEN (Bit 0) */
|
||||
#define LINK_REG_PL1CTRL1_L1RESPEN_Msk (0x1UL) /* L1RESPEN (Bitfield-Mask: 0x01) */
|
||||
/* PL1CTRL2 */
|
||||
|
||||
// PL1CTRL2
|
||||
#define LINK_REG_PL1CTRL2_RWEMON_Pos (12UL) /* RWEMON (Bit 12) */
|
||||
#define LINK_REG_PL1CTRL2_RWEMON_Msk (0x1000UL) /* RWEMON (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_PL1CTRL2_HIRDMON_Pos (8UL) /* HIRDMON (Bit 8) */
|
||||
#define LINK_REG_PL1CTRL2_HIRDMON_Msk (0xf00UL) /* HIRDMON (Bitfield-Mask: 0x0f) */
|
||||
/* HL1CTRL1 */
|
||||
|
||||
// HL1CTRL1
|
||||
#define LINK_REG_HL1CTRL1_L1STATUS_Pos (1UL) /* L1STATUS (Bit 1) */
|
||||
#define LINK_REG_HL1CTRL1_L1STATUS_Msk (0x6UL) /* L1STATUS (Bitfield-Mask: 0x03) */
|
||||
#define LINK_REG_HL1CTRL1_L1REQ_Pos (0UL) /* L1REQ (Bit 0) */
|
||||
#define LINK_REG_HL1CTRL1_L1REQ_Msk (0x1UL) /* L1REQ (Bitfield-Mask: 0x01) */
|
||||
/* HL1CTRL2 */
|
||||
|
||||
// HL1CTRL2
|
||||
#define LINK_REG_HL1CTRL2_BESL_Pos (15UL) /* BESL (Bit 15) */
|
||||
#define LINK_REG_HL1CTRL2_BESL_Msk (0x8000UL) /* BESL (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_HL1CTRL2_L1RWE_Pos (12UL) /* L1RWE (Bit 12) */
|
||||
@ -1506,14 +1477,16 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_HL1CTRL2_HIRD_Msk (0xf00UL) /* HIRD (Bitfield-Mask: 0x0f) */
|
||||
#define LINK_REG_HL1CTRL2_L1ADDR_Pos (0UL) /* L1ADDR (Bit 0) */
|
||||
#define LINK_REG_HL1CTRL2_L1ADDR_Msk (0xfUL) /* L1ADDR (Bitfield-Mask: 0x0f) */
|
||||
/* DPUSR0R */
|
||||
|
||||
// DPUSR0R
|
||||
#define LINK_REG_DPUSR0R_DVBSTSHM_Pos (23UL) /* DVBSTSHM (Bit 23) */
|
||||
#define LINK_REG_DPUSR0R_DVBSTSHM_Msk (0x800000UL) /* DVBSTSHM (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DPUSR0R_DOVCBHM_Pos (21UL) /* DOVCBHM (Bit 21) */
|
||||
#define LINK_REG_DPUSR0R_DOVCBHM_Msk (0x200000UL) /* DOVCBHM (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DPUSR0R_DOVCAHM_Pos (20UL) /* DOVCAHM (Bit 20) */
|
||||
#define LINK_REG_DPUSR0R_DOVCAHM_Msk (0x100000UL) /* DOVCAHM (Bitfield-Mask: 0x01) */
|
||||
/* DPUSR1R */
|
||||
|
||||
// DPUSR1R
|
||||
#define LINK_REG_DPUSR1R_DVBSTSH_Pos (23UL) /* DVBSTSH (Bit 23) */
|
||||
#define LINK_REG_DPUSR1R_DVBSTSH_Msk (0x800000UL) /* DVBSTSH (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DPUSR1R_DOVCBH_Pos (21UL) /* DOVCBH (Bit 21) */
|
||||
@ -1526,7 +1499,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_DPUSR1R_DOVCBHE_Msk (0x20UL) /* DOVCBHE (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DPUSR1R_DOVCAHE_Pos (4UL) /* DOVCAHE (Bit 4) */
|
||||
#define LINK_REG_DPUSR1R_DOVCAHE_Msk (0x10UL) /* DOVCAHE (Bitfield-Mask: 0x01) */
|
||||
/* DPUSR2R */
|
||||
|
||||
// DPUSR2R
|
||||
#define LINK_REG_DPUSR2R_DMINTE_Pos (9UL) /* DMINTE (Bit 9) */
|
||||
#define LINK_REG_DPUSR2R_DMINTE_Msk (0x200UL) /* DMINTE (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DPUSR2R_DPINTE_Pos (8UL) /* DPINTE (Bit 8) */
|
||||
@ -1539,12 +1513,14 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_DPUSR2R_DMINT_Msk (0x2UL) /* DMINT (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DPUSR2R_DPINT_Pos (0UL) /* DPINT (Bit 0) */
|
||||
#define LINK_REG_DPUSR2R_DPINT_Msk (0x1UL) /* DPINT (Bitfield-Mask: 0x01) */
|
||||
/* DPUSRCR */
|
||||
|
||||
// DPUSRCR
|
||||
#define LINK_REG_DPUSRCR_FIXPHYPD_Pos (1UL) /* FIXPHYPD (Bit 1) */
|
||||
#define LINK_REG_DPUSRCR_FIXPHYPD_Msk (0x2UL) /* FIXPHYPD (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DPUSRCR_FIXPHY_Pos (0UL) /* FIXPHY (Bit 0) */
|
||||
#define LINK_REG_DPUSRCR_FIXPHY_Msk (0x1UL) /* FIXPHY (Bitfield-Mask: 0x01) */
|
||||
/* DPUSR0R_FS */
|
||||
|
||||
// DPUSR0R_FS
|
||||
#define LINK_REG_DPUSR0R_FS_DVBSTS0_Pos (23UL) /* DVBSTS0 (Bit 23) */
|
||||
#define LINK_REG_DPUSR0R_FS_DVBSTS0_Msk (0x800000UL) /* DVBSTS0 (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DPUSR0R_FS_DOVCB0_Pos (21UL) /* DOVCB0 (Bit 21) */
|
||||
@ -1563,7 +1539,8 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_DPUSR0R_FS_RPUE0_Msk (0x2UL) /* RPUE0 (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DPUSR0R_FS_SRPC0_Pos (0UL) /* SRPC0 (Bit 0) */
|
||||
#define LINK_REG_DPUSR0R_FS_SRPC0_Msk (0x1UL) /* SRPC0 (Bitfield-Mask: 0x01) */
|
||||
/* DPUSR1R_FS */
|
||||
|
||||
// DPUSR1R_FS
|
||||
#define LINK_REG_DPUSR1R_FS_DVBINT0_Pos (23UL) /* DVBINT0 (Bit 23) */
|
||||
#define LINK_REG_DPUSR1R_FS_DVBINT0_Msk (0x800000UL) /* DVBINT0 (Bitfield-Mask: 0x01) */
|
||||
#define LINK_REG_DPUSR1R_FS_DOVRCRB0_Pos (21UL) /* DOVRCRB0 (Bit 21) */
|
||||
@ -1617,6 +1594,74 @@ TU_ATTR_BIT_FIELD_ORDER_END
|
||||
#define LINK_REG_PIPECFG_TYPE_INT (2U << LINK_REG_PIPECFG_TYPE_Pos)
|
||||
#define LINK_REG_PIPECFG_TYPE_ISO (3U << LINK_REG_PIPECFG_TYPE_Pos)
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Static Assert
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
TU_VERIFY_STATIC(sizeof(LINK_REG_PIPE_TR_t) == 4, "incorrect size");
|
||||
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSCFG ) == 0x00000000, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, BUSWAIT ) == 0x00000002, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, SYSSTS0 ) == 0x00000004, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, PLLSTA ) == 0x00000006, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, DVSTCTR0 ) == 0x00000008, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, TESTMODE ) == 0x0000000C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFO ) == 0x00000014, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFO ) == 0x00000018, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFO ) == 0x0000001C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOSEL ) == 0x00000020, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, CFIFOCTR ) == 0x00000022, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOSEL ) == 0x00000028, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, D0FIFOCTR ) == 0x0000002A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOSEL ) == 0x0000002C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, D1FIFOCTR ) == 0x0000002E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB0 ) == 0x00000030, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTENB1 ) == 0x00000032, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYENB ) == 0x00000036, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYENB ) == 0x00000038, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPENB ) == 0x0000003A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, SOFCFG ) == 0x0000003C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSET ) == 0x0000003E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS0 ) == 0x00000040, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, INTSTS1 ) == 0x00000042, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, BRDYSTS ) == 0x00000046, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, NRDYSTS ) == 0x00000048, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, BEMPSTS ) == 0x0000004A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, FRMNUM ) == 0x0000004C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, UFRMNUM ) == 0x0000004E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBADDR ) == 0x00000050, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBREQ ) == 0x00000054, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBVAL ) == 0x00000056, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBINDX ) == 0x00000058, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBLENG ) == 0x0000005A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCFG ) == 0x0000005C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPMAXP ) == 0x0000005E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, DCPCTR ) == 0x00000060, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPESEL ) == 0x00000064, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPECFG ) == 0x00000068, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEMAXP ) == 0x0000006C, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPEPERI ) == 0x0000006E, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_CTR ) == 0x00000070, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, PIPE_TR ) == 0x00000090, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBBCCTRL0 ) == 0x000000B0, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, UCKSEL ) == 0x000000C4, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, USBMC ) == 0x000000CC, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, DEVADD ) == 0x000000D0, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, PHYSLEW ) == 0x000000F0, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPCTRL ) == 0x00000100, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, LPSTS ) == 0x00000102, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, BCCTRL ) == 0x00000140, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL1 ) == 0x00000144, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, PL1CTRL2 ) == 0x00000146, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL1 ) == 0x00000148, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, HL1CTRL2 ) == 0x0000014A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R ) == 0x00000160, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R ) == 0x00000164, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR2R ) == 0x00000168, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSRCR ) == 0x0000016A, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR0R_FS ) == 0x00000400, "incorrect offset");
|
||||
TU_VERIFY_STATIC(offsetof(LINK_REG_t, DPUSR1R_FS ) == 0x00000404, "incorrect offset");
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user