change default risv-gcc to riscv-none-elf- and add _zicsr extension

add cmake for ch32v20x, skip freertos examples for CH32V20X, also skip net webserver due to lack of RAM update to use openocd with wlinke adapter
2025-02-05 18:40:28 +00:00 · 2024-05-15 20:13:00 +07:00 · 2024-05-15 20:13:00 +07:00 · 2a67ce773d
commit 2a67ce773d
parent db60fa1c63
22 changed files with 191 additions and 50 deletions
--- a/.github/workflows/ci_set_matrix.py
+++ b/.github/workflows/ci_set_matrix.py
@ -7,14 +7,14 @@ toolchain_list = {
    "arm-iar": "",
    "arm-gcc": "",
    "msp430-gcc": "http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2",
-    "riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack/releases/download/v10.1.0-1.1/xpack-riscv-none-embed-gcc-10.1.0-1.1-linux-x64.tar.gz",
+    "riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz"
 }

 # family: [supported toolchain]
 family_list = {
    "broadcom_32bit": ["arm-gcc"],
    "broadcom_64bit": ["aarch64-gcc"],
-    "ch32v307 fomu gd32vf103": ["riscv-gcc"],
+    "ch32v20x ch32v307 fomu gd32vf103": ["riscv-gcc"],
    "imxrt": ["arm-gcc", "arm-clang"],
    "kinetis_k kinetis_kl kinetis_k32l2": ["arm-gcc", "arm-clang"],
    "lpc11 lpc13 lpc15": ["arm-gcc", "arm-clang"],
--- a/.idea/cmake.xml
+++ b/.idea/cmake.xml
@ -66,6 +66,7 @@
      <configuration PROFILE_NAME="metro_m0_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m0_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
      <configuration PROFILE_NAME="feather_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
      <configuration PROFILE_NAME="metro_m4_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=metro_m4_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
+      <configuration PROFILE_NAME="itsybitsy_m4" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=itsybitsy_m4 -DLOG=3 -DLOGGER=RTT" />
      <configuration PROFILE_NAME="same54_xplained" ENABLED="false" GENERATION_OPTIONS="-DBOARD=same54_xplained -DLOG=2 -DLOGGER=RTT" />
      <configuration PROFILE_NAME="feather_nrf52840_express" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=feather_nrf52840_express -DLOG=3 -DLOGGER=RTT -DMAX3421_HOST=1" />
      <configuration PROFILE_NAME="pca10056" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=pca10056 -DLOG=3 -DLOGGER=RTT -DTRACE_ETM=1" />
@ -103,6 +104,7 @@
      <configuration PROFILE_NAME="stm32l476disco" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32l476disco" />
      <configuration PROFILE_NAME="stm32u575nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u575nucleo -DLOG=2 -DLOGGER=RTT" />
      <configuration PROFILE_NAME="stm32u5a5nucleo" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=stm32u5a5nucleo -DLOG=3 -DLOGGER=RTT" />
+      <configuration PROFILE_NAME="stm32wb55nucleo" ENABLED="false" GENERATION_OPTIONS="-DBOARD=stm32wb55nucleo" />
      <configuration PROFILE_NAME="ra2a1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra2a1_ek -DLOG=3 -DLOGGER=RTT" />
      <configuration PROFILE_NAME="ra4m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra4m1_ek -DLOG=3 -DLOGGER=RTT" />
      <configuration PROFILE_NAME="ra6m1" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=ra6m1_ek -DLOG=3 -DLOGGER=RTT" />
@ -120,7 +122,6 @@
      <configuration PROFILE_NAME="lpcxpresso51u68" ENABLED="false" CONFIG_NAME="Debug" TOOLCHAIN_NAME="armclang 17.0.1" GENERATION_OPTIONS="-DBOARD=lpcxpresso51u68 -DLOG=2 -DLOGGER=RTT" />
      <configuration PROFILE_NAME="msp_exp432e401y" ENABLED="false" CONFIG_NAME="Debug" GENERATION_OPTIONS="-DBOARD=msp_exp432e401y -DLOG=2" />
      <configuration PROFILE_NAME="atsaml21_xpro" ENABLED="false" GENERATION_OPTIONS="-DBOARD=atsaml21_xpro" />
-      <configuration PROFILE_NAME="stm32wb55nucleo" ENABLED="false" GENERATION_OPTIONS="-DBOARD=stm32wb55nucleo" />
      <configuration PROFILE_NAME="samd11_xplained" ENABLED="false" CONFIG_NAME="MinSizeRel" GENERATION_OPTIONS="-DBOARD=samd11_xplained" />
      <configuration PROFILE_NAME="ek_tm4c123gxl" ENABLED="false" CONFIG_NAME="MinSizeRel" GENERATION_OPTIONS="-DBOARD=ek_tm4c123gxl" />
      <configuration PROFILE_NAME="xmc4500_relax" ENABLED="false" GENERATION_OPTIONS="-DBOARD=xmc4500_relax -DLOG=2 -DLOGGER=RTT" />
@ -130,6 +131,7 @@
      <configuration PROFILE_NAME="ch32v307v_r1_1v0" ENABLED="false" GENERATION_OPTIONS="-DBOARD=ch32v307v_r1_1v0" />
      <configuration PROFILE_NAME="fomu" ENABLED="false" GENERATION_OPTIONS="-DBOARD=fomu" />
      <configuration PROFILE_NAME="sipeed_longan_nano" ENABLED="false" GENERATION_OPTIONS="-DBOARD=sipeed_longan_nano" />
+      <configuration PROFILE_NAME="nanoch32v203" ENABLED="false" GENERATION_OPTIONS="-DBOARD=nanoch32v203" />
    </configurations>
  </component>
 </project>
--- a/examples/build_system/cmake/cpu/rv32i-ilp32.cmake
+++ b/examples/build_system/cmake/cpu/rv32i-ilp32.cmake
@ -1,13 +1,13 @@
 if (TOOLCHAIN STREQUAL "gcc")
  set(TOOLCHAIN_COMMON_FLAGS
-    -march=rv32i
+    -march=rv32i_zicsr
    -mabi=ilp32
    )
  set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")

 elseif (TOOLCHAIN STREQUAL "clang")
  set(TOOLCHAIN_COMMON_FLAGS
-    -march=rv32i
+    -march=rv32i_zicsr
    -mabi=ilp32
    )
  set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
--- a/examples/build_system/cmake/cpu/rv32imac-ilp32.cmake
+++ b/examples/build_system/cmake/cpu/rv32imac-ilp32.cmake
@ -1,13 +1,13 @@
 if (TOOLCHAIN STREQUAL "gcc")
  set(TOOLCHAIN_COMMON_FLAGS
-    -march=rv32imac
+    -march=rv32imac_zicsr
    -mabi=ilp32
    )
  set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")

 elseif (TOOLCHAIN STREQUAL "clang")
  set(TOOLCHAIN_COMMON_FLAGS
-    -march=rv32imac
+    -march=rv32imac_zicsr
    -mabi=ilp32
    )
  set(FREERTOS_PORT GCC_RISC_V CACHE INTERNAL "")
--- a/examples/build_system/cmake/toolchain/riscv_gcc.cmake
+++ b/examples/build_system/cmake/toolchain/riscv_gcc.cmake
@ -1,15 +1,24 @@
+# default Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
+if (NOT DEFINED CROSS_COMPILE)
+  set(CROSS_COMPILE "riscv-none-elf-")
+endif ()
+
 if (NOT DEFINED CMAKE_C_COMPILER)
-  set(CMAKE_C_COMPILER "riscv-none-embed-gcc")
+  set(CMAKE_C_COMPILER ${CROSS_COMPILE}gcc)
+endif ()
+
+if (NOT DEFINED CMAKE_C_COMPILER)
+  set(CMAKE_C_COMPILER ${CROSS_COMPILE}gcc)
 endif ()

 if (NOT DEFINED CMAKE_CXX_COMPILER)
-  set(CMAKE_CXX_COMPILER "riscv-none-embed-g++")
+  set(CMAKE_CXX_COMPILER ${CROSS_COMPILE}g++)
 endif ()

 set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER})
-set(CMAKE_SIZE "riscv-none-embed-size" CACHE FILEPATH "")
-set(CMAKE_OBJCOPY "riscv-none-embed-objcopy" CACHE FILEPATH "")
-set(CMAKE_OBJDUMP "riscv-none-embed-objdump" CACHE FILEPATH "")
+set(CMAKE_SIZE ${CROSS_COMPILE}size CACHE FILEPATH "")
+set(CMAKE_OBJCOPY ${CROSS_COMPILE}objcopy CACHE FILEPATH "")
+set(CMAKE_OBJDUMP ${CROSS_COMPILE}objdump CACHE FILEPATH "")

 include(${CMAKE_CURRENT_LIST_DIR}/common.cmake)

--- a/examples/build_system/make/cpu/rv32i-ilp32.mk
+++ b/examples/build_system/make/cpu/rv32i-ilp32.mk
@ -1,12 +1,15 @@
 ifeq ($(TOOLCHAIN),gcc)
  CFLAGS += \
-    -march=rv32i \
+    -march=rv32i_zicsr \
+    -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+    -march=rv32i_zicsr \
    -mabi=ilp32 \

 else ifeq ($(TOOLCHAIN),iar)
-	#CFLAGS += --cpu cortex-a53
-	#ASFLAGS += --cpu cortex-a53
-
+  $(error not support)
 endif

 # For freeRTOS port source
--- a/examples/build_system/make/cpu/rv32imac-ilp32.mk
+++ b/examples/build_system/make/cpu/rv32imac-ilp32.mk
@ -1,11 +1,15 @@
 ifeq ($(TOOLCHAIN),gcc)
  CFLAGS += \
-    -march=rv32imac \
+    -march=rv32imac_zicsr \
+    -mabi=ilp32 \
+
+else ifeq ($(TOOLCHAIN),clang)
+  CFLAGS += \
+    -march=rv32imac_zicsr \
    -mabi=ilp32 \

 else ifeq ($(TOOLCHAIN),iar)
-	#CFLAGS += --cpu cortex-a53
-	#ASFLAGS += --cpu cortex-a53
+  $(error not support)

 endif

--- a/examples/device/audio_4_channel_mic_freertos/skip.txt
+++ b/examples/device/audio_4_channel_mic_freertos/skip.txt
@ -1,3 +1,4 @@
+mcu:CH32V20X
 mcu:CH32V307
 mcu:CXD56
 mcu:F1C100S
--- a/examples/device/audio_test_freertos/skip.txt
+++ b/examples/device/audio_test_freertos/skip.txt
@ -1,3 +1,4 @@
+mcu:CH32V20X
 mcu:CH32V307
 mcu:CXD56
 mcu:F1C100S
--- a/examples/device/net_lwip_webserver/skip.txt
+++ b/examples/device/net_lwip_webserver/skip.txt
@ -1,3 +1,4 @@
+mcu:CH32V20X
 mcu:LPC11UXX
 mcu:LPC13XX
 mcu:LPC15XX
--- a/examples/device/video_capture_2ch/skip.txt
+++ b/examples/device/video_capture_2ch/skip.txt
@ -2,6 +2,7 @@ mcu:MSP430x5xx
 mcu:NUC121
 mcu:SAMD11
 mcu:GD32VF103
+mcu:CH32V20X
 mcu:CH32V307
 mcu:STM32L0
 family:espressif
--- a/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
+++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.cmake
@ -0,0 +1,7 @@
+set(MCU_VARIANT D6)
+
+function(update_board TARGET)
+  target_compile_definitions(${TARGET} PUBLIC
+    CH32V20x_D6
+    )
+endfunction()
--- a/hw/bsp/ch32v20x/family.cmake
+++ b/hw/bsp/ch32v20x/family.cmake
@ -0,0 +1,109 @@
+include_guard()
+
+set(CH32_FAMILY ch32v20x)
+set(SDK_DIR ${TOP}/hw/mcu/wch/${CH32_FAMILY}/EVT/EXAM/SRC)
+
+# include board specific
+include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake)
+
+# toolchain set up
+set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor")
+set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake)
+
+set(FAMILY_MCUS CH32V20X CACHE INTERNAL "")
+set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
+
+#------------------------------------
+# BOARD_TARGET
+#------------------------------------
+# only need to be built ONCE for all examples
+function(add_board_target BOARD_TARGET)
+  if (TARGET ${BOARD_TARGET})
+    return()
+  endif()
+
+  if (NOT DEFINED LD_FILE_GNU)
+    set(LD_FILE_GNU ${SDK_DIR}/Ld/Link.ld)
+  endif ()
+  set(LD_FILE_Clang ${LD_FILE_GNU})
+
+  if (NOT DEFINED STARTUP_FILE_GNU)
+    set(STARTUP_FILE_GNU ${SDK_DIR}/Startup/startup_${CH32_FAMILY}_${MCU_VARIANT}.S)
+  endif ()
+  set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU})
+
+  add_library(${BOARD_TARGET} STATIC
+    ${SDK_DIR}/Core/core_riscv.c
+    ${SDK_DIR}/Peripheral/src/${CH32_FAMILY}_gpio.c
+    ${SDK_DIR}/Peripheral/src/${CH32_FAMILY}_misc.c
+    ${SDK_DIR}/Peripheral/src/${CH32_FAMILY}_rcc.c
+    ${SDK_DIR}/Peripheral/src/${CH32_FAMILY}_usart.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/system_${CH32_FAMILY}.c
+    ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}}
+    )
+  target_include_directories(${BOARD_TARGET} PUBLIC
+    ${SDK_DIR}/Peripheral/inc
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    )
+  target_compile_definitions(${BOARD_TARGET} PUBLIC
+    BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED
+    )
+
+  update_board(${BOARD_TARGET})
+
+  if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    target_compile_options(${BOARD_TARGET} PUBLIC
+      -mcmodel=medany
+      )
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--script=${LD_FILE_GNU}"
+      -nostartfiles
+      --specs=nosys.specs --specs=nano.specs
+      )
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang")
+    message(FATAL_ERROR "Clang is not supported for MSP432E4")
+  elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR")
+    target_link_options(${BOARD_TARGET} PUBLIC
+      "LINKER:--config=${LD_FILE_IAR}"
+      )
+  endif ()
+endfunction()
+
+
+#------------------------------------
+# Functions
+#------------------------------------
+function(family_configure_example TARGET RTOS)
+  family_configure_common(${TARGET} ${RTOS})
+
+  # Board target
+  add_board_target(board_${BOARD})
+
+  #---------- Port Specific ----------
+  # These files are built for each example since it depends on example's tusb_config.h
+  target_sources(${TARGET} PUBLIC
+    # BSP
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c
+    )
+  target_include_directories(${TARGET} PUBLIC
+    # family, hw, board
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../
+    ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}
+    )
+
+  # Add TinyUSB target and port source
+  family_add_tinyusb(${TARGET} OPT_MCU_CH32V20X ${RTOS})
+  target_sources(${TARGET}-tinyusb PUBLIC
+    ${TOP}/src/portable/wch/dcd_ch32_usbfs.c
+    )
+  target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
+
+  # Link dependencies
+  target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb)
+
+  # Flashing
+  family_add_bin_hex(${TARGET})
+  family_flash_openocd_wch(${TARGET})
+endfunction()
--- a/hw/bsp/ch32v20x/family.mk
+++ b/hw/bsp/ch32v20x/family.mk
@ -1,3 +1,9 @@
+# https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
+#CROSS_COMPILE ?= riscv32-unknown-elf-
+
+# Toolchain from https://nucleisys.com/download.php
+#CROSS_COMPILE ?= riscv-nuclei-elf-
+
 # Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
 CROSS_COMPILE ?= riscv-none-elf-

@ -9,23 +15,21 @@ DEPS_SUBMODULES += $(CH32V20X_SDK)
 CH32V20X_SDK_SRC = $(CH32V20X_SDK)/EVT/EXAM/SRC

 include $(TOP)/$(BOARD_PATH)/board.mk
+CPU_CORE ?= rv32imac-ilp32

 CFLAGS += \
-	-march=rv32imac_zicsr \
-	-mabi=ilp32 \
 	-mcmodel=medany \
 	-ffunction-sections \
 	-fdata-sections \
 	-ffat-lto-objects \
 	-flto \
-	-nostdlib -nostartfiles \
 	-DCFG_TUSB_MCU=OPT_MCU_CH32V20X \
 	-DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED \

 LDFLAGS_GCC += \
 	-Wl,--gc-sections \
-	-specs=nosys.specs \
-	-specs=nano.specs \
+	-nostdlib -nostartfiles \
+	--specs=nosys.specs --specs=nano.specs \

 LD_FILE = $(CH32V20X_SDK_SRC)/Ld/Link.ld

@ -46,5 +50,6 @@ FREERTOS_PORTABLE_SRC = $(FREERTOS_PORTABLE_PATH)/RISC-V
 # wch-link is not supported yet in official openOCD yet. We need to either use
 # 1. download openocd as part of mounriver studio http://www.mounriver.com/download or
 # 2. compiled from modified source https://github.com/dragonlock2/miscboards/blob/main/wch/SDK/riscv-openocd.tar.xz
+OPENOCD ?= $(HOME)/app/riscv-openocd-wch/src/openocd
 flash: $(BUILD)/$(PROJECT).elf
-	openocd -f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg -c init -c halt -c "flash write_image $<" -c reset -c exit
+	$(OPENOCD) -f $(TOP)/$(FAMILY_PATH)/wch-riscv.cfg -c init -c halt -c "flash write_image $<" -c reset -c exit
--- a/hw/bsp/ch32v20x/wch-riscv.cfg
+++ b/hw/bsp/ch32v20x/wch-riscv.cfg
@ -1,4 +1,3 @@
-#interface wlink
 adapter driver wlinke
 adapter speed 6000
 transport select sdi
--- a/hw/bsp/ch32v307/family.cmake
+++ b/hw/bsp/ch32v307/family.cmake
@ -11,7 +11,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TO

 set(FAMILY_MCUS CH32V307 CACHE INTERNAL "")
 set(OPENOCD_OPTION "-f ${CMAKE_CURRENT_LIST_DIR}/wch-riscv.cfg")
-set(OPENOCD_OPTION2 "-c wlink_reset_resume")

 #------------------------------------
 # BOARD_TARGET
--- a/hw/bsp/ch32v307/family.mk
+++ b/hw/bsp/ch32v307/family.mk
@ -1,11 +1,11 @@
 # https://www.embecosm.com/resources/tool-chain-downloads/#riscv-stable
 #CROSS_COMPILE ?= riscv32-unknown-elf-

-# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
-CROSS_COMPILE ?= riscv-none-embed-
+# Toolchain from https://nucleisys.com/download.php
+#CROSS_COMPILE ?= riscv-nuclei-elf-

 # Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
-#CROSS_COMPILE ?= riscv-none-elf-
+CROSS_COMPILE ?= riscv-none-elf-

 # Submodules
 CH32V307_SDK = hw/mcu/wch/ch32v307
@ -16,8 +16,6 @@ CH32V307_SDK_SRC = $(CH32V307_SDK)/EVT/EXAM/SRC
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= rv32imac-ilp32

-# 	-march=rv32imac_zicsr
-
 CFLAGS += \
 	-flto \
 	-msmall-data-limit=8 \
--- a/hw/bsp/ch32v307/wch-riscv.cfg
+++ b/hw/bsp/ch32v307/wch-riscv.cfg
@ -1,13 +1,15 @@
-#interface wlink
-adapter driver wlink
-wlink_set
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+adapter driver wlinke
+adapter speed 6000
+transport select sdi
+
+wlink_set_address 0x00000000
+set _CHIPNAME wch_riscv
+sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001

 set _TARGETNAME $_CHIPNAME.cpu

-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-$_TARGETNAME.0 configure  -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
 set _FLASHNAME $_CHIPNAME.flash

 flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
--- a/hw/bsp/family_support.cmake
+++ b/hw/bsp/family_support.cmake
@ -440,6 +440,7 @@ function(family_flash_openocd TARGET)
 endfunction()

 # Add flash openocd-wch target
+# compiled from https://github.com/hathach/riscv-openocd-wch or https://github.com/dragonlock2/miscboards/blob/main/wch/SDK/riscv-openocd.tar.xz
 function(family_flash_openocd_wch TARGET)
  if (NOT DEFINED OPENOCD)
    set(OPENOCD $ENV{HOME}/app/riscv-openocd-wch/src/openocd)
--- a/hw/bsp/fomu/family.mk
+++ b/hw/bsp/fomu/family.mk
@ -1,9 +1,5 @@
-# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
-CROSS_COMPILE = riscv-none-embed-
-
 # Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
-# CROSS_COMPILE = riscv-none-elf-
-#  -march=rv32i_zicsr
+CROSS_COMPILE = riscv-none-elf-

 CPU_CORE ?= rv32i-ilp32

--- a/hw/bsp/gd32vf103/family.mk
+++ b/hw/bsp/gd32vf103/family.mk
@ -4,11 +4,8 @@
 # Toolchain from https://nucleisys.com/download.php
 #CROSS_COMPILE ?= riscv-nuclei-elf-

-# Toolchain from https://github.com/xpack-dev-tools/riscv-none-embed-gcc-xpack
-CROSS_COMPILE ?= riscv-none-embed-
-
 # Toolchain from https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack
-# CROSS_COMPILE ?= riscv-none-elf-
+CROSS_COMPILE ?= riscv-none-elf-

 # Submodules
 NUCLEI_SDK = hw/mcu/gd/nuclei-sdk
@ -22,8 +19,6 @@ STARTUP_ASM = $(GD32VF103_SDK_SOC)/Common/Source/GCC
 include $(TOP)/$(BOARD_PATH)/board.mk
 CPU_CORE ?= rv32imac-ilp32

-# -march=rv32imac_zicsr
-
 CFLAGS += \
 	-mcmodel=medlow \
 	-mstrict-align \
--- a/src/portable/wch/dcd_ch32_usbfs.c
+++ b/src/portable/wch/dcd_ch32_usbfs.c
@ -201,6 +201,14 @@ void dcd_disconnect(uint8_t rhport) {
    USBOTG_FS->BASE_CTRL &= ~USBFS_CTRL_DEV_PUEN;
 }

+void dcd_sof_enable(uint8_t rhport, bool en)
+{
+  (void) rhport;
+  (void) en;
+
+  // TODO implement later
+}
+
 void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) {
    (void) rhport;
    if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&