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https://github.com/hathach/tinyusb.git
synced 2025-03-23 13:20:54 +00:00
remove toggle walkaround, fix control stall race condition
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hathach
parent
520df6bb53
commit
2a479175ae
@ -51,12 +51,6 @@ typedef struct
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// Endpoint 0-5, each can only be either OUT or In
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xfer_desc_t _dcd_xfer[EP_COUNT];
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// Indicate that DATA Toggle for Control Status is incorrect, which must always be DATA1 by USB Specs.
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// However SAMG DToggle is read-only, therefore we must duplicate the status phase ( D0 then D1 )
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// as walk-around to resolve this. The D0 status packet is likely to be discarded by USB Host safely.
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// Note: Only needed for IN Status e.g CDC_SET_LINE_CODING, since out data is sent by host
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volatile bool _walkaround_incorrect_dtoggle_control_status;
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void xfer_epsize_set(xfer_desc_t* xfer, uint16_t epsize)
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{
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xfer->epsize = epsize;
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@ -110,6 +104,49 @@ static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
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}
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}
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//! Bitmap for all status bits in CSR that are not affected by a value 1.
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#define UDP_REG_NO_EFFECT_1_ALL (UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 | UDP_CSR_STALLSENT | UDP_CSR_RXSETUP | UDP_CSR_TXCOMP)
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/*! Sets specified bit(s) in the UDP_CSR.
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* \param ep
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Endpoint number.
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* \param bits Bitmap to set to 1.
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*/
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#define csr_set(ep, bits) \
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do { \
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volatile uint32_t reg; \
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volatile uint32_t nop_count; \
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reg = UDP->UDP_CSR[ep]; \
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reg |= UDP_REG_NO_EFFECT_1_ALL; \
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reg |= (bits); \
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UDP->UDP_CSR[ep] = reg; \
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for (nop_count = 0; nop_count < 20; nop_count ++) {\
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__NOP(); \
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} \
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} while (0)
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/*! Clears specified bit(s) in the UDP_CSR.
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* \param ep
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Endpoint number.
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* \param bits Bitmap to set to 0.
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*/
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#define csr_clear(ep, bits) \
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do { \
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volatile uint32_t reg; \
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volatile uint32_t nop_count; \
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reg = UDP->UDP_CSR[ep]; \
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reg |= UDP_REG_NO_EFFECT_1_ALL; \
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reg &= ~(bits); \
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UDP->UDP_CSR[ep] = reg; \
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for (nop_count = 0; nop_count < 20; nop_count ++) {\
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__NOP(); \
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} \
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} while (0)
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#define udp_clear_csr csr_clear
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#define udp_set_csr csr_set
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/*------------------------------------------------------------------*/
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/* Device API
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*------------------------------------------------------------------*/
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@ -117,7 +154,6 @@ static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
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// Set up endpoint 0, clear all other endpoints
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static void bus_reset(void)
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{
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_walkaround_incorrect_dtoggle_control_status = false;
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tu_memclr(_dcd_xfer, sizeof(_dcd_xfer));
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xfer_epsize_set(&_dcd_xfer[0], CFG_TUD_ENDPOINT0_SIZE);
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@ -189,7 +225,6 @@ void dcd_disconnect(uint8_t rhport)
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UDP->UDP_TXVC = UDP_TXVC_TXVDIS_Msk;
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}
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//--------------------------------------------------------------------+
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// Endpoint API
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//--------------------------------------------------------------------+
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@ -240,7 +275,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
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xfer_epsize_set(&_dcd_xfer[epnum], ep_desc->wMaxPacketSize.size);
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// Configure type and eanble EP
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// Configure type and enable EP
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UDP->UDP_CSR[epnum] = UDP_CSR_EPEDS_Msk | UDP_CSR_EPTYPE(ep_desc->bmAttributes.xfer + 4*dir);
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// Enable EP Interrupt for IN
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@ -260,49 +295,30 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
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xfer_desc_t* xfer = &_dcd_xfer[epnum];
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xfer_begin(xfer, buffer, total_bytes);
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// Control Status Stage if EP0 with len = 0 and direction is opposite of current Data Stage
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if ( (epnum == 0) && /*(total_bytes == 0) &&*/ (dir != ((UDP->UDP_CSR[epnum] & UDP_CSR_DIR_Msk) >> UDP_CSR_DIR_Pos)) )
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{
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TU_LOG2_INT(dir);
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if ( dir )
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{
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csr_set(0, UDP_CSR_DIR_Msk);
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}else
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{
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csr_clear(0, UDP_CSR_DIR_Msk);
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}
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}
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if (dir == TUSB_DIR_OUT)
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{
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// Clear EP0 direction bit
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if (epnum == 0) UDP->UDP_CSR[epnum] &= ~UDP_CSR_DIR_Msk;
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// Enable interrupt when starting OUT transfer
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if (epnum != 0) UDP->UDP_IER |= (1 << epnum);
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}
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else
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{
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if (epnum == 0)
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{
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// Previous EP0 direction is OUT --> This transfer is ZLP control status.
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if ( !(UDP->UDP_CSR[epnum] & UDP_CSR_DIR_Msk) )
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{
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// Set EP0 dir bit
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UDP->UDP_CSR[epnum] |= UDP_CSR_DIR_Msk;
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// DATA Toggle is 0, USB Specs requires Status Stage must be DATA1
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// Since SAMG DToggle is read-only, we mark this and implement the walk-around
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if ( !(UDP->UDP_CSR[epnum] & UDP_CSR_DTGLE_Msk) )
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{
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TU_LOG2("Incorrect DATA TOGGLE, Control Status must be DATA1\n");
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// DTGLE is read-only on SAMG, this statement has no effect
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UDP->UDP_CSR[epnum] |= UDP_CSR_DTGLE_Msk;
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// WALKROUND: duplicate IN transfer to send DATA1 status packet
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// set flag for irq to skip reporting first incorrect packet
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_walkaround_incorrect_dtoggle_control_status = true;
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UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
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while ( UDP->UDP_CSR[epnum] & UDP_CSR_TXPKTRDY_Msk ) {}
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_walkaround_incorrect_dtoggle_control_status = false;
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}
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}
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}
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xact_ep_write(epnum, xfer->buffer, xfer_packet_len(xfer));
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// TX ready for transfer
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UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
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csr_set(epnum, UDP_CSR_TXPKTRDY_Msk);
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}
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return true;
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@ -313,10 +329,14 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
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{
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(void) rhport;
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// For EP0 USBD will stall both EP0 Out and In with 0x00 and 0x80
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// only handle one by skipping 0x80
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if ( ep_addr == tu_edpt_addr(0, TUSB_DIR_IN_MASK) ) return;
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uint8_t const epnum = tu_edpt_number(ep_addr);
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// Set force stall bit
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UDP->UDP_CSR[epnum] |= UDP_CSR_FORCESTALL_Msk;
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csr_set(epnum, UDP_CSR_FORCESTALL_Msk);
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}
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// clear stall, data toggle is also reset to DATA0
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@ -327,11 +347,11 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr)
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uint8_t const epnum = tu_edpt_number(ep_addr);
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// clear stall
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UDP->UDP_CSR[epnum] &= ~UDP_CSR_FORCESTALL_Msk;
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csr_clear(epnum, UDP_CSR_FORCESTALL_Msk);
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// must also reset EP to clear data toggle
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UDP->UDP_RST_EP = tu_bit_set(UDP->UDP_RST_EP, epnum);
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UDP->UDP_RST_EP = tu_bit_clear(UDP->UDP_RST_EP, epnum);
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UDP->UDP_RST_EP |= (1 << epnum);
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UDP->UDP_RST_EP &= ~(1 << epnum);
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}
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//--------------------------------------------------------------------+
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@ -368,8 +388,10 @@ void dcd_int_handler(uint8_t rhport)
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if ( intr_status & TU_BIT(0) )
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{
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uint32_t csr0 = UDP->UDP_CSR[0];
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// setup packet
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if (UDP->UDP_CSR[0] & UDP_CSR_RXSETUP)
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if (csr0 & UDP_CSR_RXSETUP)
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{
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// get setup from FIFO
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uint8_t setup[8];
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@ -381,19 +403,31 @@ void dcd_int_handler(uint8_t rhport)
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// notify usbd
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dcd_event_setup_received(rhport, setup, true);
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// Reset FIFO
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// UDP->UDP_RST_EP |= (1 << 0);
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// UDP->UDP_RST_EP &= ~(1 << 0);
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csr0 &= ~(UDP_CSR_TXPKTRDY_Msk | UDP_CSR_TXCOMP_Msk | UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1);
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// Set EP direction bit according to DATA stage
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if (setup[0] & 0x80)
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// must be set before RXSETUP is clear per specs
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if ( tu_edpt_dir(setup[0]) )
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{
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UDP->UDP_CSR[0] |= UDP_CSR_DIR_Msk;
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}else
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//csr_set(0, UDP_CSR_DIR_Msk);
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csr0 |= UDP_CSR_DIR_Msk;
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}
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else
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{
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UDP->UDP_CSR[0] &= ~UDP_CSR_DIR_Msk;
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//csr_clear(0, UDP_CSR_DIR_Msk);
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csr0 &= ~UDP_CSR_DIR_Msk;
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}
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// Clear Setup bit & stall bit if needed
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UDP->UDP_CSR[0] &= ~(UDP_CSR_RXSETUP_Msk | UDP_CSR_FORCESTALL_Msk);
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//csr_clear(0, UDP_CSR_RXSETUP_Msk | UDP_CSR_FORCESTALL_Msk);
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csr0 &= ~(UDP_CSR_RXSETUP_Msk | UDP_CSR_STALLSENT_Msk | UDP_CSR_FORCESTALL_Msk);
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return;
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UDP->UDP_CSR[0] = csr0;
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for (uint32_t nop_count = 0; nop_count < 20; nop_count ++) __NOP();
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}
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}
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@ -416,21 +450,19 @@ void dcd_int_handler(uint8_t rhport)
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xact_ep_write(epnum, xfer->buffer, xact_len);
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// TX ready for transfer
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//csr_set(epnum, UDP_CSR_TXPKTRDY_Msk);
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UDP->UDP_CSR[epnum] |= UDP_CSR_TXPKTRDY_Msk;
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}else
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{
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// WALKAROUND: Skip reporting this incorrect DATA Toggle status IN transfer
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if ( !(_walkaround_incorrect_dtoggle_control_status && (epnum == 0) && (xfer->actual_len == 0)) )
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{
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// xfer is complete
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dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
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// xfer is complete
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dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->actual_len, XFER_RESULT_SUCCESS, true);
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// Required since control OUT can happen right after before stack handle this event
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xfer_end(xfer);
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}
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// Required since control OUT can happen right after before stack handle this event
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xfer_end(xfer);
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}
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// Clear TX Complete bit
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//csr_clear(epnum, UDP_CSR_TXCOMP_Msk);
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UDP->UDP_CSR[epnum] &= ~UDP_CSR_TXCOMP_Msk;
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}
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@ -456,12 +488,14 @@ void dcd_int_handler(uint8_t rhport)
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}
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// Clear DATA Bank0/1 bit
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//csr_clear(epnum, banks_complete);
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UDP->UDP_CSR[epnum] &= ~banks_complete;
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}
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// Stall sent to host
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if (UDP->UDP_CSR[epnum] & UDP_CSR_STALLSENT_Msk)
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{
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//csr_clear(epnum, UDP_CSR_STALLSENT_Msk);
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UDP->UDP_CSR[epnum] &= ~UDP_CSR_STALLSENT_Msk;
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}
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}
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