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Merge pull request #2888 from hathach/esp32p4-host-dma

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Esp32p4 host dma
This commit is contained in:
Ha Thach 2024-11-27 12:52:56 +07:00 committed by GitHub
commit 2732aff7dd
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26 changed files with 337 additions and 284 deletions
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14
examples/host/cdc_msc_hid_freertos/src/cdc_app.c
View File

@ -28,22 +28,8 @@
#include "bsp/board_api.h"
#if TUSB_MCU_VENDOR_ESPRESSIF
// ESP-IDF need "freertos/" prefix in include path.
// CFG_TUSB_OS_INC_PATH should be defined accordingly.
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/queue.h"
#include "freertos/task.h"
#include "freertos/timers.h"
#define CDC_STACK_SZIE 2048
#else
#include "FreeRTOS.h"
#include "semphr.h"
#include "queue.h"
#include "task.h"
#include "timers.h"
#define CDC_STACK_SZIE (3*configMINIMAL_STACK_SIZE/2)
#endif

14
examples/host/cdc_msc_hid_freertos/src/main.c
View File

@ -31,22 +31,8 @@
#include "tusb.h"
#if TUSB_MCU_VENDOR_ESPRESSIF
// ESP-IDF need "freertos/" prefix in include path.
// CFG_TUSB_OS_INC_PATH should be defined accordingly.
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/queue.h"
#include "freertos/task.h"
#include "freertos/timers.h"
#define USBH_STACK_SIZE 4096
#else
#include "FreeRTOS.h"
#include "semphr.h"
#include "queue.h"
#include "task.h"
#include "timers.h"
// Increase stack size when debug log is enabled
#define USBH_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1)
#endif

9
examples/host/cdc_msc_hid_freertos/src/msc_app.c
View File

@ -25,7 +25,10 @@
#include "tusb.h"
static scsi_inquiry_resp_t inquiry_resp;
// define the buffer to be place in USB/DMA memory with correct alignment/cache line size
CFG_TUH_MEM_SECTION static struct {
TUH_EPBUF_TYPE_DEF(scsi_inquiry_resp_t, inquiry);
} scsi_resp;
void msc_app_init(void) {
// nothing to do
@ -41,7 +44,7 @@ bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const *cb_dat
}
// Print out Vendor ID, Product ID and Rev
printf("%.8s %.16s rev %.4s\r\n", inquiry_resp.vendor_id, inquiry_resp.product_id, inquiry_resp.product_rev);
printf("%.8s %.16s rev %.4s\r\n", scsi_resp.inquiry.vendor_id, scsi_resp.inquiry.product_id, scsi_resp.inquiry.product_rev);
// Get capacity of device
uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
@ -58,7 +61,7 @@ void tuh_msc_mount_cb(uint8_t dev_addr) {
printf("A MassStorage device is mounted\r\n");
uint8_t const lun = 0;
tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb, 0);
tuh_msc_inquiry(dev_addr, lun, &scsi_resp.inquiry, inquiry_complete_cb, 0);
}
void tuh_msc_umount_cb(uint8_t dev_addr) {

59
examples/host/device_info/src/main.c
View File

@ -63,6 +63,14 @@ enum {
};
static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED;
// Declare for buffer for usb transfer, may need to be in USB/DMA section and
// multiple of dcache line size if dcache is enabled (for some ports).
CFG_TUH_MEM_SECTION struct {
TUH_EPBUF_TYPE_DEF(tusb_desc_device_t, device);
TUH_EPBUF_DEF(serial, 64*sizeof(uint16_t));
TUH_EPBUF_DEF(buf, 128*sizeof(uint16_t));
} desc;
void led_blinking_task(void* param);
static void print_utf16(uint16_t* temp_buf, size_t buf_len);
@ -109,60 +117,57 @@ void tuh_mount_cb(uint8_t daddr) {
blink_interval_ms = BLINK_MOUNTED;
// Get Device Descriptor
tusb_desc_device_t desc_device;
uint8_t xfer_result = tuh_descriptor_get_device_sync(daddr, &desc_device, 18);
uint8_t xfer_result = tuh_descriptor_get_device_sync(daddr, &desc.device, 18);
if (XFER_RESULT_SUCCESS != xfer_result) {
printf("Failed to get device descriptor\r\n");
return;
}
uint16_t serial[64];
uint16_t buf[256];
printf("Device %u: ID %04x:%04x SN ", daddr, desc_device.idVendor, desc_device.idProduct);
xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, serial, sizeof(serial));
printf("Device %u: ID %04x:%04x SN ", daddr, desc.device.idVendor, desc.device.idProduct);
xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, desc.serial, sizeof(desc.serial));
if (XFER_RESULT_SUCCESS != xfer_result) {
uint16_t* serial = (uint16_t*)(uintptr_t) desc.serial;
serial[0] = 'n';
serial[1] = '/';
serial[2] = 'a';
serial[3] = 0;
}
print_utf16(serial, TU_ARRAY_SIZE(serial));
print_utf16((uint16_t*)(uintptr_t) desc.serial, sizeof(desc.serial)/2);
printf("\r\n");
printf("Device Descriptor:\r\n");
printf(" bLength %u\r\n", desc_device.bLength);
printf(" bDescriptorType %u\r\n", desc_device.bDescriptorType);
printf(" bcdUSB %04x\r\n", desc_device.bcdUSB);
printf(" bDeviceClass %u\r\n", desc_device.bDeviceClass);
printf(" bDeviceSubClass %u\r\n", desc_device.bDeviceSubClass);
printf(" bDeviceProtocol %u\r\n", desc_device.bDeviceProtocol);
printf(" bMaxPacketSize0 %u\r\n", desc_device.bMaxPacketSize0);
printf(" idVendor 0x%04x\r\n", desc_device.idVendor);
printf(" idProduct 0x%04x\r\n", desc_device.idProduct);
printf(" bcdDevice %04x\r\n", desc_device.bcdDevice);
printf(" bLength %u\r\n", desc.device.bLength);
printf(" bDescriptorType %u\r\n", desc.device.bDescriptorType);
printf(" bcdUSB %04x\r\n", desc.device.bcdUSB);
printf(" bDeviceClass %u\r\n", desc.device.bDeviceClass);
printf(" bDeviceSubClass %u\r\n", desc.device.bDeviceSubClass);
printf(" bDeviceProtocol %u\r\n", desc.device.bDeviceProtocol);
printf(" bMaxPacketSize0 %u\r\n", desc.device.bMaxPacketSize0);
printf(" idVendor 0x%04x\r\n", desc.device.idVendor);
printf(" idProduct 0x%04x\r\n", desc.device.idProduct);
printf(" bcdDevice %04x\r\n", desc.device.bcdDevice);
// Get String descriptor using Sync API
printf(" iManufacturer %u ", desc_device.iManufacturer);
xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
printf(" iManufacturer %u ", desc.device.iManufacturer);
xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf));
if (XFER_RESULT_SUCCESS == xfer_result) {
print_utf16(buf, TU_ARRAY_SIZE(buf));
print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2);
}
printf("\r\n");
printf(" iProduct %u ", desc_device.iProduct);
xfer_result = tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf));
printf(" iProduct %u ", desc.device.iProduct);
xfer_result = tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf));
if (XFER_RESULT_SUCCESS == xfer_result) {
print_utf16(buf, TU_ARRAY_SIZE(buf));
print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2);
}
printf("\r\n");
printf(" iSerialNumber %u ", desc_device.iSerialNumber);
printf((char*)serial); // serial is already to UTF-8
printf(" iSerialNumber %u ", desc.device.iSerialNumber);
printf((char*)desc.serial); // serial is already to UTF-8
printf("\r\n");
printf(" bNumConfigurations %u\r\n", desc_device.bNumConfigurations);
printf(" bNumConfigurations %u\r\n", desc.device.bNumConfigurations);
}
// Invoked when device is unmounted (bus reset/unplugged)

10
examples/host/msc_file_explorer/src/msc_app.c
View File

@ -53,7 +53,11 @@ static CLI_UINT cli_buffer[BYTES_TO_CLI_UINTS(CLI_BUFFER_SIZE)];
static FATFS fatfs[CFG_TUH_DEVICE_MAX]; // for simplicity only support 1 LUN per device
static volatile bool _disk_busy[CFG_TUH_DEVICE_MAX];
static scsi_inquiry_resp_t inquiry_resp;
// define the buffer to be place in USB/DMA memory with correct alignment/cache line size
CFG_TUH_MEM_SECTION static struct {
TUH_EPBUF_TYPE_DEF(scsi_inquiry_resp_t, inquiry);
} scsi_resp;
//--------------------------------------------------------------------+
//
@ -107,7 +111,7 @@ bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_da
}
// Print out Vendor ID, Product ID and Rev
printf("%.8s %.16s rev %.4s\r\n", inquiry_resp.vendor_id, inquiry_resp.product_id, inquiry_resp.product_rev);
printf("%.8s %.16s rev %.4s\r\n", scsi_resp.inquiry.vendor_id, scsi_resp.inquiry.product_id, scsi_resp.inquiry.product_rev);
// Get capacity of device
uint32_t const block_count = tuh_msc_get_block_count(dev_addr, cbw->lun);
@ -145,7 +149,7 @@ void tuh_msc_mount_cb(uint8_t dev_addr)
printf("A MassStorage device is mounted\r\n");
uint8_t const lun = 0;
tuh_msc_inquiry(dev_addr, lun, &inquiry_resp, inquiry_complete_cb, 0);
tuh_msc_inquiry(dev_addr, lun, &scsi_resp.inquiry, inquiry_complete_cb, 0);
}
void tuh_msc_umount_cb(uint8_t dev_addr)

40
hw/bsp/espressif/boards/family.c
View File

@ -35,10 +35,6 @@
#include "driver/uart.h"
#include "esp_private/periph_ctrl.h"
// Note; current code use UART0 can cause device to reset while monitoring
#define USE_UART 0
#define UART_ID UART_NUM_0
#ifdef NEOPIXEL_PIN
#include "led_strip.h"
static led_strip_handle_t led_strip;
@ -57,19 +53,6 @@ static bool usb_init(void);
// Initialize on-board peripherals : led, button, uart and USB
void board_init(void) {
#if USE_UART
// uart init
uart_config_t uart_config = {
.baud_rate = 115200,
.data_bits = UART_DATA_8_BITS,
.parity = UART_PARITY_DISABLE,
.stop_bits = UART_STOP_BITS_1,
.flow_ctrl = UART_HW_FLOWCTRL_DISABLE
};
uart_driver_install(UART_ID, 1024, 0, 0, NULL, 0);
uart_param_config(UART_ID, &uart_config);
#endif
#ifdef NEOPIXEL_PIN
#ifdef NEOPIXEL_POWER_PIN
gpio_reset_pin(NEOPIXEL_POWER_PIN);
@ -145,23 +128,26 @@ uint32_t board_button_read(void) {
// Get characters from UART
int board_uart_read(uint8_t* buf, int len) {
#if USE_UART
return uart_read_bytes(UART_ID, buf, len, 0);
#else
return -1;
#endif
for (int i=0; i<len; i++) {
int c = getchar();
if (c == EOF) {
return i;
}
buf[i] = (uint8_t) c;
}
return len;
}
// Send characters to UART
int board_uart_write(void const* buf, int len) {
(void) buf;
(void) len;
return 0;
for (int i = 0; i < len; i++) {
putchar(((char*) buf)[i]);
}
return len;
}
int board_getchar(void) {
uint8_t c = 0;
return board_uart_read(&c, 1) > 0 ? (int) c : (-1);
return getchar();
}
//--------------------------------------------------------------------

4
hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt
View File

@ -18,7 +18,8 @@ list(APPEND compile_definitions
if (target STREQUAL esp32p4)
# P4 change alignment to 64 (DCache line size) for possible DMA configuration
list(APPEND compile_definitions
CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
CFG_TUD_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
CFG_TUH_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
)
endif ()
@ -68,6 +69,7 @@ if (DEFINED LOG)
endif()
if(DEFINED CFLAGS_CLI)
separate_arguments(CFLAGS_CLI)
list(APPEND compile_definitions ${CFLAGS_CLI})
endif()

2
hw/bsp/family_support.cmake
View File

@ -206,6 +206,7 @@ function(family_configure_common TARGET RTOS)
# compile define from command line
if(DEFINED CFLAGS_CLI)
separate_arguments(CFLAGS_CLI)
target_compile_options(${TARGET} PUBLIC ${CFLAGS_CLI})
endif()
@ -291,6 +292,7 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS)
# compile define from command line
if(DEFINED CFLAGS_CLI)
separate_arguments(CFLAGS_CLI)
target_compile_options(${TARGET}-tinyusb PUBLIC ${CFLAGS_CLI})
endif()

1
hw/bsp/rp2040/family.cmake
View File

@ -191,6 +191,7 @@ function(family_configure_target TARGET RTOS)
# compile define from command line
if(DEFINED CFLAGS_CLI)
separate_arguments(CFLAGS_CLI)
target_compile_options(${TARGET} PUBLIC ${CFLAGS_CLI})
endif()

36
src/class/cdc/cdc_host.c
View File

@ -73,15 +73,17 @@ typedef struct {
tu_edpt_stream_t rx;
uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
CFG_TUH_MEM_ALIGN uint8_t tx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE];
CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE];
} stream;
} cdch_interface_t;
CFG_TUH_MEM_SECTION
typedef struct {
TUH_EPBUF_DEF(tx, CFG_TUH_CDC_TX_EPSIZE);
TUH_EPBUF_DEF(rx, CFG_TUH_CDC_TX_EPSIZE);
} cdch_epbuf_t;
static cdch_interface_t cdch_data[CFG_TUH_CDC];
CFG_TUH_MEM_SECTION static cdch_epbuf_t cdch_epbuf[CFG_TUH_CDC];
//--------------------------------------------------------------------+
// Serial Driver
@ -626,13 +628,14 @@ bool cdch_init(void) {
tu_memclr(cdch_data, sizeof(cdch_data));
for (size_t i = 0; i < CFG_TUH_CDC; i++) {
cdch_interface_t* p_cdc = &cdch_data[i];
cdch_epbuf_t* epbuf = &cdch_epbuf[i];
tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false,
p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE,
p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE);
epbuf->tx, CFG_TUH_CDC_TX_EPSIZE);
tu_edpt_stream_init(&p_cdc->stream.rx, true, false, false,
p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE,
p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE);
epbuf->rx, CFG_TUH_CDC_RX_EPSIZE);
}
return true;
@ -654,7 +657,9 @@ void cdch_close(uint8_t daddr) {
TU_LOG_DRV(" CDCh close addr = %u index = %u\r\n", daddr, idx);
// Invoke application callback
if (tuh_cdc_umount_cb) tuh_cdc_umount_cb(idx);
if (tuh_cdc_umount_cb) {
tuh_cdc_umount_cb(idx);
}
p_cdc->daddr = 0;
p_cdc->bInterfaceNumber = 0;
@ -675,7 +680,9 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
if ( ep_addr == p_cdc->stream.tx.ep_addr ) {
// invoke tx complete callback to possibly refill tx fifo
if (tuh_cdc_tx_complete_cb) tuh_cdc_tx_complete_cb(idx);
if (tuh_cdc_tx_complete_cb) {
tuh_cdc_tx_complete_cb(idx);
}
if ( 0 == tu_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) ) {
// If there is no data left, a ZLP should be sent if:
@ -695,7 +702,9 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t
}
// invoke receive callback
if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(idx);
if (tuh_cdc_rx_cb) {
tuh_cdc_rx_cb(idx);
}
// prepare for next transfer if needed
tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx);
@ -738,9 +747,8 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
if (TUSB_CLASS_CDC == itf_desc->bInterfaceClass &&
CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) {
return acm_open(daddr, itf_desc, max_len);
}
else if (SERIAL_DRIVER_COUNT > 1 &&
TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) {
} else if (SERIAL_DRIVER_COUNT > 1 &&
TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) {
uint16_t vid, pid;
TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid));
@ -760,7 +768,9 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d
static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) {
TU_LOG_DRV("CDCh Set Configure complete\r\n");
p_cdc->mounted = true;
if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx);
if (tuh_cdc_mount_cb) {
tuh_cdc_mount_cb(idx);
}
// Prepare for incoming data
tu_edpt_stream_read_xfer(p_cdc->daddr, &p_cdc->stream.rx);

3
src/class/cdc/cdc_host.h
View File

@ -89,8 +89,7 @@ bool tuh_cdc_get_dtr(uint8_t idx);
bool tuh_cdc_get_rts(uint8_t idx);
// Check if interface is connected (DTR active)
TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx)
{
TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx) {
return tuh_cdc_get_dtr(idx);
}

38
src/class/hid/hid_host.c
View File

@ -45,12 +45,11 @@
//--------------------------------------------------------------------+
typedef struct {
uint8_t daddr;
uint8_t itf_num;
uint8_t ep_in;
uint8_t ep_out;
bool mounted; // Enumeration is complete
bool mounted; // Enumeration is complete
uint8_t itf_protocol; // None, Keyboard, Mouse
uint8_t protocol_mode; // Boot (0) or Report protocol (1)
@ -59,15 +58,17 @@ typedef struct {
uint16_t epin_size;
uint16_t epout_size;
CFG_TUH_MEM_ALIGN uint8_t epin_buf[CFG_TUH_HID_EPIN_BUFSIZE];
CFG_TUH_MEM_ALIGN uint8_t epout_buf[CFG_TUH_HID_EPOUT_BUFSIZE];
} hidh_interface_t;
CFG_TUH_MEM_SECTION
tu_static hidh_interface_t _hidh_itf[CFG_TUH_HID];
typedef struct {
TUH_EPBUF_DEF(epin, CFG_TUH_HID_EPIN_BUFSIZE);
TUH_EPBUF_DEF(epout, CFG_TUH_HID_EPOUT_BUFSIZE);
} hidh_epbuf_t;
tu_static uint8_t _hidh_default_protocol = HID_PROTOCOL_BOOT;
static hidh_interface_t _hidh_itf[CFG_TUH_HID];
CFG_TUH_MEM_SECTION static hidh_epbuf_t _hidh_epbuf[CFG_TUH_HID];
static uint8_t _hidh_default_protocol = HID_PROTOCOL_BOOT;
//--------------------------------------------------------------------+
// Helper
@ -78,6 +79,10 @@ TU_ATTR_ALWAYS_INLINE static inline hidh_interface_t* get_hid_itf(uint8_t daddr,
return (p_hid->daddr == daddr) ? p_hid : NULL;
}
TU_ATTR_ALWAYS_INLINE static inline hidh_epbuf_t* get_hid_epbuf(uint8_t idx) {
return &_hidh_epbuf[idx];
}
// Get instance ID by endpoint address
static uint8_t get_idx_by_epaddr(uint8_t daddr, uint8_t ep_addr) {
for (uint8_t idx = 0; idx < CFG_TUH_HID; idx++) {
@ -353,11 +358,12 @@ bool tuh_hid_receive_ready(uint8_t dev_addr, uint8_t idx) {
bool tuh_hid_receive_report(uint8_t daddr, uint8_t idx) {
hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
TU_VERIFY(p_hid);
hidh_epbuf_t* epbuf = get_hid_epbuf(idx);
// claim endpoint
TU_VERIFY(usbh_edpt_claim(daddr, p_hid->ep_in));
if (!usbh_edpt_xfer(daddr, p_hid->ep_in, p_hid->epin_buf, p_hid->epin_size)) {
if (!usbh_edpt_xfer(daddr, p_hid->ep_in, epbuf->epin, p_hid->epin_size)) {
usbh_edpt_release(daddr, p_hid->ep_in);
return false;
}
@ -381,6 +387,7 @@ bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const vo
hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
TU_VERIFY(p_hid);
hidh_epbuf_t* epbuf = get_hid_epbuf(idx);
if (p_hid->ep_out == 0) {
// This HID does not have an out endpoint (other than control)
@ -396,16 +403,16 @@ bool tuh_hid_send_report(uint8_t daddr, uint8_t idx, uint8_t report_id, const vo
if (report_id == 0) {
// No report ID in transmission
memcpy(&p_hid->epout_buf[0], report, len);
memcpy(&epbuf->epout[0], report, len);
} else {
p_hid->epout_buf[0] = report_id;
memcpy(&p_hid->epout_buf[1], report, len);
epbuf->epout[0] = report_id;
memcpy(&epbuf->epout[1], report, len);
++len; // 1 more byte for report_id
}
TU_LOG3_MEM(p_hid->epout_buf, len, 2);
if (!usbh_edpt_xfer(daddr, p_hid->ep_out, p_hid->epout_buf, len)) {
if (!usbh_edpt_xfer(daddr, p_hid->ep_out, epbuf->epout, len)) {
usbh_edpt_release(daddr, p_hid->ep_out);
return false;
}
@ -434,14 +441,15 @@ bool hidh_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t
hidh_interface_t* p_hid = get_hid_itf(daddr, idx);
TU_VERIFY(p_hid);
hidh_epbuf_t* epbuf = get_hid_epbuf(idx);
if (dir == TUSB_DIR_IN) {
TU_LOG_DRV(" Get Report callback (%u, %u)\r\n", daddr, idx);
TU_LOG3_MEM(p_hid->epin_buf, xferred_bytes, 2);
tuh_hid_report_received_cb(daddr, idx, p_hid->epin_buf, (uint16_t) xferred_bytes);
tuh_hid_report_received_cb(daddr, idx, epbuf->epin, (uint16_t) xferred_bytes);
} else {
if (tuh_hid_report_sent_cb) {
tuh_hid_report_sent_cb(daddr, idx, p_hid->epout_buf, (uint16_t) xferred_bytes);
tuh_hid_report_sent_cb(daddr, idx, epbuf->epout, (uint16_t) xferred_bytes);
}
}

2
src/class/msc/msc_device.c
View File

@ -147,7 +147,7 @@ static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) {
return (uint16_t) (cbw->total_bytes / block_count);
}
uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) {
static uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) {
uint8_t status = MSC_CSW_STATUS_PASSED;
uint16_t const block_count = rdwr10_get_blockcount(cbw);

97
src/class/msc/msc_host.c
View File

@ -54,38 +54,37 @@ typedef struct {
uint8_t itf_num;
uint8_t ep_in;
uint8_t ep_out;
uint8_t max_lun;
volatile bool configured; // Receive SET_CONFIGURE
volatile bool mounted; // Enumeration is complete
struct {
uint32_t block_size;
uint32_t block_count;
} capacity[CFG_TUH_MSC_MAXLUN];
//------------- SCSI -------------//
// SCSI command data
uint8_t stage;
void* buffer;
tuh_msc_complete_cb_t complete_cb;
uintptr_t complete_arg;
CFG_TUH_MEM_ALIGN msc_cbw_t cbw;
CFG_TUH_MEM_ALIGN msc_csw_t csw;
struct {
uint32_t block_size;
uint32_t block_count;
} capacity[CFG_TUH_MSC_MAXLUN];
} msch_interface_t;
CFG_TUH_MEM_SECTION static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
typedef struct {
TUH_EPBUF_TYPE_DEF(msc_cbw_t, cbw);
TUH_EPBUF_TYPE_DEF(msc_csw_t, csw);
} msch_epbuf_t;
// buffer used to read scsi information when mounted
// largest response data currently is inquiry TODO Inquiry is not part of enum anymore
CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN
static uint8_t _msch_buffer[sizeof(scsi_inquiry_resp_t)];
static msch_interface_t _msch_itf[CFG_TUH_DEVICE_MAX];
CFG_TUH_MEM_SECTION static msch_epbuf_t _msch_epbuf[CFG_TUH_DEVICE_MAX];
// FIXME potential nul reference
TU_ATTR_ALWAYS_INLINE
static inline msch_interface_t* get_itf(uint8_t dev_addr) {
return &_msch_itf[dev_addr - 1];
TU_ATTR_ALWAYS_INLINE static inline msch_interface_t* get_itf(uint8_t daddr) {
return &_msch_itf[daddr - 1];
}
TU_ATTR_ALWAYS_INLINE static inline msch_epbuf_t* get_epbuf(uint8_t daddr) {
return &_msch_epbuf[daddr - 1];
}
//--------------------------------------------------------------------+
@ -133,14 +132,15 @@ bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data,
// claim endpoint
TU_VERIFY(usbh_edpt_claim(daddr, p_msc->ep_out));
msch_epbuf_t* epbuf = get_epbuf(daddr);
p_msc->cbw = *cbw;
p_msc->stage = MSC_STAGE_CMD;
epbuf->cbw = *cbw;
p_msc->buffer = data;
p_msc->complete_cb = complete_cb;
p_msc->complete_arg = arg;
p_msc->stage = MSC_STAGE_CMD;
if (!usbh_edpt_xfer(daddr, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t))) {
if (!usbh_edpt_xfer(daddr, p_msc->ep_out, (uint8_t*) &epbuf->cbw, sizeof(msc_cbw_t))) {
usbh_edpt_release(daddr, p_msc->ep_out);
return false;
}
@ -286,6 +286,7 @@ bool tuh_msc_reset(uint8_t dev_addr) {
//--------------------------------------------------------------------+
bool msch_init(void) {
TU_LOG_DRV("sizeof(msch_interface_t) = %u\r\n", sizeof(msch_interface_t));
TU_LOG_DRV("sizeof(msch_epbuf_t) = %u\r\n", sizeof(msch_epbuf_t));
tu_memclr(_msch_itf, sizeof(_msch_itf));
return true;
}
@ -303,7 +304,9 @@ void msch_close(uint8_t dev_addr) {
// invoke Application Callback
if (p_msc->mounted) {
if (tuh_msc_umount_cb) tuh_msc_umount_cb(dev_addr);
if (tuh_msc_umount_cb) {
tuh_msc_umount_cb(dev_addr);
}
}
tu_memclr(p_msc, sizeof(msch_interface_t));
@ -311,30 +314,28 @@ void msch_close(uint8_t dev_addr) {
bool msch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes) {
msch_interface_t* p_msc = get_itf(dev_addr);
msc_cbw_t const * cbw = &p_msc->cbw;
msc_csw_t * csw = &p_msc->csw;
msch_epbuf_t* epbuf = get_epbuf(dev_addr);
msc_cbw_t const * cbw = &epbuf->cbw;
msc_csw_t * csw = &epbuf->csw;
switch (p_msc->stage) {
case MSC_STAGE_CMD:
// Must be Command Block
TU_ASSERT(ep_addr == p_msc->ep_out && event == XFER_RESULT_SUCCESS && xferred_bytes == sizeof(msc_cbw_t));
if (cbw->total_bytes && p_msc->buffer) {
// Data stage if any
p_msc->stage = MSC_STAGE_DATA;
uint8_t const ep_data = (cbw->dir & TUSB_DIR_IN_MASK) ? p_msc->ep_in : p_msc->ep_out;
TU_ASSERT(usbh_edpt_xfer(dev_addr, ep_data, p_msc->buffer, (uint16_t) cbw->total_bytes));
} else {
// Status stage
p_msc->stage = MSC_STAGE_STATUS;
TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t)));
break;
}
break;
TU_ATTR_FALLTHROUGH; // fallthrough to status stage
case MSC_STAGE_DATA:
// Status stage
p_msc->stage = MSC_STAGE_STATUS;
TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) &p_msc->csw, (uint16_t) sizeof(msc_csw_t)));
TU_ASSERT(usbh_edpt_xfer(dev_addr, p_msc->ep_in, (uint8_t*) csw, (uint16_t) sizeof(msc_csw_t)));
break;
case MSC_STAGE_STATUS:
@ -399,10 +400,9 @@ bool msch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const* de
return true;
}
bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) {
msch_interface_t* p_msc = get_itf(dev_addr);
bool msch_set_config(uint8_t daddr, uint8_t itf_num) {
msch_interface_t* p_msc = get_itf(daddr);
TU_ASSERT(p_msc->itf_num == itf_num);
p_msc->configured = true;
//------------- Get Max Lun -------------//
@ -419,11 +419,12 @@ bool msch_set_config(uint8_t dev_addr, uint8_t itf_num) {
.wLength = 1
};
uint8_t* enum_buf = usbh_get_enum_buf();
tuh_xfer_t xfer = {
.daddr = dev_addr,
.daddr = daddr,
.ep_addr = 0,
.setup = &request,
.buffer = _msch_buffer,
.buffer = enum_buf,
.complete_cb = config_get_maxlun_complete,
.user_data = 0
};
@ -436,9 +437,13 @@ static void config_get_maxlun_complete(tuh_xfer_t* xfer) {
uint8_t const daddr = xfer->daddr;
msch_interface_t* p_msc = get_itf(daddr);
// STALL means zero
p_msc->max_lun = (XFER_RESULT_SUCCESS == xfer->result) ? _msch_buffer[0] : 0;
p_msc->max_lun++; // MAX LUN is minus 1 by specs
// MAXLUN's response is minus 1 by specs, STALL means 1
if (XFER_RESULT_SUCCESS == xfer->result) {
uint8_t* enum_buf = usbh_get_enum_buf();
p_msc->max_lun = enum_buf[0] + 1;
} else {
p_msc->max_lun = 1;
}
TU_LOG_DRV(" Max LUN = %u\r\n", p_msc->max_lun);
@ -451,18 +456,19 @@ static void config_get_maxlun_complete(tuh_xfer_t* xfer) {
static bool config_test_unit_ready_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
msc_cbw_t const* cbw = cb_data->cbw;
msc_csw_t const* csw = cb_data->csw;
uint8_t* enum_buf = usbh_get_enum_buf();
if (csw->status == 0) {
// Unit is ready, read its capacity
TU_LOG_DRV("SCSI Read Capacity\r\n");
tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer),
tuh_msc_read_capacity(dev_addr, cbw->lun, (scsi_read_capacity10_resp_t*) (uintptr_t) enum_buf,
config_read_capacity_complete, 0);
} else {
// Note: During enumeration, some device fails Test Unit Ready and require a few retries
// with Request Sense to start working !!
// TODO limit number of retries
TU_LOG_DRV("SCSI Request Sense\r\n");
TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, _msch_buffer, config_request_sense_complete, 0));
TU_ASSERT(tuh_msc_request_sense(dev_addr, cbw->lun, enum_buf, config_request_sense_complete, 0));
}
return true;
@ -480,19 +486,20 @@ static bool config_request_sense_complete(uint8_t dev_addr, tuh_msc_complete_dat
static bool config_read_capacity_complete(uint8_t dev_addr, tuh_msc_complete_data_t const* cb_data) {
msc_cbw_t const* cbw = cb_data->cbw;
msc_csw_t const* csw = cb_data->csw;
TU_ASSERT(csw->status == 0);
msch_interface_t* p_msc = get_itf(dev_addr);
uint8_t* enum_buf = usbh_get_enum_buf();
// Capacity response field: Block size and Last LBA are both Big-Endian
scsi_read_capacity10_resp_t* resp = (scsi_read_capacity10_resp_t*) ((void*) _msch_buffer);
scsi_read_capacity10_resp_t* resp = (scsi_read_capacity10_resp_t*) (uintptr_t) enum_buf;
p_msc->capacity[cbw->lun].block_count = tu_ntohl(resp->last_lba) + 1;
p_msc->capacity[cbw->lun].block_size = tu_ntohl(resp->block_size);
// Mark enumeration is complete
p_msc->mounted = true;
if (tuh_msc_mount_cb) tuh_msc_mount_cb(dev_addr);
if (tuh_msc_mount_cb) {
tuh_msc_mount_cb(dev_addr);
}
// notify usbh that driver enumeration is complete
usbh_driver_set_config_complete(dev_addr, p_msc->itf_num);

7
src/class/msc/msc_host.h
View File

@ -73,10 +73,12 @@ uint32_t tuh_msc_get_block_size(uint8_t dev_addr, uint8_t lun);
// Perform a full SCSI command (cbw, data, csw) in non-blocking manner.
// Complete callback is invoked when SCSI op is complete.
// return true if success, false if there is already pending operation.
// NOTE: buffer must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
bool tuh_msc_scsi_command(uint8_t daddr, msc_cbw_t const* cbw, void* data, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
// Perform SCSI Inquiry command
// Complete callback is invoked when SCSI op is complete.
// NOTE: response must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
bool tuh_msc_inquiry(uint8_t dev_addr, uint8_t lun, scsi_inquiry_resp_t* response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
// Perform SCSI Test Unit Ready command
@ -85,14 +87,17 @@ bool tuh_msc_test_unit_ready(uint8_t dev_addr, uint8_t lun, tuh_msc_complete_cb_
// Perform SCSI Request Sense 10 command
// Complete callback is invoked when SCSI op is complete.
// NOTE: response must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
bool tuh_msc_request_sense(uint8_t dev_addr, uint8_t lun, void *response, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
// Perform SCSI Read 10 command. Read n blocks starting from LBA to buffer
// Complete callback is invoked when SCSI op is complete.
// NOTE: buffer must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
bool tuh_msc_read10(uint8_t dev_addr, uint8_t lun, void * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
// Perform SCSI Write 10 command. Write n blocks starting from LBA to device
// Complete callback is invoked when SCSI op is complete.
// NOTE: buffer must be accessible by USB/DMA controller, aligned correctly and multiple of cache line if enabled
bool tuh_msc_write10(uint8_t dev_addr, uint8_t lun, void const * buffer, uint32_t lba, uint16_t block_count, tuh_msc_complete_cb_t complete_cb, uintptr_t arg);
// Perform SCSI Read Capacity 10 command
@ -116,7 +121,7 @@ TU_ATTR_WEAK void tuh_msc_umount_cb(uint8_t dev_addr);
bool msch_init (void);
bool msch_deinit (void);
bool msch_open (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *desc_itf, uint16_t max_len);
bool msch_set_config (uint8_t dev_addr, uint8_t itf_num);
bool msch_set_config (uint8_t daddr, uint8_t itf_num);
void msch_close (uint8_t dev_addr);
bool msch_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);

21
src/common/tusb_mcu.h
View File

@ -354,9 +354,12 @@
#define TUP_USBIP_DWC2
#define TUP_USBIP_DWC2_ESP32
#define TUP_DCD_ENDPOINT_MAX 7 // only 5 TX FIFO for endpoint IN
#define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif
#define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/
// Disable slave if DMA is enabled
#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
#elif TU_CHECK_MCU(OPT_MCU_ESP32P4)
#define TUP_USBIP_DWC2
#define TUP_USBIP_DWC2_ESP32
@ -364,16 +367,16 @@
#define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep
#define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/
// Disable slave if DMA is enabled
#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT !CFG_TUH_DWC2_DMA_ENABLE
// Enable dcache if DMA is enabled
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT CFG_TUH_DWC2_DMA_ENABLE
#define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 64
#if defined(CFG_TUD_DWC2_DMA_ENABLE) && CFG_TUD_DWC2_DMA_ENABLE == 1
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
#endif
#define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0
#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 0
#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)
#if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421))
#error "MCUs are only supported with CFG_TUH_MAX3421 enabled"

10
src/common/tusb_types.h
View File

@ -44,14 +44,14 @@
union { \
CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \
uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \
};
}
// Declare an endpoint buffer with a type
#define TUD_EPBUF_TYPE_DEF(_name, _type) \
union { \
CFG_TUD_MEM_ALIGN _type _name; \
uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
};
}
//------------- Host DCache declaration -------------//
#define TUH_EPBUF_DCACHE_SIZE(_size) (CFG_TUH_MEM_DCACHE_ENABLE ? \
@ -62,14 +62,14 @@
union { \
CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \
uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \
};
}
// Declare an endpoint buffer with a type
#define TUH_EPBUF_TYPE_DEF(_name, _type) \
#define TUH_EPBUF_TYPE_DEF(_type, _name) \
union { \
CFG_TUH_MEM_ALIGN _type _name; \
uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \
};
}
/*------------------------------------------------------------------*/

6
src/host/hcd.h
View File

@ -103,15 +103,15 @@ typedef struct {
// clean/flush data cache: write cache -> memory.
// Required before an DMA TX transfer to make sure data is in memory
bool hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
bool hcd_dcache_clean(void const* addr, uint32_t data_size);
// invalidate data cache: mark cache as invalid, next read will read from memory
// Required BOTH before and after an DMA RX transfer
bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
bool hcd_dcache_invalidate(void const* addr, uint32_t data_size);
// clean and invalidate data cache
// Required before an DMA transfer where memory is both read/write by DMA
bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size);
//--------------------------------------------------------------------+
// Controller API

182
src/host/usbh.c
View File

@ -65,6 +65,21 @@ TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_is
(void) in_isr;
}
TU_ATTR_WEAK bool hcd_dcache_clean(const void* addr, uint32_t data_size) {
(void) addr; (void) data_size;
return false;
}
TU_ATTR_WEAK bool hcd_dcache_invalidate(const void* addr, uint32_t data_size) {
(void) addr; (void) data_size;
return false;
}
TU_ATTR_WEAK bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
(void) addr; (void) data_size;
return false;
}
//--------------------------------------------------------------------+
// USBH-HCD common data structure
//--------------------------------------------------------------------+
@ -137,65 +152,65 @@ typedef struct {
#endif
static usbh_class_driver_t const usbh_class_drivers[] = {
#if CFG_TUH_CDC
{
.name = DRIVER_NAME("CDC"),
.init = cdch_init,
.deinit = cdch_deinit,
.open = cdch_open,
.set_config = cdch_set_config,
.xfer_cb = cdch_xfer_cb,
.close = cdch_close
},
#endif
#if CFG_TUH_CDC
{
.name = DRIVER_NAME("CDC"),
.init = cdch_init,
.deinit = cdch_deinit,
.open = cdch_open,
.set_config = cdch_set_config,
.xfer_cb = cdch_xfer_cb,
.close = cdch_close
},
#endif
#if CFG_TUH_MSC
{
.name = DRIVER_NAME("MSC"),
.init = msch_init,
.deinit = msch_deinit,
.open = msch_open,
.set_config = msch_set_config,
.xfer_cb = msch_xfer_cb,
.close = msch_close
},
#endif
#if CFG_TUH_MSC
{
.name = DRIVER_NAME("MSC"),
.init = msch_init,
.deinit = msch_deinit,
.open = msch_open,
.set_config = msch_set_config,
.xfer_cb = msch_xfer_cb,
.close = msch_close
},
#endif
#if CFG_TUH_HID
{
.name = DRIVER_NAME("HID"),
.init = hidh_init,
.deinit = hidh_deinit,
.open = hidh_open,
.set_config = hidh_set_config,
.xfer_cb = hidh_xfer_cb,
.close = hidh_close
},
#endif
#if CFG_TUH_HID
{
.name = DRIVER_NAME("HID"),
.init = hidh_init,
.deinit = hidh_deinit,
.open = hidh_open,
.set_config = hidh_set_config,
.xfer_cb = hidh_xfer_cb,
.close = hidh_close
},
#endif
#if CFG_TUH_HUB
{
.name = DRIVER_NAME("HUB"),
.init = hub_init,
.deinit = hub_deinit,
.open = hub_open,
.set_config = hub_set_config,
.xfer_cb = hub_xfer_cb,
.close = hub_close
},
#endif
#if CFG_TUH_HUB
{
.name = DRIVER_NAME("HUB"),
.init = hub_init,
.deinit = hub_deinit,
.open = hub_open,
.set_config = hub_set_config,
.xfer_cb = hub_xfer_cb,
.close = hub_close
},
#endif
#if CFG_TUH_VENDOR
{
.name = DRIVER_NAME("VENDOR"),
.init = cush_init,
.deinit = cush_deinit,
.open = cush_open,
.set_config = cush_set_config,
.xfer_cb = cush_isr,
.close = cush_close
}
#endif
#if CFG_TUH_VENDOR
{
.name = DRIVER_NAME("VENDOR"),
.init = cush_init,
.deinit = cush_deinit,
.open = cush_open,
.set_config = cush_set_config,
.xfer_cb = cush_isr,
.close = cush_close
}
#endif
};
enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
@ -249,14 +264,10 @@ static usbh_device_t _usbh_devices[TOTAL_DEVICES];
OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
static osal_queue_t _usbh_q;
CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN
static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
// Control transfers: since most controllers do not support multiple control transfers
// on multiple devices concurrently and control transfers are not used much except for
// enumeration, we will only execute control transfers one at a time.
CFG_TUH_MEM_SECTION struct {
CFG_TUH_MEM_ALIGN tusb_control_request_t request;
static struct {
uint8_t* buffer;
tuh_xfer_cb_t complete_cb;
uintptr_t user_data;
@ -264,7 +275,14 @@ CFG_TUH_MEM_SECTION struct {
uint8_t daddr;
volatile uint8_t stage;
volatile uint16_t actual_len;
}_ctrl_xfer;
} _ctrl_xfer;
typedef struct {
TUH_EPBUF_TYPE_DEF(tusb_control_request_t, request);
TUH_EPBUF_DEF(ctrl, CFG_TUH_ENUMERATION_BUFSIZE);
} usbh_epbuf_t;
CFG_TUH_MEM_SECTION static usbh_epbuf_t _usbh_epbuf;
//------------- Helper Function -------------//
@ -475,7 +493,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) {
switch (event.event_id) {
case HCD_EVENT_DEVICE_ATTACH:
// due to the shared _usbh_ctrl_buf, we must complete enumerating one device before enumerating another one.
// due to the shared control buffer, we must complete enumerating one device before enumerating another one.
// TODO better to have an separated queue for newly attached devices
if (_dev0.enumerating) {
// Some device can cause multiple duplicated attach events
@ -622,10 +640,10 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
_ctrl_xfer.daddr = daddr;
_ctrl_xfer.actual_len = 0;
_ctrl_xfer.request = (*xfer->setup);
_ctrl_xfer.buffer = xfer->buffer;
_ctrl_xfer.complete_cb = xfer->complete_cb;
_ctrl_xfer.user_data = xfer->user_data;
_usbh_epbuf.request = (*xfer->setup);
}
(void) osal_mutex_unlock(_usbh_mutex);
@ -639,7 +657,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
TU_LOG_BUF_USBH(xfer->setup, 8);
if (xfer->complete_cb) {
TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) );
TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_usbh_epbuf.request) );
}else {
// blocking if complete callback is not provided
// change callback to internal blocking, and result as user argument
@ -649,7 +667,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) {
_ctrl_xfer.user_data = (uintptr_t) &result;
_ctrl_xfer.complete_cb = _control_blocking_complete_cb;
TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) );
TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_usbh_epbuf.request) );
while (result == XFER_RESULT_INVALID) {
// Note: this can be called within an callback ie. part of tuh_task()
@ -681,7 +699,7 @@ static void _control_xfer_complete(uint8_t daddr, xfer_result_t result) {
TU_LOG_USBH("\r\n");
// duplicate xfer since user can execute control transfer within callback
tusb_control_request_t const request = _ctrl_xfer.request;
tusb_control_request_t const request = _usbh_epbuf.request;
tuh_xfer_t xfer_temp = {
.daddr = daddr,
.ep_addr = 0,
@ -704,7 +722,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t
(void) ep_addr;
const uint8_t rhport = usbh_get_rhport(daddr);
tusb_control_request_t const * request = &_ctrl_xfer.request;
tusb_control_request_t const * request = &_usbh_epbuf.request;
if (XFER_RESULT_SUCCESS != result) {
TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %" PRIu32 "\r\n", rhport, daddr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes);
@ -817,7 +835,7 @@ uint8_t usbh_get_rhport(uint8_t dev_addr) {
}
uint8_t *usbh_get_enum_buf(void) {
return _usbh_ctrl_buf;
return _usbh_epbuf.ctrl;
}
void usbh_int_set(bool enabled) {
@ -1279,7 +1297,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu
// Enumeration Process
// is a lengthy process with a series of control transfer to configure
// newly attached device.
// NOTE: due to the shared _usbh_ctrl_buf, we must complete enumerating
// NOTE: due to the shared control buffer, we must complete enumerating
// one device before enumerating another one.
//--------------------------------------------------------------------+
@ -1347,7 +1365,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
case ENUM_HUB_CLEAR_RESET_1: {
hub_port_status_response_t port_status;
memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t));
if (!port_status.status.connection) {
// device unplugged while delaying, nothing else to do
@ -1368,13 +1386,13 @@ static void process_enumeration(tuh_xfer_t* xfer) {
case ENUM_HUB_GET_STATUS_2:
tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS);
TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf,
TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_epbuf.ctrl,
process_enumeration, ENUM_HUB_CLEAR_RESET_2),);
break;
case ENUM_HUB_CLEAR_RESET_2: {
hub_port_status_response_t port_status;
memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t));
// Acknowledge Port Reset Change if Reset Successful
if (port_status.change.reset) {
@ -1392,7 +1410,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
// Get first 8 bytes of device descriptor for Control Endpoint size
TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n");
TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8,
TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_epbuf.ctrl, 8,
process_enumeration, ENUM_SET_ADDR),);
break;
}
@ -1443,13 +1461,13 @@ static void process_enumeration(tuh_xfer_t* xfer) {
// Get full device descriptor
TU_LOG_USBH("Get Device Descriptor\r\n");
TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t),
TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_epbuf.ctrl, sizeof(tusb_desc_device_t),
process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC),);
break;
}
case ENUM_GET_9BYTE_CONFIG_DESC: {
tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl;
usbh_device_t* dev = get_device(daddr);
TU_ASSERT(dev,);
@ -1459,18 +1477,16 @@ static void process_enumeration(tuh_xfer_t* xfer) {
dev->i_product = desc_device->iProduct;
dev->i_serial = desc_device->iSerialNumber;
// if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf);
// Get 9-byte for total length
uint8_t const config_idx = CONFIG_NUM - 1;
TU_LOG_USBH("Get Configuration[0] Descriptor (9 bytes)\r\n");
TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, 9,
TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9,
process_enumeration, ENUM_GET_FULL_CONFIG_DESC),);
break;
}
case ENUM_GET_FULL_CONFIG_DESC: {
uint8_t const* desc_config = _usbh_ctrl_buf;
uint8_t const* desc_config = _usbh_epbuf.ctrl;
// Use offsetof to avoid pointer to the odd/misaligned address
uint16_t const total_len = tu_le16toh(
@ -1482,7 +1498,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
// Get full configuration descriptor
uint8_t const config_idx = CONFIG_NUM - 1;
TU_LOG_USBH("Get Configuration[0] Descriptor\r\n");
TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, total_len,
TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, total_len,
process_enumeration, ENUM_SET_CONFIG),);
break;
}
@ -1500,7 +1516,7 @@ static void process_enumeration(tuh_xfer_t* xfer) {
// Parse configuration & set up drivers
// driver_open() must not make any usb transfer
TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf),);
TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_epbuf.ctrl),);
// Start the Set Configuration process for interfaces (itf = TUSB_INDEX_INVALID_8)
// Since driver can perform control transfer within its set_config, this is done asynchronously.
@ -1561,7 +1577,7 @@ static bool enum_new_device(hcd_event_t* event) {
tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS);
// ENUM_HUB_GET_STATUS
TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf,
TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_epbuf.ctrl,
process_enumeration, ENUM_HUB_CLEAR_RESET_1));
}
#endif // hub
@ -1589,7 +1605,7 @@ static uint8_t get_new_address(bool is_hub) {
}
static bool enum_request_set_addr(void) {
tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl;
// Get new address
uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);

2
src/host/usbh.h
View File

@ -96,8 +96,6 @@ typedef union {
// APPLICATION CALLBACK
//--------------------------------------------------------------------+
//TU_ATTR_WEAK uint8_t tuh_attach_cb (tusb_desc_device_t const *desc_device);
// Invoked when a device is mounted (configured)
TU_ATTR_WEAK void tuh_mount_cb (uint8_t daddr);

8
src/portable/synopsys/dwc2/dcd_dwc2.c
View File

@ -31,8 +31,8 @@
#if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2)
#if !CFG_TUD_DWC2_SLAVE_ENABLE && !CFG_TUH_DWC2_DMA_ENABLE
#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled
#if !(CFG_TUD_DWC2_SLAVE_ENABLE || CFG_TUD_DWC2_DMA_ENABLE)
#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUD_DWC2_DMA_ENABLE to be enabled
#endif
// Debug level for DWC2
@ -615,10 +615,6 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t
return true;
}
void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) {
edpt_disable(rhport, ep_addr, false);
}
void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) {
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
edpt_disable(rhport, ep_addr, true);

28
src/portable/synopsys/dwc2/hcd_dwc2.c
View File

@ -28,6 +28,10 @@
#if CFG_TUH_ENABLED && defined(TUP_USBIP_DWC2)
#if !(CFG_TUH_DWC2_SLAVE_ENABLE || CFG_TUH_DWC2_DMA_ENABLE)
#error DWC2 require either CFG_TUH_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled
#endif
// Debug level for DWC2
#define DWC2_DEBUG 2
@ -132,6 +136,23 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc
return CFG_TUH_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA;
}
#if CFG_TUH_MEM_DCACHE_ENABLE
bool hcd_dcache_clean(const void* addr, uint32_t data_size) {
TU_VERIFY(addr && data_size);
return dwc2_dcache_clean(addr, data_size);
}
bool hcd_dcache_invalidate(const void* addr, uint32_t data_size) {
TU_VERIFY(addr && data_size);
return dwc2_dcache_invalidate(addr, data_size);
}
bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
TU_VERIFY(addr && data_size);
return dwc2_dcache_clean_invalidate(addr, data_size);
}
#endif
// Allocate a channel for new transfer
TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) {
const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2);
@ -555,6 +576,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) {
if (hcchar_bm->ep_dir == TUSB_DIR_IN) {
channel_send_in_token(dwc2, channel);
} else {
hcd_dcache_clean(edpt->buffer, edpt->buflen);
channel->hcchar |= HCCHAR_CHENA;
}
} else {
@ -1119,13 +1141,17 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) {
const uint32_t hcint = channel->hcint;
channel->hcint = hcint; // clear interrupt
bool is_done;
bool is_done = false;
if (is_dma) {
#if CFG_TUH_DWC2_DMA_ENABLE
if (hcchar_bm.ep_dir == TUSB_DIR_OUT) {
is_done = handle_channel_out_dma(dwc2, ch_id, hcint);
} else {
is_done = handle_channel_in_dma(dwc2, ch_id, hcint);
if (is_done && (channel->hcdma > xfer->xferred_bytes)) {
// hcdma is increased by word --> need to align4
hcd_dcache_invalidate((void*) tu_align4(channel->hcdma - xfer->xferred_bytes), xfer->xferred_bytes);
}
}
#endif
} else {

14
src/tusb_option.h
View File

@ -249,12 +249,20 @@
//--------------------------------------------------------------------+
#ifndef CFG_TUD_DWC2_SLAVE_ENABLE
#define CFG_TUD_DWC2_SLAVE_ENABLE 1
#ifndef CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT
#define CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT 1
#endif
#define CFG_TUD_DWC2_SLAVE_ENABLE CFG_TUD_DWC2_SLAVE_ENABLE_DEFAULT
#endif
// Enable DWC2 DMA for device
#ifndef CFG_TUD_DWC2_DMA_ENABLE
#define CFG_TUD_DWC2_DMA_ENABLE 0
#ifndef CFG_TUD_DWC2_DMA_ENABLE_DEFAULT
#define CFG_TUD_DWC2_DMA_ENABLE_DEFAULT 0
#endif
#define CFG_TUD_DWC2_DMA_ENABLE CFG_TUD_DWC2_DMA_ENABLE_DEFAULT
#endif
// Enable DWC2 Slave mode for host
@ -269,7 +277,7 @@
// Enable DWC2 DMA for host
#ifndef CFG_TUH_DWC2_DMA_ENABLE
#ifndef CFG_TUH_DWC2_DMA_ENABLE_DEFAULT
#define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 1
#define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0
#endif
#define CFG_TUH_DWC2_DMA_ENABLE CFG_TUH_DWC2_DMA_ENABLE_DEFAULT

2
test/hil/hil_test.py
View File

@ -549,7 +549,7 @@ def test_board(board):
for f1 in flags_on_list:
f1_str = ""
if f1 != "":
f1_str = '-' + f1.replace(' ', '-')
f1_str = '-f1_' + f1.replace(' ', '_')
for test in test_list:
fw_dir = f'{TINYUSB_ROOT}/cmake-build/cmake-build-{name}{f1_str}/{test}'
if not os.path.exists(fw_dir):

10
test/hil/tinyusb.json
View File

@ -4,7 +4,7 @@
"name": "espressif_p4_function_ev",
"uid": "6055F9F98715",
"build" : {
"flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"]
"flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE CFG_TUH_DWC2_DMA_ENABLE"]
},
"tests": {
"only": ["device/cdc_msc_freertos", "device/hid_composite_freertos", "host/device_info"],
@ -14,7 +14,8 @@
"name": "esptool",
"uid": "4ea4f48f6bc3ee11bbb9d00f9e1b1c54",
"args": "-b 1500000"
}
},
"comment": "Use TS3USB30 mux to test both device and host"
},
{
"name": "espressif_s3_devkitm",
@ -133,7 +134,7 @@
"name": "stm32f723disco",
"uid": "460029001951373031313335",
"build" : {
"flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"]
"flags_on": ["", "CFG_TUH_DWC2_DMA_ENABLE"]
},
"tests": {
"device": true, "host": true, "dual": false,
@ -143,7 +144,8 @@
"name": "jlink",
"uid": "000776606156",
"args": "-device stm32f723ie"
}
},
"comment": "Device port0 FS (slave only), Host port1 HS with DMA"
},
{
"name": "stm32h743nucleo",

2
tools/build.py
View File

@ -90,7 +90,7 @@ def cmake_board(board, toolchain, build_flags_on):
if len(build_flags_on) > 0:
build_flags = ' '.join(f'-D{flag}=1' for flag in build_flags_on)
build_flags = f'-DCFLAGS_CLI="{build_flags}"'
build_dir += '-' + '-'.join(build_flags_on)
build_dir += '-f1_' + '_'.join(build_flags_on)
family = find_family(board)
if family == 'espressif':