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Merge pull request #2883 from hathach/feature/esp32p4_dma_cache_syncronization
[DCD_DWC2][ESP32P4][HS] Added cache synchronization (cont)
This commit is contained in:
Ha Thach
GitHub
commit
2571889061
@ -15,6 +15,13 @@ list(APPEND compile_definitions
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BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED}
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)
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if (target STREQUAL esp32p4)
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# P4 change alignment to 64 (DCache line size) for possible DMA configuration
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list(APPEND compile_definitions
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CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\)
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)
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endif ()
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list(APPEND srcs
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# common
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${tusb_src}/tusb.c
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@ -68,6 +75,7 @@ endif()
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idf_component_register(SRCS ${srcs}
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INCLUDE_DIRS ${tusb_src}
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REQUIRES src
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PRIV_REQUIRES esp_mm
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)
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target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions})
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@ -361,6 +361,18 @@
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#define TUP_USBIP_DWC2_ESP32
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#define TUP_RHPORT_HIGHSPEED 1 // port0 FS, port1 HS
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#define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep
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#if defined(CFG_TUD_DWC2_DMA_ENABLE) && CFG_TUD_DWC2_DMA_ENABLE == 1
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#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1
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#endif
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#if defined(CFG_TUH_DWC2_DMA_ENABLE) && CFG_TUH_DWC2_DMA_ENABLE == 1
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#define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1
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#endif
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#define CFG_TUD_MEM_DCACHE_LINE_SIZE 64
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#define CFG_TUH_MEM_DCACHE_LINE_SIZE 64
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#define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif
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#elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2)
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@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) {
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// clean/flush data cache: write cache -> memory.
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// Required before an DMA TX transfer to make sure data is in memory
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void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
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void dcd_dcache_clean(const void* addr, uint32_t data_size);
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// invalidate data cache: mark cache as invalid, next read will read from memory
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// Required BOTH before and after an DMA RX transfer
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void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
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void dcd_dcache_invalidate(const void* addr, uint32_t data_size);
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// clean and invalidate data cache
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// Required before an DMA transfer where memory is both read/write by DMA
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void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK;
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void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size);
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//--------------------------------------------------------------------+
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// Controller API
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@ -46,9 +46,7 @@
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// Weak stubs: invoked if no strong implementation is available
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//--------------------------------------------------------------------+
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TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) {
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(void) rhport;
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(void) eventid;
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(void) in_isr;
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(void) rhport; (void) eventid; (void) in_isr;
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}
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TU_ATTR_WEAK void tud_sof_cb(uint32_t frame_count) {
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@ -82,9 +80,7 @@ TU_ATTR_WEAK void tud_resume_cb(void) {
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}
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TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const* request) {
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(void) rhport;
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(void) stage;
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(void) request;
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(void) rhport; (void) stage; (void) request;
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return false;
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}
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@ -101,6 +97,18 @@ TU_ATTR_WEAK void dcd_disconnect(uint8_t rhport) {
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(void) rhport;
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}
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TU_ATTR_WEAK void dcd_dcache_clean(const void* addr, uint32_t data_size) {
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(void) addr; (void) data_size;
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}
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TU_ATTR_WEAK void dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
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(void) addr; (void) data_size;
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}
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TU_ATTR_WEAK void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
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(void) addr; (void) data_size;
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}
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//--------------------------------------------------------------------+
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// Device Data
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//--------------------------------------------------------------------+
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@ -46,9 +46,6 @@
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM
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//--------------------------------------------------------------------+
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static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2];
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typedef struct {
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uint8_t* buffer;
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tu_fifo_t* ff;
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@ -60,19 +57,49 @@ typedef struct {
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static xfer_ctl_t xfer_status[DWC2_EP_MAX][2];
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#define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir])
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// EP0 transfers are limited to 1 packet - larger sizes has to be split
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static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
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static uint16_t _dfifo_top; // top free location in DFIFO in words
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typedef struct {
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CFG_TUD_MEM_ALIGN union {
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uint32_t setup_packet[2];
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#if CFG_TUD_MEM_DCACHE_ENABLE
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uint8_t setup_packet_cache_padding[CFG_TUD_MEM_DCACHE_LINE_SIZE];
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#endif
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};
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// Number of IN endpoints active
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static uint8_t _allocated_ep_in_count;
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// EP0 transfers are limited to 1 packet - larger sizes has to be split
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uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type
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uint16_t dfifo_top; // top free location in DFIFO in words
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// SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
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static bool _sof_en;
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// Number of IN endpoints active
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uint8_t allocated_epin_count;
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// SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by
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bool sof_en;
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} dcd_data_t;
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CFG_TUD_MEM_SECTION static dcd_data_t _dcd_data;
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//--------------------------------------------------------------------
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// DMA
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//--------------------------------------------------------------------
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#if CFG_TUD_MEM_DCACHE_ENABLE
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void dcd_dcache_clean(const void* addr, uint32_t data_size) {
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if (addr && data_size) {
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dwc2_dcache_clean(addr, data_size);
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}
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}
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void dcd_dcache_invalidate(const void* addr, uint32_t data_size) {
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if (addr && data_size) {
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dwc2_dcache_invalidate(addr, data_size);
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}
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}
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void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
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if (addr && data_size) {
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dwc2_dcache_clean_invalidate(addr, data_size);
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}
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}
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#endif
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TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) {
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(void) dwc2;
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@ -91,7 +118,7 @@ static void dma_setup_prepare(uint8_t rhport) {
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// Receive only 1 packet
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dwc2->epout[0].doeptsiz = (1 << DOEPTSIZ_STUPCNT_Pos) | (1 << DOEPTSIZ_PKTCNT_Pos) | (8 << DOEPTSIZ_XFRSIZ_Pos);
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dwc2->epout[0].doepdma = (uintptr_t)_setup_packet;
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dwc2->epout[0].doepdma = (uintptr_t) _dcd_data.setup_packet;
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dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP;
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}
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@ -149,27 +176,27 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_device_grxfsiz(uint16_t larges
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static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport];
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uint8_t const ep_count = dwc2_controller->ep_count;
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uint8_t const epnum = tu_edpt_number(ep_addr);
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uint8_t const dir = tu_edpt_dir(ep_addr);
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const uint8_t ep_count = dwc2_controller->ep_count;
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const uint8_t epnum = tu_edpt_number(ep_addr);
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const uint8_t dir = tu_edpt_dir(ep_addr);
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TU_ASSERT(epnum < ep_count);
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uint16_t fifo_size = tu_div_ceil(packet_size, 4);
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if (dir == TUSB_DIR_OUT) {
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// Calculate required size of RX FIFO
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uint16_t const new_sz = calc_device_grxfsiz(4 * fifo_size, ep_count);
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const uint16_t new_sz = calc_device_grxfsiz(4 * fifo_size, ep_count);
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// If size_rx needs to be extended check if there is enough free space
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if (dwc2->grxfsiz < new_sz) {
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TU_ASSERT(new_sz <= _dfifo_top);
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TU_ASSERT(new_sz <= _dcd_data.dfifo_top);
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dwc2->grxfsiz = new_sz; // Enlarge RX FIFO
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}
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} else {
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// Check IN endpoints concurrently active limit
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if(_dwc2_controller->ep_in_count) {
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TU_ASSERT(_allocated_ep_in_count < _dwc2_controller->ep_in_count);
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_allocated_ep_in_count++;
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TU_ASSERT(_dcd_data.allocated_epin_count < _dwc2_controller->ep_in_count);
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_dcd_data.allocated_epin_count++;
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}
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// If The TXFELVL is configured as half empty, the fifo must be twice the max_size.
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@ -178,16 +205,16 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) {
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}
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// Check if free space is available
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TU_ASSERT(_dfifo_top >= fifo_size + dwc2->grxfsiz);
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_dfifo_top -= fifo_size;
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TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, _dfifo_top);
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TU_ASSERT(_dcd_data.dfifo_top >= fifo_size + dwc2->grxfsiz);
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_dcd_data.dfifo_top -= fifo_size;
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// TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, dfifo_top);
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// Both TXFD and TXSA are in unit of 32-bit words.
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if (epnum == 0) {
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dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dfifo_top;
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dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dcd_data.dfifo_top;
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} else {
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// DIEPTXF starts at FIFO #1.
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dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dfifo_top;
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dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dcd_data.dfifo_top;
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}
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}
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@ -201,11 +228,11 @@ static void dfifo_device_init(uint8_t rhport) {
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// Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction
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const bool is_dma = dma_device_enabled(dwc2);
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_dfifo_top = dwc2_controller->ep_fifo_size/4;
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_dcd_data.dfifo_top = dwc2_controller->ep_fifo_size/4;
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if (is_dma) {
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_dfifo_top -= 2 * dwc2_controller->ep_count;
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_dcd_data.dfifo_top -= 2 * dwc2_controller->ep_count;
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}
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dwc2->gdfifocfg = (_dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dfifo_top;
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dwc2->gdfifocfg = (_dcd_data.dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dcd_data.dfifo_top;
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// Allocate FIFO for EP0 IN
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dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE);
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@ -215,7 +242,7 @@ static void dfifo_device_init(uint8_t rhport) {
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//--------------------------------------------------------------------
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// Endpoint
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//--------------------------------------------------------------------
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static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) {
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static void edpt_activate(uint8_t rhport, const tusb_desc_endpoint_t* p_endpoint_desc) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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const uint8_t epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress);
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const uint8_t dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress);
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@ -306,8 +333,8 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
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// EP0 is limited to one packet per xfer
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if (epnum == 0) {
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total_bytes = tu_min16(ep0_pending[dir], xfer->max_size);
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ep0_pending[dir] -= total_bytes;
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total_bytes = tu_min16(_dcd_data.ep0_pending[dir], xfer->max_size);
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_dcd_data.ep0_pending[dir] -= total_bytes;
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num_packets = 1;
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} else {
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total_bytes = xfer->total_len;
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@ -348,14 +375,18 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin
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const bool is_dma = dma_device_enabled(dwc2);
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if(is_dma) {
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if (dir == TUSB_DIR_IN && total_bytes != 0) {
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dcd_dcache_clean(xfer->buffer, total_bytes);
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}
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dep->diepdma = (uintptr_t) xfer->buffer;
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}
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dep->diepctl = depctl.value; // enable endpoint
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} else {
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dep->diepctl = depctl.value; // enable endpoint
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dep->diepctl = depctl.value; // enable endpoint
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// Slave: enable tx fifo empty interrupt only if there is data. Note must after depctl enable
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if (!is_dma && dir == TUSB_DIR_IN && total_bytes != 0) {
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dwc2->diepempmsk |= (1 << epnum);
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// Enable tx fifo empty interrupt only if there is data. Note must after depctl enable
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if (dir == TUSB_DIR_IN && total_bytes != 0) {
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dwc2->diepempmsk |= (1 << epnum);
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}
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}
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}
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@ -366,6 +397,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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(void) rh_init;
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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tu_memclr(&_dcd_data, sizeof(_dcd_data));
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// Core Initialization
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const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE);
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const bool is_dma = dma_device_enabled(dwc2);
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@ -483,7 +516,7 @@ void dcd_sof_enable(uint8_t rhport, bool en) {
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(void) rhport;
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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_sof_en = en;
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_dcd_data.sof_en = en;
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if (en) {
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dwc2->gintsts = GINTSTS_SOF;
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@ -508,7 +541,7 @@ void dcd_edpt_close_all(uint8_t rhport) {
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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uint8_t const ep_count = _dwc2_controller[rhport].ep_count;
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_allocated_ep_in_count = 1;
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_dcd_data.allocated_epin_count = 1;
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// Disable non-control interrupt
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dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos);
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@ -552,7 +585,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to
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// EP0 can only handle one packet
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if (epnum == 0) {
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ep0_pending[dir] = total_bytes;
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_dcd_data.ep0_pending[dir] = total_bytes;
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}
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// Schedule packets to be sent within interrupt
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@ -618,8 +651,8 @@ static void handle_bus_reset(uint8_t rhport) {
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tu_memclr(xfer_status, sizeof(xfer_status));
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_sof_en = false;
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_allocated_ep_in_count = 1;
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_dcd_data.sof_en = false;
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_dcd_data.allocated_epin_count = 1;
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// 1. NAK for all OUT endpoints
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for (uint8_t n = 0; n < ep_count; n++) {
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@ -723,8 +756,8 @@ static void handle_rxflvl_irq(uint8_t rhport) {
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case GRXSTS_PKTSTS_SETUP_RX:
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// Setup packet received
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// We can receive up to three setup packets in succession, but only the last one is valid.
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_setup_packet[0] = (*rx_fifo);
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_setup_packet[1] = (*rx_fifo);
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_dcd_data.setup_packet[0] = (*rx_fifo);
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_dcd_data.setup_packet[1] = (*rx_fifo);
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break;
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case GRXSTS_PKTSTS_SETUP_DONE:
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@ -751,8 +784,8 @@ static void handle_rxflvl_irq(uint8_t rhport) {
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if (byte_count < xfer->max_size) {
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xfer->total_len -= epout->tsiz_bm.xfer_size;
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if (epnum == 0) {
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xfer->total_len -= ep0_pending[TUSB_DIR_OUT];
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ep0_pending[TUSB_DIR_OUT] = 0;
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xfer->total_len -= _dcd_data.ep0_pending[TUSB_DIR_OUT];
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_dcd_data.ep0_pending[TUSB_DIR_OUT] = 0;
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}
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}
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}
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@ -771,7 +804,7 @@ static void handle_rxflvl_irq(uint8_t rhport) {
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static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) {
|
||||
if (doepint_bm.setup_phase_done) {
|
||||
dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
|
||||
dcd_event_setup_received(rhport, (uint8_t*) _dcd_data.setup_packet, true);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -783,7 +816,7 @@ static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doe
|
||||
if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) {
|
||||
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
|
||||
|
||||
if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
|
||||
if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_OUT]) {
|
||||
// EP0 can only handle one packet, Schedule another packet to be received.
|
||||
edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT);
|
||||
} else {
|
||||
@ -799,7 +832,7 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep
|
||||
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
|
||||
|
||||
if (diepint_bm.xfer_complete) {
|
||||
if ((epnum == 0) && ep0_pending[TUSB_DIR_IN]) {
|
||||
if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_IN]) {
|
||||
// EP0 can only handle one packet. Schedule another packet to be transmitted.
|
||||
edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN);
|
||||
} else {
|
||||
@ -847,7 +880,8 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
|
||||
|
||||
if (doepint_bm.setup_phase_done) {
|
||||
dma_setup_prepare(rhport);
|
||||
dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true);
|
||||
dcd_dcache_invalidate(_dcd_data.setup_packet, 8);
|
||||
dcd_event_setup_received(rhport, (uint8_t*) _dcd_data.setup_packet, true);
|
||||
return;
|
||||
}
|
||||
|
||||
@ -856,7 +890,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
|
||||
// only handle data skip if it is setup or status related
|
||||
// Normal OUT transfer complete
|
||||
if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) {
|
||||
if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) {
|
||||
if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_OUT]) {
|
||||
// EP0 can only handle one packet Schedule another packet to be received.
|
||||
edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT);
|
||||
} else {
|
||||
@ -873,6 +907,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi
|
||||
dma_setup_prepare(rhport);
|
||||
}
|
||||
|
||||
dcd_dcache_invalidate(xfer->buffer, xfer->total_len);
|
||||
dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
}
|
||||
@ -883,7 +918,7 @@ static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepin
|
||||
xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN);
|
||||
|
||||
if (diepint_bm.xfer_complete) {
|
||||
if ((epnum == 0) && ep0_pending[TUSB_DIR_IN]) {
|
||||
if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_IN]) {
|
||||
// EP0 can only handle one packet. Schedule another packet to be transmitted.
|
||||
edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN);
|
||||
} else {
|
||||
@ -983,7 +1018,7 @@ void dcd_int_handler(uint8_t rhport) {
|
||||
|
||||
if (gintsts & GINTSTS_OTGINT) {
|
||||
// OTG INT bit is read-only
|
||||
uint32_t const otg_int = dwc2->gotgint;
|
||||
const uint32_t otg_int = dwc2->gotgint;
|
||||
|
||||
if (otg_int & GOTGINT_SEDET) {
|
||||
dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true);
|
||||
@ -997,7 +1032,7 @@ void dcd_int_handler(uint8_t rhport) {
|
||||
const uint32_t frame = (dwc2->dsts & DSTS_FNSOF) >> DSTS_FNSOF_Pos;
|
||||
|
||||
// Disable SOF interrupt if SOF was not explicitly enabled since SOF was used for remote wakeup detection
|
||||
if (!_sof_en) {
|
||||
if (!_dcd_data.sof_en) {
|
||||
dwc2->gintmsk &= ~GINTMSK_SOFM;
|
||||
}
|
||||
|
||||
|
||||
@ -229,6 +229,8 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) {
|
||||
dwc2->gotgint = 0xFFFFFFFFU;
|
||||
dwc2->gintmsk = 0;
|
||||
|
||||
TU_LOG(DWC2_COMMON_DEBUG, "DMA = %u\r\n", is_dma);
|
||||
|
||||
if (is_dma) {
|
||||
// DMA seems to be only settable after a core reset, and not possible to switch on-the-fly
|
||||
dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2;
|
||||
|
||||
@ -111,6 +111,47 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint
|
||||
// maybe usb_utmi_hal_disable()
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Data Cache
|
||||
//--------------------------------------------------------------------+
|
||||
#if CFG_TUD_DWC2_DMA_ENABLE || CFG_TUH_DWC2_DMA_ENABLE
|
||||
#if defined(SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE) && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
|
||||
#include "hal/cache_hal.h"
|
||||
#include "esp_cache.h"
|
||||
|
||||
#if CFG_TUD_MEM_DCACHE_LINE_SIZE != CONFIG_CACHE_L1_CACHE_LINE_SIZE || \
|
||||
CFG_TUH_MEM_DCACHE_LINE_SIZE != CONFIG_CACHE_L1_CACHE_LINE_SIZE
|
||||
#error "CFG_TUD/TUH_MEM_DCACHE_LINE_SIZE must match CONFIG_CACHE_L1_CACHE_LINE_SIZE"
|
||||
#endif
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) {
|
||||
if (size & (CONFIG_CACHE_L1_CACHE_LINE_SIZE-1)) {
|
||||
size = (size & ~(CONFIG_CACHE_L1_CACHE_LINE_SIZE-1)) + CONFIG_CACHE_L1_CACHE_LINE_SIZE;
|
||||
}
|
||||
return size;
|
||||
}
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean(const void* addr, uint32_t data_size) {
|
||||
const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M;
|
||||
data_size = round_up_to_cache_line_size(data_size);
|
||||
assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag));
|
||||
}
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_invalidate(const void* addr, uint32_t data_size) {
|
||||
const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C;
|
||||
data_size = round_up_to_cache_line_size(data_size);
|
||||
assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag));
|
||||
}
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean_invalidate(const void* addr, uint32_t data_size) {
|
||||
const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C;
|
||||
data_size = round_up_to_cache_line_size(data_size);
|
||||
assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag));
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -266,6 +266,7 @@
|
||||
#ifndef CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT
|
||||
#define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT 1
|
||||
#endif
|
||||
|
||||
#define CFG_TUH_DWC2_SLAVE_ENABLE CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT
|
||||
#endif
|
||||
|
||||
@ -274,6 +275,7 @@
|
||||
#ifndef CFG_TUH_DWC2_DMA_ENABLE_DEFAULT
|
||||
#define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 1
|
||||
#endif
|
||||
|
||||
#define CFG_TUH_DWC2_DMA_ENABLE CFG_TUH_DWC2_DMA_ENABLE_DEFAULT
|
||||
#endif
|
||||
|
||||
@ -422,6 +424,18 @@
|
||||
#define CFG_TUD_MEM_ALIGN CFG_TUSB_MEM_ALIGN
|
||||
#endif
|
||||
|
||||
#ifndef CFG_TUD_MEM_DCACHE_ENABLE
|
||||
#ifndef CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT
|
||||
#define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 0
|
||||
#endif
|
||||
|
||||
#define CFG_TUD_MEM_DCACHE_ENABLE CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT
|
||||
#endif
|
||||
|
||||
#ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE
|
||||
#define CFG_TUD_MEM_DCACHE_LINE_SIZE 32
|
||||
#endif
|
||||
|
||||
#ifndef CFG_TUD_ENDPOINT0_SIZE
|
||||
#define CFG_TUD_ENDPOINT0_SIZE 64
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user