mirror of
https://github.com/hathach/tinyusb.git
synced 2025-03-25 10:43:44 +00:00
refractor qhd_xfer_error_isr (omit xfer_type para)
add accumulated total xferred byte for an endpoint until transfer with IOC set - control xfer will have length of data phase in usbh_xfer_isr callback
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@ -209,11 +209,12 @@ void test_bulk_xfer_complete_isr(void)
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ehci_qtd_t* p_head = p_qhd_bulk->p_qtd_list_head;
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ehci_qtd_t* p_tail = p_qhd_bulk->p_qtd_list_tail;
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usbh_xfer_isr_Expect(pipe_hdl_bulk, TUSB_CLASS_MSC, TUSB_EVENT_XFER_COMPLETE, sizeof(data2));
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usbh_xfer_isr_Expect(pipe_hdl_bulk, TUSB_CLASS_MSC, TUSB_EVENT_XFER_COMPLETE, sizeof(data2)+sizeof(xfer_data));
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//------------- Code Under Test -------------//
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ehci_controller_run(hostid);
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TEST_ASSERT_EQUAL(0, p_qhd_bulk->total_xferred_bytes);
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TEST_ASSERT_TRUE(p_qhd_bulk->qtd_overlay.next.terminate);
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TEST_ASSERT_FALSE(p_head->used);
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TEST_ASSERT_FALSE(p_tail->used);
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@ -155,6 +155,7 @@ void test_control_addr0_xfer_get_check_qhd_qtd_mapping(void)
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p_data = &ehci_data.addr0_qtd[1];
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p_status = &ehci_data.addr0_qtd[2];
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TEST_ASSERT_EQUAL(0 , p_qhd->total_xferred_bytes);
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TEST_ASSERT_EQUAL_HEX( p_setup, p_qhd->qtd_overlay.next.address );
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TEST_ASSERT_EQUAL_HEX( p_setup , p_qhd->p_qtd_list_head);
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TEST_ASSERT_EQUAL_HEX( p_data , p_setup->next.address);
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@ -227,11 +228,12 @@ void test_control_xfer_complete_isr(void)
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{
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TEST_ASSERT_STATUS( hcd_pipe_control_xfer(dev_addr, &request_get_dev_desc, xfer_data) );
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usbh_xfer_isr_Expect(((pipe_handle_t){.dev_addr = dev_addr}), 0, TUSB_EVENT_XFER_COMPLETE, 0);
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usbh_xfer_isr_Expect(((pipe_handle_t){.dev_addr = dev_addr}), 0, TUSB_EVENT_XFER_COMPLETE, 18);
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//------------- Code Under TEST -------------//
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ehci_controller_run(hostid);
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TEST_ASSERT_EQUAL(0, p_control_qhd->total_xferred_bytes);
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TEST_ASSERT_NULL(p_control_qhd->p_qtd_list_head);
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TEST_ASSERT_NULL(p_control_qhd->p_qtd_list_tail);
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@ -249,6 +251,8 @@ void test_control_xfer_error_isr(void)
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//------------- Code Under TEST -------------//
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ehci_controller_run_error(hostid);
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TEST_ASSERT_EQUAL(0, p_control_qhd->total_xferred_bytes);
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}
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void test_control_xfer_error_stall(void)
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@ -259,4 +263,6 @@ void test_control_xfer_error_stall(void)
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//------------- Code Under TEST -------------//
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ehci_controller_run_stall(hostid);
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TEST_ASSERT_EQUAL(0, p_control_qhd->total_xferred_bytes);
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}
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@ -201,7 +201,7 @@ void test_interrupt_xfer_complete_isr_interval_less_than_1ms(void)
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TEST_ASSERT_STATUS( hcd_pipe_xfer(pipe_hdl_interrupt, data2, sizeof(data2), true) );
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usbh_xfer_isr_Expect(pipe_hdl_interrupt, TUSB_CLASS_HID, TUSB_EVENT_XFER_COMPLETE, sizeof(data2));
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usbh_xfer_isr_Expect(pipe_hdl_interrupt, TUSB_CLASS_HID, TUSB_EVENT_XFER_COMPLETE, sizeof(xfer_data)+sizeof(data2));
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ehci_qtd_t* p_head = p_qhd_interrupt->p_qtd_list_head;
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ehci_qtd_t* p_tail = p_qhd_interrupt->p_qtd_list_tail;
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@ -209,6 +209,7 @@ void test_interrupt_xfer_complete_isr_interval_less_than_1ms(void)
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//------------- Code Under Test -------------//
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ehci_controller_run(hostid);
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TEST_ASSERT_EQUAL(0, p_qhd_interrupt->total_xferred_bytes);
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check_qhd_after_complete(p_qhd_interrupt);
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TEST_ASSERT_FALSE(p_head->used);
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TEST_ASSERT_FALSE(p_tail->used);
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@ -230,6 +231,7 @@ void test_interrupt_xfer_complete_isr_interval_2ms(void)
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//------------- Code Under Test -------------//
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ehci_controller_run(hostid);
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TEST_ASSERT_EQUAL(0, p_qhd_interrupt->total_xferred_bytes);
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check_qhd_after_complete(p_qhd_2ms);
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TEST_ASSERT_FALSE(p_head->used);
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TEST_ASSERT_FALSE(p_tail->used);
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@ -244,6 +246,8 @@ void test_interrupt_xfer_error_isr(void)
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//------------- Code Under TEST -------------//
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ehci_controller_run_error(hostid);
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TEST_ASSERT_EQUAL(0, p_qhd_interrupt->total_xferred_bytes);
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}
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void test_interrupt_xfer_error_stall(void)
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@ -254,5 +258,7 @@ void test_interrupt_xfer_error_stall(void)
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//------------- Code Under TEST -------------//
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ehci_controller_run_stall(hostid);
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TEST_ASSERT_EQUAL(0, p_qhd_interrupt->total_xferred_bytes);
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}
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@ -517,23 +517,29 @@ static void port_connect_status_change_isr(uint8_t hostid)
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static void qhd_xfer_complete_isr(ehci_qhd_t * p_qhd)
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{
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uint8_t max_loop = 0;
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tusb_xfer_type_t const xfer_type = qhd_get_xfer_type(p_qhd);
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// free all TDs from the head td to the first active TD
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while(p_qhd->p_qtd_list_head != NULL && !p_qhd->p_qtd_list_head->active)
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while(p_qhd->p_qtd_list_head != NULL && !p_qhd->p_qtd_list_head->active
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&& max_loop < EHCI_MAX_QTD)
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{
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// TD need to be freed and removed from qhd, before invoking callback
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bool is_ioc = (p_qhd->p_qtd_list_head->int_on_complete != 0);
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uint16_t actual_bytes_xferred = p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes;
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p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes;
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p_qhd->p_qtd_list_head->used = 0; // free QTD
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qtd_remove_1st_from_qhd(p_qhd);
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if (is_ioc) // end of request
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{
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{ // call USBH callback
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usbh_xfer_isr( qhd_create_pipe_handle(p_qhd, xfer_type),
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p_qhd->class_code, TUSB_EVENT_XFER_COMPLETE, actual_bytes_xferred); // call USBH callback
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p_qhd->class_code, TUSB_EVENT_XFER_COMPLETE,
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p_qhd->total_xferred_bytes - (xfer_type == TUSB_XFER_CONTROL ? 8 : 0) ); // subtract setup packet size if control,
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p_qhd->total_xferred_bytes = 0;
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}
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max_loop++;
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}
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}
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@ -591,28 +597,35 @@ static void period_list_xfer_complete_isr(uint8_t hostid, uint8_t interval_ms)
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}
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#endif
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static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd, tusb_xfer_type_t xfer_type)
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static void qhd_xfer_error_isr(ehci_qhd_t * p_qhd)
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{
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if ( (p_qhd->device_address != 0 && p_qhd->qtd_overlay.halted) || // addr0 cannot be protocol STALL
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p_qhd->qtd_overlay.buffer_err ||p_qhd->qtd_overlay.babble_err || p_qhd->qtd_overlay.xact_err )
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//p_qhd->qtd_overlay.non_hs_period_missed_uframe || p_qhd->qtd_overlay.pingstate_err TODO split transaction error
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{
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// current qhd has error in transaction
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{ // current qhd has error in transaction
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uint16_t total_xferred_bytes;
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tusb_xfer_type_t const xfer_type = qhd_get_xfer_type(p_qhd);
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tusb_event_t error_event;
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// no error bits are set, endpoint is halted due to STALL
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error_event = ( !(p_qhd->qtd_overlay.buffer_err || p_qhd->qtd_overlay.babble_err ||
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p_qhd->qtd_overlay.xact_err) ) ? TUSB_EVENT_XFER_STALLED : TUSB_EVENT_XFER_ERROR;
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uint16_t actual_bytes_xferred = p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes;
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p_qhd->total_xferred_bytes += p_qhd->p_qtd_list_head->expected_bytes - p_qhd->p_qtd_list_head->total_bytes;
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hal_debugger_breakpoint();
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p_qhd->p_qtd_list_head->used = 0; // free QTD
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qtd_remove_1st_from_qhd(p_qhd);
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// subtract setup size if it is control xfer
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total_xferred_bytes = p_qhd->total_xferred_bytes - (xfer_type == TUSB_XFER_CONTROL ? min8_of(8, p_qhd->total_xferred_bytes) : 0);
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// call USBH callback
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usbh_xfer_isr( qhd_create_pipe_handle(p_qhd, xfer_type),
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p_qhd->class_code, error_event, actual_bytes_xferred); // call USBH callback
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p_qhd->class_code, error_event,
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total_xferred_bytes);
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p_qhd->total_xferred_bytes = 0;
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}
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}
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@ -624,8 +637,7 @@ static void xfer_error_isr(uint8_t hostid)
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ehci_qhd_t *p_qhd = async_head;
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do
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{
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qhd_xfer_error_isr( p_qhd,
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p_qhd->endpoint_number != 0 ? TUSB_XFER_BULK : TUSB_XFER_CONTROL);
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qhd_xfer_error_isr( p_qhd );
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p_qhd = qhd_next(p_qhd);
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max_loop++;
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}while(p_qhd != async_head && max_loop < EHCI_MAX_QHD); // async list traversal, stop if loop around
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@ -647,7 +659,7 @@ static void xfer_error_isr(uint8_t hostid)
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case EHCI_QUEUE_ELEMENT_QHD:
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{
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ehci_qhd_t *p_qhd_int = (ehci_qhd_t *) align32(next_item.address);
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qhd_xfer_error_isr(p_qhd_int, TUSB_XFER_INTERRUPT);
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qhd_xfer_error_isr(p_qhd_int);
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}
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break;
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@ -199,8 +199,9 @@ typedef struct {
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uint8_t pid_non_control;
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uint8_t class_code;
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uint16_t total_xferred_bytes; // number of bytes xferred until a qtd with ioc bit set
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uint8_t interval_ms; // polling interval in frames (or milisecond)
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uint8_t reserved[3];
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uint8_t reserved;
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ehci_qtd_t *p_qtd_list_head; // head of the scheduled TD list
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ehci_qtd_t *p_qtd_list_tail; // tail of the scheduled TD list
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