mirror/tinyusb
1
0
Fork 0
mirror of https://github.com/hathach/tinyusb.git synced 2025-02-21 21:41:09 +00:00
Code Issues Packages Projects Releases Wiki Activity

dcd: same70: trim trailling spaces

Browse Source 
Signed-off-by: Rafael Silva <perigoso@riseup.net>
This commit is contained in:
Rafael Silva 2021-06-11 21:03:36 +01:00
parent 28875c431b
commit 2196991df3
1 changed files with 54 additions and 54 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

108
src/portable/microchip/same70/dcd_same70.c
View File

@ -1,4 +1,4 @@
/*
/*
* The MIT License (MIT)
*
* Copyright (c) 2018, hathach (tinyusb.org)
@ -137,7 +137,7 @@ void dcd_set_address (uint8_t rhport, uint8_t dev_addr)
(void) dev_addr;
// DCD can only set address after status for this request is complete
// do it at dcd_edpt0_status_complete()
// Response with zlp status
dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
}
@ -234,7 +234,7 @@ static void dcd_ep_handler(uint8_t ep_ix)
uint8_t *ptr = EP_GET_FIFO_PTR(0,8);
dcd_event_setup_received(0, ptr, true);
}
// Acknowledge the interrupt
// Acknowledge the interrupt
USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_CTRL_RXSTPIC;
}
if (int_status & USBHS_DEVEPTISR_RXOUTI)
@ -251,34 +251,34 @@ static void dcd_ep_handler(uint8_t ep_ix)
}
xfer->queued_len = (uint16_t)(xfer->queued_len + count);
}
// Acknowledge the interrupt
// Acknowledge the interrupt
USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_RXOUTIC;
if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
{
// RX COMPLETE
// RX COMPLETE
dcd_event_xfer_complete(0, 0, xfer->queued_len, XFER_RESULT_SUCCESS, true);
// Disable the interrupt
// Disable the interrupt
USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_RXOUTEC;
// Though the host could still send, we don't know.
}
}
if (int_status & USBHS_DEVEPTISR_TXINI)
{
// Disable the interrupt
// Disable the interrupt
USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_TXINEC;
xfer_ctl_t * xfer = &xfer_status[EP_MAX];
if ((xfer->total_len != xfer->queued_len))
{
// TX not complete
// TX not complete
dcd_transmit_packet(xfer, 0);
} else {
// TX complete
// TX complete
dcd_event_xfer_complete(0, 0x80 + 0, xfer->total_len, XFER_RESULT_SUCCESS, true);
}
}
} else {
if (int_status & USBHS_DEVEPTISR_RXOUTI)
{
{
xfer_ctl_t *xfer = &xfer_status[ep_ix];
if (count)
{
@ -291,27 +291,27 @@ static void dcd_ep_handler(uint8_t ep_ix)
}
xfer->queued_len = (uint16_t)(xfer->queued_len + count);
}
// Acknowledge the interrupt
// Acknowledge the interrupt
USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_RXOUTIC;
// Clear the FIFO control flag to receive more data.
USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
if ((count < xfer->max_packet_size) || (xfer->queued_len == xfer->total_len))
{
// RX COMPLETE
// RX COMPLETE
dcd_event_xfer_complete(0, ep_ix, xfer->queued_len, XFER_RESULT_SUCCESS, true);
// Disable the interrupt
// Disable the interrupt
USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_RXOUTEC;
// Though the host could still send, we don't know.
}
}
if (int_status & USBHS_DEVEPTISR_TXINI)
{
// Acknowledge the interrupt
// Acknowledge the interrupt
USBHS->USBHS_DEVEPTICR[ep_ix] = USBHS_DEVEPTICR_TXINIC;
xfer_ctl_t * xfer = &xfer_status[ep_ix];;
if ((xfer->total_len != xfer->queued_len))
{
// TX not complete
// TX not complete
dcd_transmit_packet(xfer, ep_ix);
} else {
// TX complete
@ -331,7 +331,7 @@ static void dcd_dma_handler(uint8_t ep_ix)
}
// Disable DMA interrupt
USBHS->USBHS_DEVIDR = USBHS_DEVIDR_DMA_1 << (ep_ix - 1);
xfer_ctl_t *xfer = &xfer_status[ep_ix];
uint16_t count = xfer->total_len - ((status & USBHS_DEVDMASTATUS_BUFF_COUNT_Msk) >> USBHS_DEVDMASTATUS_BUFF_COUNT_Pos);
if(USBHS->USBHS_DEVEPTCFG[ep_ix] & USBHS_DEVEPTCFG_EPDIR)
@ -346,10 +346,10 @@ void dcd_int_handler(uint8_t rhport)
{
(void) rhport;
uint32_t int_status = USBHS->USBHS_DEVISR;
// End of reset interrupt
// End of reset interrupt
if (int_status & USBHS_DEVISR_EORST)
{
// Unfreeze USB clock
// Unfreeze USB clock
USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
while(USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
// Reset all endpoints
@ -363,10 +363,10 @@ void dcd_int_handler(uint8_t rhport)
USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
dcd_event_bus_reset(rhport, get_speed(), true);
}
// End of Wakeup interrupt
// End of Wakeup interrupt
if (int_status & USBHS_DEVISR_WAKEUP)
{
USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
@ -374,31 +374,31 @@ void dcd_int_handler(uint8_t rhport)
USBHS->USBHS_DEVICR = USBHS_DEVICR_WAKEUPC;
USBHS->USBHS_DEVIDR = USBHS_DEVIDR_WAKEUPEC;
USBHS->USBHS_DEVIER = USBHS_DEVIER_SUSPES;
dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
}
// Suspend interrupt
// Suspend interrupt
if (int_status & USBHS_DEVISR_SUSP)
{
// Unfreeze USB clock
// Unfreeze USB clock
USBHS->USBHS_CTRL &= ~USBHS_CTRL_FRZCLK;
while (USBHS_SR_CLKUSABLE != (USBHS->USBHS_SR & USBHS_SR_CLKUSABLE));
USBHS->USBHS_DEVICR = USBHS_DEVICR_SUSPC;
USBHS->USBHS_DEVIDR = USBHS_DEVIDR_SUSPEC;
USBHS->USBHS_DEVIER = USBHS_DEVIER_WAKEUPES;
USBHS->USBHS_CTRL |= USBHS_CTRL_FRZCLK;
dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
}
#if USE_SOF
if(int_status & USBHS_DEVISR_SOF)
{
USBHS->USBHS_DEVICR = USBHS_DEVICR_SOFC;
dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
}
#endif
// Endpoints interrupt
#endif
// Endpoints interrupt
for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
{
if (int_status & (USBHS_DEVISR_PEP_0 << ep_ix))
@ -406,7 +406,7 @@ void dcd_int_handler(uint8_t rhport)
dcd_ep_handler(ep_ix);
}
}
// Endpoints DMA interrupt
// Endpoints DMA interrupt
for (int ep_ix = 0; ep_ix < EP_MAX; ep_ix++)
{
if (EP_DMA_SUPPORT(ep_ix))
@ -433,7 +433,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * re
request->bRequest == TUSB_REQ_SET_ADDRESS )
{
uint8_t const dev_addr = (uint8_t) request->wValue;
USBHS->USBHS_DEVCTRL |= dev_addr | USBHS_DEVCTRL_ADDEN;
}
}
@ -446,9 +446,9 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
uint8_t const dir = tu_edpt_dir(ep_desc->bEndpointAddress);
uint16_t const epMaxPktSize = ep_desc->wMaxPacketSize.size;
tusb_xfer_type_t const eptype = (tusb_xfer_type_t)ep_desc->bmAttributes.xfer;
uint8_t fifoSize = 0; // FIFO size
uint16_t defaultEndpointSize = 8; // Default size of Endpoint
// Find upper 2 power number of epMaxPktSize
uint8_t fifoSize = 0; // FIFO size
uint16_t defaultEndpointSize = 8; // Default size of Endpoint
// Find upper 2 power number of epMaxPktSize
if (epMaxPktSize)
{
while (defaultEndpointSize < epMaxPktSize)
@ -458,16 +458,16 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
}
}
xfer_status[epnum].max_packet_size = epMaxPktSize;
USBHS->USBHS_DEVEPT |= 1 << (USBHS_DEVEPT_EPRST0_Pos + epnum);
USBHS->USBHS_DEVEPT &=~(1 << (USBHS_DEVEPT_EPRST0_Pos + epnum));
if (epnum == 0)
if (epnum == 0)
{
xfer_status[EP_MAX].max_packet_size = epMaxPktSize;
// Enable the control endpoint - Endpoint 0
// Enable the control endpoint - Endpoint 0
USBHS->USBHS_DEVEPT |= USBHS_DEVEPT_EPEN0;
// Configure the Endpoint 0 configuration register
// Configure the Endpoint 0 configuration register
USBHS->USBHS_DEVEPTCFG[0] =
(
USBHS_DEVEPTCFG_EPSIZE(fifoSize) |
@ -479,20 +479,20 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
USBHS->USBHS_DEVEPTIDR[0] = USBHS_DEVEPTIDR_CTRL_STALLRQC;
if (USBHS_DEVEPTISR_CFGOK == (USBHS->USBHS_DEVEPTISR[0] & USBHS_DEVEPTISR_CFGOK))
{
// Endpoint configuration is successful
// Endpoint configuration is successful
USBHS->USBHS_DEVEPTIER[0] = USBHS_DEVEPTIER_CTRL_RXSTPES;
// Enable Endpoint 0 Interrupts
// Enable Endpoint 0 Interrupts
USBHS->USBHS_DEVIER = USBHS_DEVIER_PEP_0;
return true;
} else {
// Endpoint configuration is not successful
// Endpoint configuration is not successful
return false;
}
} else {
// Enable the endpoint
// Enable the endpoint
USBHS->USBHS_DEVEPT |= ((0x01 << epnum) << USBHS_DEVEPT_EPEN0_Pos);
// Set up the maxpacket size, fifo start address fifosize
// and enable the interrupt. CLear the data toggle.
// and enable the interrupt. CLear the data toggle.
// AUTOSW is needed for DMA ack !
USBHS->USBHS_DEVEPTCFG[epnum] =
(
@ -504,12 +504,12 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
);
if (eptype == TUSB_XFER_ISOCHRONOUS)
{
USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1);
USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_NBTRANS(1);
}
#if USE_DUAL_BANK
if (eptype == TUSB_XFER_ISOCHRONOUS || eptype == TUSB_XFER_BULK)
{
USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_EPBK_2_BANK;
USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_EPBK_2_BANK;
}
#endif
USBHS->USBHS_DEVEPTCFG[epnum] |= USBHS_DEVEPTCFG_ALLOC;
@ -520,7 +520,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
USBHS->USBHS_DEVIER = ((0x01 << epnum) << USBHS_DEVIER_PEP_0_Pos);
return true;
} else {
// Endpoint configuration is not successful
// Endpoint configuration is not successful
return false;
}
}
@ -546,7 +546,7 @@ static void dcd_transmit_packet(xfer_ctl_t * xfer, uint8_t ep_ix)
{
// Control endpoint: clear the interrupt flag to send the data
USBHS->USBHS_DEVEPTICR[0] = USBHS_DEVEPTICR_TXINIC;
} else {
// Other endpoint types: clear the FIFO control flag to send the data
USBHS->USBHS_DEVEPTIDR[ep_ix] = USBHS_DEVEPTIDR_FIFOCONC;
@ -560,16 +560,16 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t
(void) rhport;
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
xfer_ctl_t * xfer = &xfer_status[epnum];
if(ep_addr == 0x80)
xfer = &xfer_status[EP_MAX];
xfer->buffer = buffer;
xfer->total_len = total_bytes;
xfer->queued_len = 0;
xfer->fifo = NULL;
if(EP_DMA_SUPPORT(epnum) && total_bytes != 0)
{
uint32_t udd_dma_ctrl = USBHS_DEVDMACONTROL_BUFF_LENGTH(total_bytes);
@ -618,16 +618,16 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
(void) rhport;
uint8_t const epnum = tu_edpt_number(ep_addr);
uint8_t const dir = tu_edpt_dir(ep_addr);
xfer_ctl_t * xfer = &xfer_status[epnum];
if(epnum == 0x80)
xfer = &xfer_status[EP_MAX];
xfer->buffer = NULL;
xfer->total_len = total_bytes;
xfer->queued_len = 0;
xfer->fifo = ff;
if (EP_DMA_SUPPORT(epnum) && total_bytes != 0)
{
tu_fifo_buffer_info_t info;
@ -646,13 +646,13 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16
}
udd_dma_ctrl_wrap |= USBHS_DEVDMACONTROL_END_B_EN;
}
USBHS->UsbhsDevdma[epnum - 1].USBHS_DEVDMAADDRESS = (uint32_t)info.ptr_lin;
if (info.len_wrap)
{
dma_desc[epnum - 1].next_desc = 0;
dma_desc[epnum - 1].buff_addr = (uint32_t)info.ptr_wrap;
dma_desc[epnum - 1].chnl_ctrl =
dma_desc[epnum - 1].chnl_ctrl =
udd_dma_ctrl_wrap | USBHS_DEVDMACONTROL_BUFF_LENGTH(info.len_wrap);
udd_dma_ctrl_lin |= USBHS_DEVDMASTATUS_DESC_LDST;
__DSB();