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metro m4 working with max3421e

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hathach 2023-09-08 18:39:09 +07:00
parent bcc77a60e0
commit 1d68f2a328
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1 changed files with 9 additions and 4 deletions
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13
hw/bsp/samd51/family.c
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@ -294,7 +294,7 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
size_t count = 0; size_t count = 0;
while (count < tx_len || count < rx_len) { while (count < tx_len || count < rx_len) {
// Wait for the transmit buffer to be empty // Wait for the transmit buffer to be empty
// while (!SERCOM2->SPI.INTFLAG.bit.DRE); while (!SERCOM2->SPI.INTFLAG.bit.DRE);
// Write data to be transmitted // Write data to be transmitted
uint8_t data = 0x00; uint8_t data = 0x00;
@ -302,19 +302,24 @@ bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const *tx_buf, size_t tx_l
data = tx_buf[count]; data = tx_buf[count];
} }
SERCOM2->SPI.DATA.bit.DATA = data; SERCOM2->SPI.DATA.reg = (uint32_t) data;
// Wait for the receive buffer to be filled // Wait for the receive buffer to be filled
while (!SERCOM2->SPI.INTFLAG.bit.RXC); while (!SERCOM2->SPI.INTFLAG.bit.RXC);
// Read received data // Read received data
if (rx_buf) { data = (uint8_t) SERCOM2->SPI.DATA.reg;
rx_buf[count] = SERCOM2->SPI.DATA.bit.DATA; if (count < rx_len) {
rx_buf[count] = data;
} }
count++; count++;
} }
// wait for bus idle and clear flags
while (!(SERCOM2->SPI.INTFLAG.reg & (SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE)));
SERCOM2->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE;
return true; return true;
} }
#endif #endif