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https://github.com/hathach/tinyusb.git
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SAM54 Xplained Pro: reduce board setup code for maintenance
The board now runs off the internal oscillator at 48 MHz. This is sufficient to run the TinyUSB examples. A better performing clock setup is keep in the file as init_clock_xtal() as an example.
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@ -1,6 +1,6 @@
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DEPS_SUBMODULES = hw/mcu/microchip
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CONF_CPU_FREQUENCY ?= 120000000
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CONF_CPU_FREQUENCY ?= 48000000
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CFLAGS += \
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-mthumb \
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@ -59,7 +59,19 @@ void USB_3_Handler(void)
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#define BUTTON_PIN PIN_PB31
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#define BOARD_SERCOM SERCOM2
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static inline void init_clock(void)
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/** Initializes the clocks from the external 12 MHz crystal
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*
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* The goal of this setup is to preserve the second PLL
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* for the application code while still having a reasonable
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* 48 MHz clock for USB / UART.
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*
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* GCLK0: CONF_CPU_FREQUENCY (default 120 MHz) from PLL0
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* GCLK1: unused
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* GCLK2: 12 MHz from XOSC1
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* DFLL48M: closed loop from GLCK2
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* GCLK3: 48 MHz
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*/
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static inline void init_clock_xtal(void)
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{
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/* configure for a 12MHz crystal connected to XIN1/XOUT1 */
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OSCCTRL->XOSCCTRL[1].reg =
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@ -118,13 +130,14 @@ static inline void init_clock(void)
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while(1 == GCLK->SYNCBUSY.bit.GENCTRL3);
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}
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/* Initialize SERCOM2 for 115200 bps 8N1 using a 48 MHz clock */
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static inline void uart_init(void)
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{
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gpio_set_pin_function(PIN_PB24, PINMUX_PB24D_SERCOM2_PAD1);
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gpio_set_pin_function(PIN_PB25, PINMUX_PB25D_SERCOM2_PAD0);
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MCLK->APBBMASK.bit.SERCOM2_ = 1;
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GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK3 | GCLK_PCHCTRL_CHEN;
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GCLK->PCHCTRL[SERCOM2_GCLK_ID_CORE].reg = GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN;
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BOARD_SERCOM->USART.CTRLA.bit.SWRST = 1; /* reset and disable SERCOM -> enable configuration */
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while (BOARD_SERCOM->USART.SYNCBUSY.bit.SWRST);
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@ -167,7 +180,8 @@ static inline void uart_send_str(const char* text)
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void board_init(void)
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{
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init_clock();
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// Uncomment this line to run off the XTAL
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// init_clock_xtal();
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SystemCoreClock = CONF_CPU_FREQUENCY;
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@ -218,7 +232,7 @@ void board_init(void)
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* The USB module requires a GCLK_USB of 48 MHz ~ 0.25% clock
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* for low speed and full speed operation.
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*/
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hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK3_Val | GCLK_PCHCTRL_CHEN);
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hri_gclk_write_PCHCTRL_reg(GCLK, USB_GCLK_ID, GCLK_PCHCTRL_GEN_GCLK0_Val | GCLK_PCHCTRL_CHEN);
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hri_mclk_set_AHBMASK_USB_bit(MCLK);
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hri_mclk_set_APBBMASK_USB_bit(MCLK);
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