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stm32h7: USB_OTG_FS -> USB2_OTG_FS.
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@ -35,9 +35,9 @@
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/* MACRO TYPEDEF CONSTANT ENUM
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*------------------------------------------------------------------*/
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#define DEVICE_BASE (USB_OTG_DeviceTypeDef *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_DEVICE_BASE)
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#define OUT_EP_BASE (USB_OTG_OUTEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_OUT_ENDPOINT_BASE)
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#define IN_EP_BASE (USB_OTG_INEndpointTypeDef *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE)
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#define FIFO_BASE(_x) (uint32_t *) (USB_OTG_FS_PERIPH_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE)
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#define OUT_EP_BASE (USB_OTG_OUTEndpointTypeDef *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_OUT_ENDPOINT_BASE)
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#define IN_EP_BASE (USB_OTG_INEndpointTypeDef *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_IN_ENDPOINT_BASE)
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#define FIFO_BASE(_x) (uint32_t *) (USB2_OTG_FS_PERIPH_BASE + USB_OTG_FIFO_BASE + (_x) * USB_OTG_FIFO_SIZE)
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static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
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static uint8_t _setup_offs; // We store up to 3 setup packets.
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@ -99,7 +99,7 @@ static void bus_reset(void)
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USB2_OTG_FS->GRXFSIZ = 50;
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// Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
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USB2_OTG_FS->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (USB_OTG_FS->GRXFSIZ & 0x0000ffffUL);
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USB2_OTG_FS->DIEPTXF0_HNPTXFSIZ = (16 << USB_OTG_TX0FD_Pos) | (USB2_OTG_FS->GRXFSIZ & 0x0000ffffUL);
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out_ep[0].DOEPTSIZ |= (3 << USB_OTG_DOEPTSIZ_STUPCNT_Pos);
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@ -266,8 +266,8 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
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// Both TXFD and TXSA are in unit of 32-bit words
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uint16_t const fifo_size = 130;
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uint32_t const fifo_offset = (USB_OTG_FS->GRXFSIZ & 0x0000ffff) + 16 + fifo_size*(epnum-1);
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USB_OTG_FS->DIEPTXF[epnum - 1] = (130 << USB_OTG_DIEPTXF_INEPTXFD_Pos) | fifo_offset;
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uint32_t const fifo_offset = (USB2_OTG_FS->GRXFSIZ & 0x0000ffff) + 16 + fifo_size*(epnum-1);
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USB2_OTG_FS->DIEPTXF[epnum - 1] = (130 << USB_OTG_DIEPTXF_INEPTXFD_Pos) | fifo_offset;
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}
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return true;
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@ -343,9 +343,9 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
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}
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// Flush the FIFO, and wait until we have confirmed it cleared.
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USB_OTG_FS->GRSTCTL |= ((epnum - 1) << USB_OTG_GRSTCTL_TXFNUM_Pos);
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USB_OTG_FS->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
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while((USB_OTG_FS->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
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USB2_OTG_FS->GRSTCTL |= ((epnum - 1) << USB_OTG_GRSTCTL_TXFNUM_Pos);
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USB2_OTG_FS->GRSTCTL |= USB_OTG_GRSTCTL_TXFFLSH;
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while((USB2_OTG_FS->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH_Msk) != 0);
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} else {
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// Only disable currently enabled non-control endpoint
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if ( (epnum == 0) || !(out_ep[epnum].DOEPCTL & USB_OTG_DOEPCTL_EPENA) ){
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@ -356,7 +356,7 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr)
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// anyway, and it can't be cleared by user code. If this while loop never
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// finishes, we have bigger problems than just the stack.
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dev->DCTL |= USB_OTG_DCTL_SGONAK;
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while((USB_OTG_FS->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
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while((USB2_OTG_FS->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF_Msk) == 0);
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// Ditto here- disable the endpoint.
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out_ep[epnum].DOEPCTL |= (USB_OTG_DOEPCTL_STALL | USB_OTG_DOEPCTL_EPDIS);
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@ -612,7 +612,7 @@ void OTG_FS_IRQHandler (void)
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USB_OTG_OUTEndpointTypeDef * out_ep = OUT_EP_BASE;
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USB_OTG_INEndpointTypeDef * in_ep = IN_EP_BASE;
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uint32_t int_status = USB_OTG_FS->GINTSTS;
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uint32_t int_status = USB2_OTG_FS->GINTSTS;
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if(int_status & USB_OTG_GINTMSK_USBRST)
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{
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@ -628,7 +628,7 @@ void OTG_FS_IRQHandler (void)
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}
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if(int_status & USB_OTG_GINTSTS_SOF) {
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USB_OTG_FS->GINTSTS = USB_OTG_GINTSTS_SOF;
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USB2_OTG_FS->GINTSTS = USB_OTG_GINTSTS_SOF;
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dcd_event_bus_signal(0, DCD_EVENT_SOF, true);
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}
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