mirror of
https://github.com/hathach/tinyusb.git
synced 2025-02-15 21:40:18 +00:00
Bunny brain board created, but not modified yet
Bunny brain board created, but not modified yet
This commit is contained in:
Jerry Palacios
parent
2fadc06412
commit
17cd5e0952
21
hw/bsp/mcx/boards/bunny-brain/board.cmake
Normal file
21
hw/bsp/mcx/boards/bunny-brain/board.cmake
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@ -0,0 +1,21 @@
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set(MCU_VARIANT MCXN947)
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set(MCU_CORE MCXN947_cm33_core0)
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set(JLINK_DEVICE MCXN947_M33_0)
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set(PYOCD_TARGET MCXN947)
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set(NXPLINK_DEVICE MCXN947:MCXN947)
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set(PORT 1)
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function(update_board TARGET)
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target_compile_definitions(${TARGET} PUBLIC
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CPU_MCXN947VDF_cm33_core0
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BOARD_TUD_RHPORT=${PORT}
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# port 0 is fullspeed, port 1 is highspeed
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BOARD_TUD_MAX_SPEED=$<IF:${PORT},OPT_MODE_HIGH_SPEED,OPT_MODE_FULL_SPEED>
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)
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target_sources(${TARGET} PUBLIC
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/clock_config.c
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${CMAKE_CURRENT_FUNCTION_LIST_DIR}/pin_mux.c
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)
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endfunction()
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66
hw/bsp/mcx/boards/bunny-brain/board.h
Normal file
66
hw/bsp/mcx/boards/bunny-brain/board.h
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@ -0,0 +1,66 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021, Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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// LED
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#define LED_GPIO GPIO3
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#define LED_CLK kCLOCK_Gpio3
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#define LED_PIN 4 // red
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#define LED_STATE_ON 0
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// WAKE button (Dummy, use unused pin
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#define BUTTON_GPIO GPIO0
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#define BUTTON_CLK kCLOCK_Gpio0
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#define BUTTON_PIN 6
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#define BUTTON_STATE_ACTIVE 0
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// UART
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#define UART_DEV LPUART4
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static inline void board_uart_init_clock(void) {
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/* attach FRO 12M to FLEXCOMM4 */
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CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
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CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
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RESET_ClearPeripheralReset(kFC4_RST_SHIFT_RSTn);
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}
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//#define UART_RX_PINMUX 0, 24, IOCON_PIO_DIG_FUNC1_EN
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//#define UART_TX_PINMUX 0, 25, IOCON_PIO_DIG_FUNC1_EN
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// XTAL
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#define XTAL0_CLK_HZ (24 * 1000 * 1000U)
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#ifdef __cplusplus
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}
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#endif
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#endif
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11
hw/bsp/mcx/boards/bunny-brain/board.mk
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11
hw/bsp/mcx/boards/bunny-brain/board.mk
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@ -0,0 +1,11 @@
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MCU_VARIANT = MCXN947
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MCU_CORE = MCXN947_cm33_core0
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PORT ?= 1
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CFLAGS += -DCPU_MCXN947VDF_cm33_core0
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JLINK_DEVICE = MCXN947_M33_0
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PYOCD_TARGET = MCXN947
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# flash using pyocd
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flash: flash-jlink
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338
hw/bsp/mcx/boards/bunny-brain/clock_config.c
Normal file
338
hw/bsp/mcx/boards/bunny-brain/clock_config.c
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@ -0,0 +1,338 @@
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/*
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* Copyright 2022 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/***********************************************************************************************************************
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* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
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* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
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**********************************************************************************************************************/
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/*
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* How to setup clock using clock driver functions:
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*
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* 1. Setup clock sources.
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*
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* 2. Set up wait states of the flash.
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*
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* 3. Set up all dividers.
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*
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* 4. Set up all selectors to provide selected clocks.
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*
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*/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!GlobalInfo
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product: Clocks v10.0
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processor: MCXN947
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package_id: MCXN947VDF
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mcu_data: ksdk2_0
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processor_version: 0.12.3
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board: MCX-N9XX-EVK
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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#include "clock_config.h"
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#include "fsl_clock.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/* System clock frequency. */
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// extern uint32_t SystemCoreClock;
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/*******************************************************************************
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************************ BOARD_InitBootClocks function ************************
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******************************************************************************/
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void BOARD_InitBootClocks(void)
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{
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BOARD_BootClockPLL150M();
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}
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/*******************************************************************************
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******************** Configuration BOARD_BootClockFRO12M **********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFRO12M
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outputs:
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- {id: CLK_144M_clock.outFreq, value: 144 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: MAIN_clock.outFreq, value: 12 MHz}
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- {id: Slow_clock.outFreq, value: 3 MHz}
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- {id: System_clock.outFreq, value: 12 MHz}
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- {id: gdet_clock.outFreq, value: 48 MHz}
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- {id: trng_clock.outFreq, value: 48 MHz}
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settings:
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- {id: SCGMode, value: SIRC}
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- {id: SCG.SCSSEL.sel, value: SCG.SIRC}
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- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
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- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
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- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFRO12M configuration
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******************************************************************************/
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void BOARD_BootClockFRO12M(void)
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{
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/*!< Enable SCG clock */
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CLOCK_EnableClock(kCLOCK_Scg);
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************* Configuration BOARD_BootClockFROHF48M *********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFROHF48M
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outputs:
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- {id: CLK_144M_clock.outFreq, value: 144 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: FRO_HF_clock.outFreq, value: 48 MHz}
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- {id: MAIN_clock.outFreq, value: 48 MHz}
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- {id: Slow_clock.outFreq, value: 12 MHz}
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- {id: System_clock.outFreq, value: 48 MHz}
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- {id: gdet_clock.outFreq, value: 48 MHz}
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- {id: trng_clock.outFreq, value: 48 MHz}
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settings:
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- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
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- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
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- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
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- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFROHF48M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFROHF48M configuration
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******************************************************************************/
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void BOARD_BootClockFROHF48M(void)
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{
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/*!< Enable SCG clock */
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CLOCK_EnableClock(kCLOCK_Scg);
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CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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/*!< Set up dividers */
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
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}
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/*******************************************************************************
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******************* Configuration BOARD_BootClockFROHF144M ********************
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******************************************************************************/
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/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
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!!Configuration
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name: BOARD_BootClockFROHF144M
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outputs:
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- {id: CLK_144M_clock.outFreq, value: 144 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
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- {id: FRO_HF_clock.outFreq, value: 144 MHz}
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- {id: MAIN_clock.outFreq, value: 144 MHz}
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- {id: Slow_clock.outFreq, value: 18 MHz}
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- {id: System_clock.outFreq, value: 72 MHz}
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- {id: gdet_clock.outFreq, value: 48 MHz}
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- {id: trng_clock.outFreq, value: 48 MHz}
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settings:
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- {id: SYSCON.AHBCLKDIV.scale, value: '2', locked: true}
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- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
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- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
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- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
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- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
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sources:
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- {id: SCG.FIRC.outFreq, value: 144 MHz}
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* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
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/* clang-format on */
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/*******************************************************************************
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* Variables for BOARD_BootClockFROHF144M configuration
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******************************************************************************/
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/*******************************************************************************
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* Code for BOARD_BootClockFROHF144M configuration
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******************************************************************************/
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void BOARD_BootClockFROHF144M(void)
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{
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/*!< Enable SCG clock */
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CLOCK_EnableClock(kCLOCK_Scg);
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CLOCK_SetupFROHFClocking(144000000U); /*!< Enable FRO HF(144MHz) output */
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/*!< Set up clock selectors - Attach clocks to the peripheries */
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CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
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/*!< Set up dividers */
|
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CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 2U); /*!< Set AHBCLKDIV divider to value 2 */
|
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/* Set SystemCoreClock variable */
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SystemCoreClock = BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK;
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}
|
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|
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/*******************************************************************************
|
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******************** Configuration BOARD_BootClockPLL150M *********************
|
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******************************************************************************/
|
||||
/* clang-format off */
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/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockPLL150M
|
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called_from_default_init: true
|
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outputs:
|
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- {id: CLK_144M_clock.outFreq, value: 144 MHz}
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
|
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- {id: FRO_HF_clock.outFreq, value: 48 MHz}
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- {id: MAIN_clock.outFreq, value: 150 MHz}
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- {id: PLL0_CLK_clock.outFreq, value: 150 MHz}
|
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- {id: Slow_clock.outFreq, value: 37.5 MHz}
|
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- {id: System_clock.outFreq, value: 150 MHz}
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- {id: gdet_clock.outFreq, value: 48 MHz}
|
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- {id: trng_clock.outFreq, value: 48 MHz}
|
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settings:
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- {id: PLL0_Mode, value: Normal}
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- {id: RunPowerMode, value: OD}
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- {id: SCGMode, value: PLL0}
|
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- {id: SCG.PLL0M_MULT.scale, value: '50', locked: true}
|
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- {id: SCG.PLL0SRCSEL.sel, value: SCG.FIRC_48M}
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- {id: SCG.PLL0_NDIV.scale, value: '8', locked: true}
|
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- {id: SCG.SCSSEL.sel, value: SCG.PLL0_CLK}
|
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- {id: SYSCON.FLEXCAN0CLKSEL.sel, value: NO_CLOCK}
|
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- {id: SYSCON.FLEXCAN1CLKSEL.sel, value: NO_CLOCK}
|
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- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
|
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- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockPLL150M(void)
|
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{
|
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/*!< Enable SCG clock */
|
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CLOCK_EnableClock(kCLOCK_Scg);
|
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|
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CLOCK_SetupFROHFClocking(48000000U); /*!< Enable FRO HF(48MHz) output */
|
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|
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/*!< Set up PLL0 */
|
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const pll_setup_t pll0Setup = {
|
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.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) | SCG_APLLCTRL_SELP(13U),
|
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.pllndiv = SCG_APLLNDIV_NDIV(8U),
|
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.pllpdiv = SCG_APLLPDIV_PDIV(1U),
|
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.pllmdiv = SCG_APLLMDIV_MDIV(50U),
|
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.pllRate = 150000000U
|
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};
|
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CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
|
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CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable); /* Pll0 Monitor is disabled */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
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CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
|
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|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
|
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|
||||
/* Set SystemCoreClock variable */
|
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SystemCoreClock = BOARD_BOOTCLOCKPLL150M_CORE_CLOCK;
|
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}
|
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|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
||||
******************************************************************************/
|
||||
/* clang-format off */
|
||||
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!Configuration
|
||||
name: BOARD_BootClockPLL100M
|
||||
outputs:
|
||||
- {id: CLK_144M_clock.outFreq, value: 144 MHz}
|
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- {id: CLK_48M_clock.outFreq, value: 48 MHz}
|
||||
- {id: CLK_IN_clock.outFreq, value: 24 MHz}
|
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- {id: FRO_12M_clock.outFreq, value: 12 MHz}
|
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- {id: MAIN_clock.outFreq, value: 100 MHz}
|
||||
- {id: PLL1_CLK_clock.outFreq, value: 100 MHz}
|
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- {id: Slow_clock.outFreq, value: 25 MHz}
|
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- {id: System_clock.outFreq, value: 100 MHz}
|
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- {id: gdet_clock.outFreq, value: 48 MHz}
|
||||
- {id: trng_clock.outFreq, value: 48 MHz}
|
||||
settings:
|
||||
- {id: PLL1_Mode, value: Normal}
|
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- {id: SCGMode, value: PLL1}
|
||||
- {id: SCG.PLL1M_MULT.scale, value: '100', locked: true}
|
||||
- {id: SCG.PLL1_NDIV.scale, value: '6', locked: true}
|
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- {id: SCG.PLL1_PDIV.scale, value: '4', locked: true}
|
||||
- {id: SCG.SCSSEL.sel, value: SCG.PLL1_CLK}
|
||||
- {id: SCG_FIRCCSR_FIRCEN_CFG, value: Disabled}
|
||||
- {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
|
||||
- {id: SYSCON.FREQMEREFCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
- {id: SYSCON.FREQMETARGETCLKSEL.sel, value: SYSCON.evtg_out0a}
|
||||
sources:
|
||||
- {id: SCG.SOSC.outFreq, value: 24 MHz, enabled: true}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
|
||||
/* clang-format on */
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Code for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
void BOARD_BootClockPLL100M(void)
|
||||
{
|
||||
/*!< Enable SCG clock */
|
||||
CLOCK_EnableClock(kCLOCK_Scg);
|
||||
|
||||
CLOCK_SetupExtClocking(24000000U);
|
||||
CLOCK_SetSysOscMonitorMode(kSCG_SysOscMonitorDisable); /* System OSC Clock Monitor is disabled */
|
||||
|
||||
/*!< Set up PLL1 */
|
||||
const pll_setup_t pll1Setup = {
|
||||
.pllctrl = SCG_SPLLCTRL_SOURCE(0U) | SCG_SPLLCTRL_SELI(53U) | SCG_SPLLCTRL_SELP(26U),
|
||||
.pllndiv = SCG_SPLLNDIV_NDIV(6U),
|
||||
.pllpdiv = SCG_SPLLPDIV_PDIV(2U),
|
||||
.pllmdiv = SCG_SPLLMDIV_MDIV(100U),
|
||||
.pllRate = 100000000U
|
||||
};
|
||||
CLOCK_SetPLL1Freq(&pll1Setup); /*!< Configure PLL1 to the desired values */
|
||||
CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable); /* Pll1 Monitor is disabled */
|
||||
|
||||
/*!< Set up clock selectors - Attach clocks to the peripheries */
|
||||
CLOCK_AttachClk(kPLL1_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL1 */
|
||||
|
||||
/*!< Set up dividers */
|
||||
CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U); /*!< Set AHBCLKDIV divider to value 1 */
|
||||
|
||||
/* Set SystemCoreClock variable */
|
||||
SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
|
||||
}
|
||||
177
hw/bsp/mcx/boards/bunny-brain/clock_config.h
Normal file
177
hw/bsp/mcx/boards/bunny-brain/clock_config.h
Normal file
@ -0,0 +1,177 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _CLOCK_CONFIG_H_
|
||||
#define _CLOCK_CONFIG_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal frequency in Hz */
|
||||
#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32K frequency in Hz */
|
||||
|
||||
/*******************************************************************************
|
||||
************************ BOARD_InitBootClocks function ************************
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes default configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootClocks(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockFRO12M **********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency: 12000000Hz */
|
||||
#define BOARD_BOOTCLOCKFRO12M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFRO12M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFRO12M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF48M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFROHF48M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency: 48000000Hz */
|
||||
#define BOARD_BOOTCLOCKFROHF48M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFROHF48M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFROHF48M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************* Configuration BOARD_BootClockFROHF144M ********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockFROHF144M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKFROHF144M_CORE_CLOCK 144000000U /*!< Core clock frequency: 144000000Hz */
|
||||
#define BOARD_BOOTCLOCKFROHF144M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockFROHF144M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockFROHF144M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL150M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKPLL150M_CORE_CLOCK 150000000U /*!< Core clock frequency: 150000000Hz */
|
||||
#define BOARD_BOOTCLOCKPLL150M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockPLL150M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockPLL150M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*******************************************************************************
|
||||
******************** Configuration BOARD_BootClockPLL100M *********************
|
||||
******************************************************************************/
|
||||
/*******************************************************************************
|
||||
* Definitions for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
#define BOARD_BOOTCLOCKPLL100M_CORE_CLOCK 100000000U /*!< Core clock frequency: 100000000Hz */
|
||||
#define BOARD_BOOTCLOCKPLL100M_ROSC_CLOCK 0U /*!< ROSC clock frequency: 0Hz */
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* API for BOARD_BootClockPLL100M configuration
|
||||
******************************************************************************/
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
/*!
|
||||
* @brief This function executes configuration of clocks.
|
||||
*
|
||||
*/
|
||||
void BOARD_BootClockPLL100M(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif /* __cplusplus*/
|
||||
|
||||
#endif /* _CLOCK_CONFIG_H_ */
|
||||
141
hw/bsp/mcx/boards/bunny-brain/pin_mux.c
Normal file
141
hw/bsp/mcx/boards/bunny-brain/pin_mux.c
Normal file
@ -0,0 +1,141 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
!!GlobalInfo
|
||||
product: Pins v12.0
|
||||
processor: MCXN947
|
||||
package_id: MCXN947VDF
|
||||
mcu_data: ksdk2_0
|
||||
processor_version: 0.12.3
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
#include "fsl_common.h"
|
||||
#include "fsl_port.h"
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitBootPins
|
||||
* Description : Calls initialization functions.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitBootPins(void)
|
||||
{
|
||||
BOARD_InitPins();
|
||||
}
|
||||
|
||||
/* clang-format off */
|
||||
/*
|
||||
* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
|
||||
BOARD_InitPins:
|
||||
- options: {callFromInitBoot: 'true', coreID: cm33_core0, enableClock: 'true'}
|
||||
- pin_list:
|
||||
- {pin_num: A1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P0, pin_signal: PIO1_8/WUU0_IN10/LPTMR1_ALT3/TRACE_DATA0/FC4_P0/FC5_P4/CT_INP8/SCT0_OUT2/FLEXIO0_D16/PLU_OUT0/ENET0_TXD2/I3C1_SDA/TSI0_CH17/ADC1_A8,
|
||||
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, pull_value: low, input_buffer: enable,
|
||||
invert_input: normal}
|
||||
- {pin_num: B1, peripheral: LPFlexcomm4, signal: LPFLEXCOMM_P1, pin_signal: PIO1_9/TRACE_DATA1/FC4_P1/FC5_P5/CT_INP9/SCT0_OUT3/FLEXIO0_D17/PLU_OUT1/ENET0_TXD3/I3C1_SCL/TSI0_CH18/ADC1_A9,
|
||||
slew_rate: fast, open_drain: disable, drive_strength: low, pull_select: down, pull_enable: disable, passive_filter: disable, input_buffer: enable, invert_input: normal}
|
||||
- {pin_num: F14, peripheral: GPIO3, signal: 'GPIO, 4', pin_signal: PIO3_4/FC7_P2/CT_INP18/PWM0_X2/FLEXIO0_D12/SIM1_CLK, slew_rate: fast, open_drain: disable, drive_strength: low,
|
||||
pull_select: down, pull_enable: disable, input_buffer: enable, invert_input: normal}
|
||||
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
|
||||
*/
|
||||
/* clang-format on */
|
||||
|
||||
/* FUNCTION ************************************************************************************************************
|
||||
*
|
||||
* Function Name : BOARD_InitPins
|
||||
* Description : Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
* END ****************************************************************************************************************/
|
||||
void BOARD_InitPins(void)
|
||||
{
|
||||
/* Enables the clock for PORT1: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Port1);
|
||||
/* Enables the clock for PORT3: Enables clock */
|
||||
CLOCK_EnableClock(kCLOCK_Port3);
|
||||
|
||||
const port_pin_config_t port1_8_pinA1_config = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as FC4_P0 */
|
||||
kPORT_MuxAlt2,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT1_8 (pin A1) is configured as FC4_P0 */
|
||||
PORT_SetPinConfig(PORT1, 8U, &port1_8_pinA1_config);
|
||||
|
||||
const port_pin_config_t port1_9_pinB1_config = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as FC4_P1 */
|
||||
kPORT_MuxAlt2,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT1_9 (pin B1) is configured as FC4_P1 */
|
||||
PORT_SetPinConfig(PORT1, 9U, &port1_9_pinB1_config);
|
||||
|
||||
const port_pin_config_t port3_4_pinF14_config = {/* Internal pull-up/down resistor is disabled */
|
||||
kPORT_PullDisable,
|
||||
/* Low internal pull resistor value is selected. */
|
||||
kPORT_LowPullResistor,
|
||||
/* Fast slew rate is configured */
|
||||
kPORT_FastSlewRate,
|
||||
/* Passive input filter is disabled */
|
||||
kPORT_PassiveFilterDisable,
|
||||
/* Open drain output is disabled */
|
||||
kPORT_OpenDrainDisable,
|
||||
/* Low drive strength is configured */
|
||||
kPORT_LowDriveStrength,
|
||||
/* Pin is configured as PIO3_4 */
|
||||
kPORT_MuxAlt0,
|
||||
/* Digital input enabled */
|
||||
kPORT_InputBufferEnable,
|
||||
/* Digital input is not inverted */
|
||||
kPORT_InputNormal,
|
||||
/* Pin Control Register fields [15:0] are not locked */
|
||||
kPORT_UnlockRegister};
|
||||
/* PORT3_4 (pin F14) is configured as PIO3_4 */
|
||||
PORT_SetPinConfig(PORT3, 4U, &port3_4_pinF14_config);
|
||||
}
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
51
hw/bsp/mcx/boards/bunny-brain/pin_mux.h
Normal file
51
hw/bsp/mcx/boards/bunny-brain/pin_mux.h
Normal file
@ -0,0 +1,51 @@
|
||||
/*
|
||||
* Copyright 2022 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/***********************************************************************************************************************
|
||||
* This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
|
||||
* will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#ifndef _PIN_MUX_H_
|
||||
#define _PIN_MUX_H_
|
||||
|
||||
/*!
|
||||
* @addtogroup pin_mux
|
||||
* @{
|
||||
*/
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* API
|
||||
**********************************************************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @brief Calls initialization functions.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitBootPins(void);
|
||||
|
||||
/*!
|
||||
* @brief Configures pin routing and optionally pin electrical features.
|
||||
*
|
||||
*/
|
||||
void BOARD_InitPins(void);
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/
|
||||
#endif /* _PIN_MUX_H_ */
|
||||
|
||||
/***********************************************************************************************************************
|
||||
* EOF
|
||||
**********************************************************************************************************************/
|
||||
Loading…
x
Reference in New Issue
Block a user