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https://github.com/hathach/tinyusb.git
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better qspi
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parent
8572947da5
commit
154daf584c
@ -47,6 +47,19 @@ void flash_flush (void);
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM DECLARATION
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//--------------------------------------------------------------------+
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enum
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{
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FLASH_STATE_IDLE,
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FLASH_STATE_BUSY,
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FLASH_STATE_COMPLETE
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};
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volatile uint8_t _fl_state = FLASH_STATE_IDLE;
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void qspi_flash_complete (void)
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{
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_fl_state = FLASH_STATE_COMPLETE;
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}
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//------------- IMPLEMENTATION -------------//
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// Callback invoked when received READ10 command.
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@ -55,8 +68,27 @@ int32_t tud_msc_read10_cb(uint8_t lun, uint32_t lba, uint32_t offset, void* buff
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{
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uint32_t addr = lba * CFG_TUD_MSC_BLOCK_SZ + offset;
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flash_read(buffer, addr, bufsize);
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// switch ( _fl_state )
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// {
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// case FLASH_STATE_IDLE:
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// _fl_state = FLASH_STATE_BUSY;
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// flash_read(buffer, addr, bufsize);
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// return 0; // data not ready
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//
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// case FLASH_STATE_BUSY:
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// return 0; // data not ready
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//
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// case FLASH_STATE_COMPLETE:
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// _fl_state = FLASH_STATE_IDLE;
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// return bufsize;
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//
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// default:
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// _fl_state = FLASH_STATE_IDLE;
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// return -1;
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// }
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flash_read(buffer, addr, bufsize);
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return bufsize;
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}
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@ -96,7 +128,16 @@ void flash_flush (void)
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if ( _fl_addr == NO_CACHE ) return;
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TU_ASSERT(NRFX_SUCCESS == nrfx_qspi_erase(NRF_QSPI_ERASE_LEN_4KB, _fl_addr),);
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// while ( _fl_state != FLASH_STATE_COMPLETE )
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// {
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// }
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// _fl_state = FLASH_STATE_IDLE;
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TU_ASSERT(NRFX_SUCCESS == nrfx_qspi_write(_fl_buf, FLASH_PAGE_SIZE, _fl_addr),);
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// while ( _fl_state != FLASH_STATE_COMPLETE )
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// {
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// }
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// _fl_state = FLASH_STATE_IDLE;
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_fl_addr = NO_CACHE;
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}
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@ -109,7 +150,8 @@ void flash_write (uint32_t dst, const void *src, int len)
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{
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flash_flush();
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_fl_addr = newAddr;
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memset(_fl_buf, 0xff, FLASH_PAGE_SIZE);
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flash_read(_fl_buf, newAddr, FLASH_PAGE_SIZE);
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}
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memcpy(_fl_buf + (dst & (FLASH_PAGE_SIZE - 1)), src, len);
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}
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@ -80,6 +80,17 @@ uint32_t tusb_hal_millis(void)
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#define QSPI_STD_CMD_RST 0x99
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#define QSPI_STD_CMD_WRSR 0x01
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extern void qspi_flash_complete (void);
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void qflash_hdl (nrfx_qspi_evt_t event, void * p_context)
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{
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(void) p_context;
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(void) event;
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qspi_flash_complete();
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}
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/* tinyusb function that handles power event (detected, ready, removed)
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* We must call it within SD's SOC event handler, or set it as power event handler if SD is not enabled.
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*/
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@ -104,42 +115,41 @@ void board_init(void)
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// 64 Mbit qspi flash
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#ifdef BOARD_MSC_FLASH_QSPI
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nrfx_qspi_config_t qspi_cfg =
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{
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.xip_offset = 0,
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nrfx_qspi_config_t qspi_cfg = {
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.xip_offset = 0,
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.pins = {
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.sck_pin = 19,
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.csn_pin = 17,
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.io0_pin = 20,
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.io1_pin = 21,
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.io2_pin = 22,
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.io3_pin = 23,
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.sck_pin = 19,
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.csn_pin = 17,
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.io0_pin = 20,
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.io1_pin = 21,
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.io2_pin = 22,
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.io3_pin = 23,
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},
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.prot_if = {
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.readoc = NRF_QSPI_READOC_FASTREAD,
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.writeoc = NRF_QSPI_WRITEOC_PP,
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.addrmode = NRF_QSPI_ADDRMODE_24BIT,
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.dpmconfig = false, // deep power down
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.readoc = NRF_QSPI_READOC_READ4IO,
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.writeoc = NRF_QSPI_WRITEOC_PP,
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.addrmode = NRF_QSPI_ADDRMODE_24BIT,
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.dpmconfig = false, // deep power down
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},
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.phy_if = {
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.sck_freq = NRF_QSPI_FREQ_32MDIV16,
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.sck_delay = 1,
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.spi_mode = NRF_QSPI_MODE_0,
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.dpmen = false
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.sck_freq = NRF_QSPI_FREQ_32MDIV4,
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.sck_delay = 1,
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.spi_mode = NRF_QSPI_MODE_0,
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.dpmen = false
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},
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.irq_priority = 7,
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};
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// callback = NULL --> blocking
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nrfx_qspi_init(&qspi_cfg, NULL, NULL);
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// nrfx_qspi_init(&qspi_cfg, qflash_hdl, NULL);
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nrf_qspi_cinstr_conf_t cinstr_cfg = {
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.opcode = 0,
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.length = 0,
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.io2_level = true,
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.io3_level = true,
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.wipwait = true,
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.wren = true
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.opcode = 0,
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.length = 0,
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.io2_level = true,
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.io3_level = true,
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.wipwait = true,
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.wren = true
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};
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// Send reset enable
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