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ea4088 quickstart build with makefile
This commit is contained in:
hathach
parent
6e6f470b58
commit
15076006ca
41
hw/bsp/ea4088qs/board.mk
Normal file
41
hw/bsp/ea4088qs/board.mk
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@ -0,0 +1,41 @@
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CFLAGS += \
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-mthumb \
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-mabi=aapcs \
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-mcpu=cortex-m4 \
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-nostdlib \
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-DCORE_M4 \
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-DCFG_TUSB_MCU=OPT_MCU_LPC40XX \
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-DCFG_TUSB_MEM_SECTION='__attribute__((section(".data.$$RAM2")))' \
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-D__USE_LPCOPEN
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# All source paths should be relative to the top level.
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LD_FILE = hw/bsp/ea4088qs/lpc4088.ld
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# TODO remove later
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SRC_C += src/portable/$(VENDOR)/$(CHIP_FAMILY)/hal_$(CHIP_FAMILY).c
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SRC_C += \
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hw/mcu/nxp/lpcopen/lpc_chip_40xx/src/chip_17xx_40xx.c \
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hw/mcu/nxp/lpcopen/lpc_chip_40xx/src/clock_17xx_40xx.c \
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hw/mcu/nxp/lpcopen/lpc_chip_40xx/src/gpio_17xx_40xx.c \
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hw/mcu/nxp/lpcopen/lpc_chip_40xx/src/iocon_17xx_40xx.c \
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hw/mcu/nxp/lpcopen/lpc_chip_40xx/src/sysctl_17xx_40xx.c \
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hw/mcu/nxp/lpcopen/lpc_chip_40xx/src/sysinit_17xx_40xx.c \
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hw/mcu/nxp/lpcopen/lpc_chip_40xx/src/uart_17xx_40xx.c
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INC += \
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$(TOP)/hw/mcu/nxp/lpcopen/lpc_chip_40xx/inc
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# For TinyUSB port source
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VENDOR = nxp
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CHIP_FAMILY = lpc17_40
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# For freeRTOS port source
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FREERTOS_PORT = ARM_CM3
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# For flash-jlink target
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JLINK_DEVICE = LPC4088
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JLINK_IF = swd
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# flash using jlink
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flash: flash-jlink
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418
hw/bsp/ea4088qs/cr_startup_lpc40xx.c
Normal file
418
hw/bsp/ea4088qs/cr_startup_lpc40xx.c
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@ -0,0 +1,418 @@
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//*****************************************************************************
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// LPC407x_8x Microcontroller Startup code for use with LPCXpresso IDE
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//
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// Version : 140114
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//*****************************************************************************
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//
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// Copyright(C) NXP Semiconductors, 2014
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// All rights reserved.
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//
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// Software that is described herein is for illustrative purposes only
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// which provides customers with programming information regarding the
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// LPC products. This software is supplied "AS IS" without any warranties of
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// any kind, and NXP Semiconductors and its licensor disclaim any and
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// all warranties, express or implied, including all implied warranties of
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// merchantability, fitness for a particular purpose and non-infringement of
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// intellectual property rights. NXP Semiconductors assumes no responsibility
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// or liability for the use of the software, conveys no license or rights under any
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// patent, copyright, mask work right, or any other intellectual property rights in
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// or to any products. NXP Semiconductors reserves the right to make changes
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// in the software without notification. NXP Semiconductors also makes no
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// representation or warranty that such application will be suitable for the
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// specified use without further testing or modification.
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//
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// Permission to use, copy, modify, and distribute this software and its
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// documentation is hereby granted, under NXP Semiconductors' and its
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// licensor's relevant copyrights in the software, without fee, provided that it
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// is used in conjunction with NXP Semiconductors microcontrollers. This
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// copyright, permission, and disclaimer notice must appear in all copies of
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// this code.
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//*****************************************************************************
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#if defined (__cplusplus)
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#ifdef __REDLIB__
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#error Redlib does not support C++
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#else
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//*****************************************************************************
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//
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// The entry point for the C++ library startup
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//
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//*****************************************************************************
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extern "C" {
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extern void __libc_init_array(void);
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}
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#endif
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#endif
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#define WEAK __attribute__ ((weak))
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#define ALIAS(f) __attribute__ ((weak, alias (#f)))
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//*****************************************************************************
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#if defined (__cplusplus)
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extern "C" {
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#endif
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//*****************************************************************************
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#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
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// Declaration of external SystemInit function
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extern void SystemInit(void);
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#endif
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//*****************************************************************************
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//
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// Forward declaration of the default handlers. These are aliased.
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// When the application defines a handler (with the same name), this will
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// automatically take precedence over these weak definitions
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//
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//*****************************************************************************
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void ResetISR(void);
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WEAK void NMI_Handler(void);
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WEAK void HardFault_Handler(void);
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WEAK void MemManage_Handler(void);
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WEAK void BusFault_Handler(void);
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WEAK void UsageFault_Handler(void);
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WEAK void SVC_Handler(void);
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WEAK void DebugMon_Handler(void);
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WEAK void PendSV_Handler(void);
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WEAK void SysTick_Handler(void);
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WEAK void IntDefaultHandler(void);
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//*****************************************************************************
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//
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// Forward declaration of the specific IRQ handlers. These are aliased
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// to the IntDefaultHandler, which is a 'forever' loop. When the application
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// defines a handler (with the same name), this will automatically take
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// precedence over these weak definitions
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//
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//*****************************************************************************
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void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
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void TIMER0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void TIMER1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void TIMER2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void TIMER3_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void UART3_IRQHandler(void) ALIAS(IntDefaultHandler);
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void PWM1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2C1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2C2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SPI_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SSP0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SSP1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void PLL0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void RTC_IRQHandler(void) ALIAS(IntDefaultHandler);
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void EINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void EINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void EINT2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void EINT3_IRQHandler(void) ALIAS(IntDefaultHandler);
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void ADC_IRQHandler(void) ALIAS(IntDefaultHandler);
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void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
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void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
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void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
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void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
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void I2S_IRQHandler(void) ALIAS(IntDefaultHandler);
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#if defined (__USE_LPCOPEN)
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void ETH_IRQHandler(void) ALIAS(IntDefaultHandler);
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#else
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void ENET_IRQHandler(void) ALIAS(IntDefaultHandler);
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#endif
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void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
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void MCPWM_IRQHandler(void) ALIAS(IntDefaultHandler);
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void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
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void PLL1_IRQHandler(void) ALIAS(IntDefaultHandler);
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void USBActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
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void CANActivity_IRQHandler(void) ALIAS(IntDefaultHandler);
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#if defined (__USE_LPCOPEN)
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void SDIO_IRQHandler(void) ALIAS(IntDefaultHandler);
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#else
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void MCI_IRQHandler(void) ALIAS(IntDefaultHandler);
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#endif
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void UART4_IRQHandler(void) ALIAS(IntDefaultHandler);
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void SSP2_IRQHandler(void) ALIAS(IntDefaultHandler);
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void LCD_IRQHandler(void) ALIAS(IntDefaultHandler);
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void GPIO_IRQHandler(void) ALIAS(IntDefaultHandler);
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void PWM0_IRQHandler(void) ALIAS(IntDefaultHandler);
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void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
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//*****************************************************************************
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//
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// The entry point for the application.
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// __main() is the entry point for Redlib based applications
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// main() is the entry point for Newlib based applications
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//
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//*****************************************************************************
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#if defined (__REDLIB__)
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extern void __main(void);
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#endif
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extern int main(void);
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//*****************************************************************************
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//
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// External declaration for the pointer to the stack top from the Linker Script
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//
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//*****************************************************************************
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extern void _vStackTop(void);
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//*****************************************************************************
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#if defined (__cplusplus)
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} // extern "C"
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#endif
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//*****************************************************************************
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//
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// The vector table.
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// This relies on the linker script to place at correct location in memory.
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//
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//*****************************************************************************
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extern void (* const g_pfnVectors[])(void);
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__attribute__ ((section(".isr_vector")))
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void (* const g_pfnVectors[])(void) = {
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// Core Level - CM4
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&_vStackTop, // The initial stack pointer
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ResetISR, // The reset handler
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NMI_Handler, // The NMI handler
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HardFault_Handler, // The hard fault handler
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MemManage_Handler, // The MPU fault handler
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BusFault_Handler, // The bus fault handler
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UsageFault_Handler, // The usage fault handler
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0, // Reserved
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0, // Reserved
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0, // Reserved
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0, // Reserved
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SVC_Handler, // SVCall handler
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DebugMon_Handler, // Debug monitor handler
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0, // Reserved
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PendSV_Handler, // The PendSV handler
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SysTick_Handler, // The SysTick handler
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// Chip Level - LPC40xx
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WDT_IRQHandler, // 16, 0x40 - WDT
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TIMER0_IRQHandler, // 17, 0x44 - TIMER0
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TIMER1_IRQHandler, // 18, 0x48 - TIMER1
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TIMER2_IRQHandler, // 19, 0x4c - TIMER2
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TIMER3_IRQHandler, // 20, 0x50 - TIMER3
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UART0_IRQHandler, // 21, 0x54 - UART0
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UART1_IRQHandler, // 22, 0x58 - UART1
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UART2_IRQHandler, // 23, 0x5c - UART2
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UART3_IRQHandler, // 24, 0x60 - UART3
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PWM1_IRQHandler, // 25, 0x64 - PWM1
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I2C0_IRQHandler, // 26, 0x68 - I2C0
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I2C1_IRQHandler, // 27, 0x6c - I2C1
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I2C2_IRQHandler, // 28, 0x70 - I2C2
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IntDefaultHandler, // 29, Not used
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SSP0_IRQHandler, // 30, 0x78 - SSP0
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SSP1_IRQHandler, // 31, 0x7c - SSP1
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PLL0_IRQHandler, // 32, 0x80 - PLL0 (Main PLL)
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RTC_IRQHandler, // 33, 0x84 - RTC
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EINT0_IRQHandler, // 34, 0x88 - EINT0
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EINT1_IRQHandler, // 35, 0x8c - EINT1
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EINT2_IRQHandler, // 36, 0x90 - EINT2
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EINT3_IRQHandler, // 37, 0x94 - EINT3
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ADC_IRQHandler, // 38, 0x98 - ADC
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BOD_IRQHandler, // 39, 0x9c - BOD
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USB_IRQHandler, // 40, 0xA0 - USB
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CAN_IRQHandler, // 41, 0xa4 - CAN
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DMA_IRQHandler, // 42, 0xa8 - GP DMA
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I2S_IRQHandler, // 43, 0xac - I2S
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#if defined (__USE_LPCOPEN)
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ETH_IRQHandler, // 44, 0xb0 - Ethernet
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SDIO_IRQHandler, // 45, 0xb4 - SD/MMC card I/F
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#else
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ENET_IRQHandler, // 44, 0xb0 - Ethernet
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MCI_IRQHandler, // 45, 0xb4 - SD/MMC card I/F
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#endif
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MCPWM_IRQHandler, // 46, 0xb8 - Motor Control PWM
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QEI_IRQHandler, // 47, 0xbc - Quadrature Encoder
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PLL1_IRQHandler, // 48, 0xc0 - PLL1 (USB PLL)
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USBActivity_IRQHandler, // 49, 0xc4 - USB Activity interrupt to wakeup
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CANActivity_IRQHandler, // 50, 0xc8 - CAN Activity interrupt to wakeup
|
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UART4_IRQHandler, // 51, 0xcc - UART4
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SSP2_IRQHandler, // 52, 0xd0 - SSP2
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LCD_IRQHandler, // 53, 0xd4 - LCD
|
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GPIO_IRQHandler, // 54, 0xd8 - GPIO
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PWM0_IRQHandler, // 55, 0xdc - PWM0
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EEPROM_IRQHandler, // 56, 0xe0 - EEPROM
|
||||||
|
|
||||||
|
};
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|
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//*****************************************************************************
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|
// Functions to carry out the initialization of RW and BSS data sections. These
|
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|
// are written as separate functions rather than being inlined within the
|
||||||
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// ResetISR() function in order to cope with MCUs with multiple banks of
|
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// memory.
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//*****************************************************************************
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__attribute__ ((section(".after_vectors")))
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void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
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unsigned int *pulDest = (unsigned int*) start;
|
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|
unsigned int *pulSrc = (unsigned int*) romstart;
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|
unsigned int loop;
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for (loop = 0; loop < len; loop = loop + 4)
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|
*pulDest++ = *pulSrc++;
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|
}
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||||||
|
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||||||
|
__attribute__ ((section(".after_vectors")))
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|
void bss_init(unsigned int start, unsigned int len) {
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|
unsigned int *pulDest = (unsigned int*) start;
|
||||||
|
unsigned int loop;
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|
for (loop = 0; loop < len; loop = loop + 4)
|
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|
*pulDest++ = 0;
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||||||
|
}
|
||||||
|
|
||||||
|
//*****************************************************************************
|
||||||
|
// The following symbols are constructs generated by the linker, indicating
|
||||||
|
// the location of various points in the "Global Section Table". This table is
|
||||||
|
// created by the linker via the Code Red managed linker script mechanism. It
|
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|
// contains the load address, execution address and length of each RW data
|
||||||
|
// section and the execution and length of each BSS (zero initialized) section.
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||||||
|
//*****************************************************************************
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|
extern unsigned int __data_section_table;
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||||||
|
extern unsigned int __data_section_table_end;
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|
extern unsigned int __bss_section_table;
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||||||
|
extern unsigned int __bss_section_table_end;
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||||||
|
|
||||||
|
//*****************************************************************************
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||||||
|
// Reset entry point for your code.
|
||||||
|
// Sets up a simple runtime environment and initializes the C/C++
|
||||||
|
// library.
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||||||
|
//*****************************************************************************
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|
__attribute__ ((section(".after_vectors")))
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|
void
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|
ResetISR(void) {
|
||||||
|
|
||||||
|
//
|
||||||
|
// Copy the data sections from flash to SRAM.
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||||||
|
//
|
||||||
|
unsigned int LoadAddr, ExeAddr, SectionLen;
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|
unsigned int *SectionTableAddr;
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|
|
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|
// Load base address of Global Section Table
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|
SectionTableAddr = &__data_section_table;
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|
|
||||||
|
// Copy the data sections from flash to SRAM.
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||||||
|
while (SectionTableAddr < &__data_section_table_end) {
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|
LoadAddr = *SectionTableAddr++;
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||||||
|
ExeAddr = *SectionTableAddr++;
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|
SectionLen = *SectionTableAddr++;
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|
data_init(LoadAddr, ExeAddr, SectionLen);
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|
}
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||||||
|
// At this point, SectionTableAddr = &__bss_section_table;
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|
// Zero fill the bss segment
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||||||
|
while (SectionTableAddr < &__bss_section_table_end) {
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||||||
|
ExeAddr = *SectionTableAddr++;
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|
SectionLen = *SectionTableAddr++;
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||||||
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bss_init(ExeAddr, SectionLen);
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|
}
|
||||||
|
|
||||||
|
#if defined (__VFP_FP__) && !defined (__SOFTFP__)
|
||||||
|
/*
|
||||||
|
* Code to enable the Cortex-M4 FPU only included
|
||||||
|
* if appropriate build options have been selected.
|
||||||
|
* Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
|
||||||
|
*/
|
||||||
|
// Read CPACR (located at address 0xE000ED88)
|
||||||
|
// Set bits 20-23 to enable CP10 and CP11 coprocessors
|
||||||
|
// Write back the modified value to the CPACR
|
||||||
|
asm volatile ("LDR.W R0, =0xE000ED88\n\t"
|
||||||
|
"LDR R1, [R0]\n\t"
|
||||||
|
"ORR R1, R1, #(0xF << 20)\n\t"
|
||||||
|
"STR R1, [R0]");
|
||||||
|
#endif // (__VFP_FP__) && !(__SOFTFP__)
|
||||||
|
|
||||||
|
// Check to see if we are running the code from a non-zero
|
||||||
|
// address (eg RAM, external flash), in which case we need
|
||||||
|
// to modify the VTOR register to tell the CPU that the
|
||||||
|
// vector table is located at a non-0x0 address.
|
||||||
|
|
||||||
|
// Note that we do not use the CMSIS register access mechanism,
|
||||||
|
// as there is no guarantee that the project has been configured
|
||||||
|
// to use CMSIS.
|
||||||
|
unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
|
||||||
|
if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
|
||||||
|
// CMSIS : SCB->VTOR = <address of vector table>
|
||||||
|
*pSCB_VTOR = (unsigned int)g_pfnVectors;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined (__USE_CMSIS) || defined (__USE_LPCOPEN)
|
||||||
|
SystemInit();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined (__cplusplus)
|
||||||
|
//
|
||||||
|
// Call C++ library initialisation
|
||||||
|
//
|
||||||
|
__libc_init_array();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined (__REDLIB__)
|
||||||
|
// Call the Redlib library, which in turn calls main()
|
||||||
|
__main() ;
|
||||||
|
#else
|
||||||
|
main();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//
|
||||||
|
// main() shouldn't return, but if it does, we'll just enter an infinite loop
|
||||||
|
//
|
||||||
|
while (1) {
|
||||||
|
;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
//*****************************************************************************
|
||||||
|
// Default exception handlers. Override the ones here by defining your own
|
||||||
|
// handler routines in your application code.
|
||||||
|
//*****************************************************************************
|
||||||
|
__attribute__ ((section(".after_vectors")))
|
||||||
|
void NMI_Handler(void)
|
||||||
|
{ while(1) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__ ((section(".after_vectors")))
|
||||||
|
void HardFault_Handler(void)
|
||||||
|
{ while(1) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__ ((section(".after_vectors")))
|
||||||
|
void MemManage_Handler(void)
|
||||||
|
{ while(1) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__ ((section(".after_vectors")))
|
||||||
|
void BusFault_Handler(void)
|
||||||
|
{ while(1) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__ ((section(".after_vectors")))
|
||||||
|
void UsageFault_Handler(void)
|
||||||
|
{ while(1) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__ ((section(".after_vectors")))
|
||||||
|
void SVC_Handler(void)
|
||||||
|
{ while(1) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__ ((section(".after_vectors")))
|
||||||
|
void DebugMon_Handler(void)
|
||||||
|
{ while(1) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__ ((section(".after_vectors")))
|
||||||
|
void PendSV_Handler(void)
|
||||||
|
{ while(1) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
__attribute__ ((section(".after_vectors")))
|
||||||
|
void SysTick_Handler(void)
|
||||||
|
{ while(1) {}
|
||||||
|
}
|
||||||
|
|
||||||
|
//*****************************************************************************
|
||||||
|
//
|
||||||
|
// Processor ends up here if an unexpected interrupt occurs or a specific
|
||||||
|
// handler is not present in the application code.
|
||||||
|
//
|
||||||
|
//*****************************************************************************
|
||||||
|
__attribute__ ((section(".after_vectors")))
|
||||||
|
void IntDefaultHandler(void)
|
||||||
|
{ while(1) {}
|
||||||
|
}
|
||||||
184
hw/bsp/ea4088qs/lpc4088.ld
Normal file
184
hw/bsp/ea4088qs/lpc4088.ld
Normal file
@ -0,0 +1,184 @@
|
|||||||
|
/*
|
||||||
|
* GENERATED FILE - DO NOT EDIT
|
||||||
|
* (c) Code Red Technologies Ltd, 2008-2013
|
||||||
|
* (c) NXP Semiconductors 2013-2019
|
||||||
|
* Generated linker script file for LPC4088
|
||||||
|
* Created from linkscript.ldt by FMCreateLinkLibraries
|
||||||
|
* Using Freemarker v2.3.23
|
||||||
|
* MCUXpresso IDE v10.2.1 [Build 795] [2018-07-25] on May 15, 2019 5:16:07 PM
|
||||||
|
*/
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
/* Define each memory region */
|
||||||
|
MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512K bytes (alias Flash) */
|
||||||
|
RamLoc64 (rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000 /* 64K bytes (alias RAM) */
|
||||||
|
RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32K bytes (alias RAM2) */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Define a symbol for the top of each memory region */
|
||||||
|
__base_MFlash512 = 0x0 ; /* MFlash512 */
|
||||||
|
__base_Flash = 0x0 ; /* Flash */
|
||||||
|
__top_MFlash512 = 0x0 + 0x80000 ; /* 512K bytes */
|
||||||
|
__top_Flash = 0x0 + 0x80000 ; /* 512K bytes */
|
||||||
|
__base_RamLoc64 = 0x10000000 ; /* RamLoc64 */
|
||||||
|
__base_RAM = 0x10000000 ; /* RAM */
|
||||||
|
__top_RamLoc64 = 0x10000000 + 0x10000 ; /* 64K bytes */
|
||||||
|
__top_RAM = 0x10000000 + 0x10000 ; /* 64K bytes */
|
||||||
|
__base_RamPeriph32 = 0x20000000 ; /* RamPeriph32 */
|
||||||
|
__base_RAM2 = 0x20000000 ; /* RAM2 */
|
||||||
|
__top_RamPeriph32 = 0x20000000 + 0x8000 ; /* 32K bytes */
|
||||||
|
__top_RAM2 = 0x20000000 + 0x8000 ; /* 32K bytes */
|
||||||
|
|
||||||
|
ENTRY(ResetISR)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
/* MAIN TEXT SECTION */
|
||||||
|
.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
FILL(0xff)
|
||||||
|
__vectors_start__ = ABSOLUTE(.) ;
|
||||||
|
KEEP(*(.isr_vector))
|
||||||
|
/* Global Section Table */
|
||||||
|
. = ALIGN(4) ;
|
||||||
|
__section_table_start = .;
|
||||||
|
__data_section_table = .;
|
||||||
|
LONG(LOADADDR(.data));
|
||||||
|
LONG( ADDR(.data));
|
||||||
|
LONG( SIZEOF(.data));
|
||||||
|
LONG(LOADADDR(.data_RAM2));
|
||||||
|
LONG( ADDR(.data_RAM2));
|
||||||
|
LONG( SIZEOF(.data_RAM2));
|
||||||
|
__data_section_table_end = .;
|
||||||
|
__bss_section_table = .;
|
||||||
|
LONG( ADDR(.bss));
|
||||||
|
LONG( SIZEOF(.bss));
|
||||||
|
LONG( ADDR(.bss_RAM2));
|
||||||
|
LONG( SIZEOF(.bss_RAM2));
|
||||||
|
__bss_section_table_end = .;
|
||||||
|
__section_table_end = . ;
|
||||||
|
/* End of Global Section Table */
|
||||||
|
|
||||||
|
*(.after_vectors*)
|
||||||
|
|
||||||
|
} > MFlash512
|
||||||
|
|
||||||
|
.text : ALIGN(4)
|
||||||
|
{
|
||||||
|
*(.text*)
|
||||||
|
*(.rodata .rodata.* .constdata .constdata.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > MFlash512
|
||||||
|
/*
|
||||||
|
* for exception handling/unwind - some Newlib functions (in common
|
||||||
|
* with C++ and STDC++) use this.
|
||||||
|
*/
|
||||||
|
.ARM.extab : ALIGN(4)
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} > MFlash512
|
||||||
|
|
||||||
|
__exidx_start = .;
|
||||||
|
|
||||||
|
.ARM.exidx : ALIGN(4)
|
||||||
|
{
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
} > MFlash512
|
||||||
|
__exidx_end = .;
|
||||||
|
|
||||||
|
_etext = .;
|
||||||
|
|
||||||
|
/* DATA section for RamPeriph32 */
|
||||||
|
|
||||||
|
.data_RAM2 : ALIGN(4)
|
||||||
|
{
|
||||||
|
FILL(0xff)
|
||||||
|
PROVIDE(__start_data_RAM2 = .) ;
|
||||||
|
*(.ramfunc.$RAM2)
|
||||||
|
*(.ramfunc.$RamPeriph32)
|
||||||
|
*(.data.$RAM2*)
|
||||||
|
*(.data.$RamPeriph32*)
|
||||||
|
. = ALIGN(4) ;
|
||||||
|
PROVIDE(__end_data_RAM2 = .) ;
|
||||||
|
} > RamPeriph32 AT>MFlash512
|
||||||
|
/* MAIN DATA SECTION */
|
||||||
|
.uninit_RESERVED : ALIGN(4)
|
||||||
|
{
|
||||||
|
KEEP(*(.bss.$RESERVED*))
|
||||||
|
. = ALIGN(4) ;
|
||||||
|
_end_uninit_RESERVED = .;
|
||||||
|
} > RamLoc64
|
||||||
|
|
||||||
|
/* Main DATA section (RamLoc64) */
|
||||||
|
.data : ALIGN(4)
|
||||||
|
{
|
||||||
|
FILL(0xff)
|
||||||
|
_data = . ;
|
||||||
|
*(vtable)
|
||||||
|
*(.ramfunc*)
|
||||||
|
*(.data*)
|
||||||
|
. = ALIGN(4) ;
|
||||||
|
_edata = . ;
|
||||||
|
} > RamLoc64 AT>MFlash512
|
||||||
|
|
||||||
|
/* BSS section for RamPeriph32 */
|
||||||
|
.bss_RAM2 : ALIGN(4)
|
||||||
|
{
|
||||||
|
PROVIDE(__start_bss_RAM2 = .) ;
|
||||||
|
*(.bss.$RAM2*)
|
||||||
|
*(.bss.$RamPeriph32*)
|
||||||
|
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
|
||||||
|
PROVIDE(__end_bss_RAM2 = .) ;
|
||||||
|
} > RamPeriph32
|
||||||
|
|
||||||
|
/* MAIN BSS SECTION */
|
||||||
|
.bss : ALIGN(4)
|
||||||
|
{
|
||||||
|
_bss = .;
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
. = ALIGN(4) ;
|
||||||
|
_ebss = .;
|
||||||
|
PROVIDE(end = .);
|
||||||
|
} > RamLoc64
|
||||||
|
|
||||||
|
/* NOINIT section for RamPeriph32 */
|
||||||
|
.noinit_RAM2 (NOLOAD) : ALIGN(4)
|
||||||
|
{
|
||||||
|
*(.noinit.$RAM2*)
|
||||||
|
*(.noinit.$RamPeriph32*)
|
||||||
|
. = ALIGN(4) ;
|
||||||
|
} > RamPeriph32
|
||||||
|
|
||||||
|
/* DEFAULT NOINIT SECTION */
|
||||||
|
.noinit (NOLOAD): ALIGN(4)
|
||||||
|
{
|
||||||
|
_noinit = .;
|
||||||
|
*(.noinit*)
|
||||||
|
. = ALIGN(4) ;
|
||||||
|
_end_noinit = .;
|
||||||
|
} > RamLoc64
|
||||||
|
PROVIDE(_pvHeapStart = DEFINED(__user_heap_base) ? __user_heap_base : .);
|
||||||
|
PROVIDE(_vStackTop = DEFINED(__user_stack_top) ? __user_stack_top : __top_RamLoc64 - 0);
|
||||||
|
|
||||||
|
/* ## Create checksum value (used in startup) ## */
|
||||||
|
PROVIDE(__valid_user_code_checksum = 0 -
|
||||||
|
(_vStackTop
|
||||||
|
+ (ResetISR + 1)
|
||||||
|
+ (NMI_Handler + 1)
|
||||||
|
+ (HardFault_Handler + 1)
|
||||||
|
+ (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1) /* MemManage_Handler may not be defined */
|
||||||
|
+ (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1) /* BusFault_Handler may not be defined */
|
||||||
|
+ (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined */
|
||||||
|
) );
|
||||||
|
|
||||||
|
/* Provide basic symbols giving location and size of main text
|
||||||
|
* block, including initial values of RW data sections. Note that
|
||||||
|
* these will need extending to give a complete picture with
|
||||||
|
* complex images (e.g multiple Flash banks).
|
||||||
|
*/
|
||||||
|
_image_start = LOADADDR(.text);
|
||||||
|
_image_end = LOADADDR(.data) + SIZEOF(.data);
|
||||||
|
_image_size = _image_end - _image_start;
|
||||||
|
}
|
||||||
@ -13,7 +13,7 @@ fail_count = 0
|
|||||||
exit_status = 0
|
exit_status = 0
|
||||||
|
|
||||||
all_device_example = ["cdc_msc_hid", "msc_dual_lun", "hid_generic_inout"]
|
all_device_example = ["cdc_msc_hid", "msc_dual_lun", "hid_generic_inout"]
|
||||||
all_boards = ["metro_m0_express", "metro_m4_express", "pca10056", "feather_nrf52840_express", "stm32f407g_disc1", "lpcxpresso11u68", "lpcxpresso1347", "lpcxpresso1769", "mcb1800"]
|
all_boards = ["metro_m0_express", "metro_m4_express", "pca10056", "feather_nrf52840_express", "stm32f407g_disc1", "lpcxpresso11u68", "lpcxpresso1347", "lpcxpresso1769", "mcb1800", "ea4088qs"]
|
||||||
|
|
||||||
def build_example(example, board):
|
def build_example(example, board):
|
||||||
subprocess.run("make -C examples/device/{} BOARD={} clean".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
|
subprocess.run("make -C examples/device/{} BOARD={} clean".format(example, board), shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT)
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user