From 12e96ce571e3ca8d9771d4729eb65bd296acb72e Mon Sep 17 00:00:00 2001 From: hathach <thach@tinyusb.org> Date: Mon, 15 Nov 2021 12:18:28 +0700 Subject: [PATCH] set DCFG_XCVRDLY when using external ULPI highspeed phy --- src/portable/synopsys/dwc2/dcd_dwc2.c | 4 ++++ src/portable/synopsys/dwc2/dwc2_type.h | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 44a5f8932..30b8aed69 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -444,6 +444,10 @@ static void phy_hs_init(dwc2_regs_t * dwc2) // Set max speed dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_HS << DCFG_DSPD_Pos); + + // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required + // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) + if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dwc2->dcfg |= DCFG_XCVRDLY; } static bool check_dwc2(dwc2_regs_t * dwc2) diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 6e52ebc7b..dbef20314 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -416,6 +416,10 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DCFG_PFIVL_0 (0x1UL << DCFG_PFIVL_Pos) // 0x00000800 */ #define DCFG_PFIVL_1 (0x2UL << DCFG_PFIVL_Pos) // 0x00001000 */ +#define DCFG_XCVRDLY_Pos (14U) +#define DCFG_XCVRDLY_Msk (0x1UL << DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define DCFG_XCVRDLY DCFG_XCVRDLY_Msk // Enables delay between xcvr_sel and txvalid during device chirp + #define DCFG_PERSCHIVL_Pos (24U) #define DCFG_PERSCHIVL_Msk (0x3UL << DCFG_PERSCHIVL_Pos) // 0x03000000 */ #define DCFG_PERSCHIVL DCFG_PERSCHIVL_Msk // Periodic scheduling interval */