mirror of
https://github.com/hathach/tinyusb.git
synced 2025-03-14 04:18:56 +00:00
adding hcd dwc2
This commit is contained in:
parent
933ac29d77
commit
10a3aa3cc8
@ -4,3 +4,4 @@ board:mcb1800
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mcu:RP2040
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mcu:ra6m5
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mcu:MAX3421
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mcu:STM32H7
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@ -4,3 +4,4 @@ board:mcb1800
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mcu:RP2040
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mcu:ra6m5
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mcu:MAX3421
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mcu:STM32H7
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@ -12,3 +12,4 @@ mcu:MSP432E4
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mcu:RP2040
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mcu:RX65X
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mcu:RAXXX
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mcu:STM32H7
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@ -151,7 +151,7 @@ void board_init(void) {
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HAL_UART_Init(&UartHandle);
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#endif
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#if BOARD_TUD_RHPORT == 0
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//------------- USB FS -------------//
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// Despite being call USB2_OTG
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// OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port
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// PA9 VUSB, PA10 ID, PA11 DM, PA12 DP
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@ -195,10 +195,9 @@ void board_init(void) {
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USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
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#endif // vbus sense
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#elif BOARD_TUD_RHPORT == 1
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//------------- USB HS -------------//
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// Despite being call USB2_OTG
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// OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port
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struct {
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GPIO_TypeDef* port;
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uint32_t pin;
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@ -238,8 +237,6 @@ void board_init(void) {
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// For waveshare openh743 ULPI PHY reset walkaround
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board_stm32h7_post_init();
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#endif // rhport = 1
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}
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//--------------------------------------------------------------------+
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@ -106,6 +106,8 @@ function(family_configure_example TARGET RTOS)
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family_add_tinyusb(${TARGET} OPT_MCU_STM32H7 ${RTOS})
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target_sources(${TARGET}-tinyusb PUBLIC
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${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c
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${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c
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${TOP}/src/portable/synopsys/dwc2/dwc2_common.c
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)
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target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD})
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@ -35,45 +35,7 @@
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#define DWC2_DEBUG 2
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#include "device/dcd.h"
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#include "dwc2_type.h"
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// Following symbols must be defined by port header
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// - _dwc2_controller[]: array of controllers
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// - DWC2_EP_MAX: largest EP counts of all controllers
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// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset
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// - dwc2_dcd_int_enable/dwc2_dcd_int_disable
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// - dwc2_remote_wakeup_delay
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#if defined(TUP_USBIP_DWC2_STM32)
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#include "dwc2_stm32.h"
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#elif defined(TUP_USBIP_DWC2_ESP32)
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#include "dwc2_esp32.h"
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#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
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#include "dwc2_gd32.h"
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#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
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#include "dwc2_bcm.h"
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#elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
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#include "dwc2_efm32.h"
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#elif TU_CHECK_MCU(OPT_MCU_XMC4000)
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#include "dwc2_xmc.h"
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#else
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#error "Unsupported MCUs"
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#endif
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enum {
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DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller)
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};
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// DWC2 registers
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//#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base)
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TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
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if (rhport >= DWC2_CONTROLLER_COUNT) {
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// user mis-configured, ignore and use first controller
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rhport = 0;
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}
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return (dwc2_regs_t*) _dwc2_controller[rhport].reg_base;
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}
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#include "dwc2_common.h"
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM
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@ -511,162 +473,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c
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}
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}
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/*------------------------------------------------------------------*/
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/* Controller API
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*------------------------------------------------------------------*/
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static void reset_core(dwc2_regs_t* dwc2) {
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// reset core
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dwc2->grstctl |= GRSTCTL_CSRST;
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// wait for reset bit is cleared
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// TODO version 4.20a should wait for RESET DONE mask
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while (dwc2->grstctl & GRSTCTL_CSRST) {}
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// wait for AHB master IDLE
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while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {}
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// wait for device mode ?
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}
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static bool phy_hs_supported(dwc2_regs_t* dwc2) {
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(void) dwc2;
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#if !TUD_OPT_HIGH_SPEED
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return false;
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#else
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return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
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#endif
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}
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static void phy_fs_init(dwc2_regs_t* dwc2) {
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TU_LOG(DWC2_DEBUG, "Fullspeed PHY init\r\n");
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// Select FS PHY
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dwc2->gusbcfg |= GUSBCFG_PHYSEL;
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// MCU specific PHY init before reset
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dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
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// Reset core after selecting PHY
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reset_core(dwc2);
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// USB turnaround time is critical for certification where long cables and 5-Hubs are used.
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// So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
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// these bits can be programmed to a larger value. Default is 5
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dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
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// MCU specific PHY update post reset
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dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
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// set max speed
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dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
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}
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static void phy_hs_init(dwc2_regs_t* dwc2) {
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uint32_t gusbcfg = dwc2->gusbcfg;
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// De-select FS PHY
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gusbcfg &= ~GUSBCFG_PHYSEL;
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if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
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TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n");
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// Select ULPI
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gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
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// ULPI 8-bit interface, single data rate
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gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
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// default internal VBUS Indicator and Drive
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gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
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// Disable FS/LS ULPI
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gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
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} else {
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TU_LOG(DWC2_DEBUG, "Highspeed UTMI+ PHY init\r\n");
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// Select UTMI+ with 8-bit interface
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gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
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// Set 16-bit interface if supported
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if (dwc2->ghwcfg4_bm.phy_data_width) {
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gusbcfg |= GUSBCFG_PHYIF16;
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}
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}
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// Apply config
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dwc2->gusbcfg = gusbcfg;
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// mcu specific phy init
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dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
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// Reset core after selecting PHY
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reset_core(dwc2);
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// Set turn-around, must after core reset otherwise it will be clear
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// - 9 if using 8-bit PHY interface
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// - 5 if using 16-bit PHY interface
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gusbcfg &= ~GUSBCFG_TRDT_Msk;
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gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
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dwc2->gusbcfg = gusbcfg;
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// MCU specific PHY update post reset
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dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
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// Set max speed
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uint32_t dcfg = dwc2->dcfg;
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dcfg &= ~DCFG_DSPD_Msk;
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dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
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// XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
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// when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
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if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
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dcfg |= DCFG_XCVRDLY;
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}
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dwc2->dcfg = dcfg;
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}
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static bool check_dwc2(dwc2_regs_t* dwc2) {
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#if CFG_TUSB_DEBUG >= DWC2_DEBUG
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// print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
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// Run 'python dwc2_info.py' and check dwc2_info.md for bit-field value and comparison with other ports
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volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
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TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
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for (size_t i = 0; i < 5; i++) {
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TU_LOG1("0x%08" PRIX32 ", ", p[i]);
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}
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TU_LOG1("0x%08" PRIX32 "\r\n", p[5]);
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#endif
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// For some reason: GD32VF103 snpsid and all hwcfg register are always zero (skip it)
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(void) dwc2;
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#if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
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uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
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TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID);
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#endif
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return true;
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}
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//--------------------------------------------------------------------
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// Controller API
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//--------------------------------------------------------------------
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bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
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(void) rhport;
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(void) rh_init;
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// Programming model begins in the last section of the chapter on the USB
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// peripheral in each Reference Manual.
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dwc2_regs_t* dwc2 = DWC2_REG(rhport);
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// Check Synopsys ID register, failed if controller clock/power is not enabled
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TU_ASSERT(check_dwc2(dwc2));
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TU_ASSERT(dwc2_controller_init(rhport, rh_init));
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dcd_disconnect(rhport);
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if (phy_hs_supported(dwc2)) {
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phy_hs_init(dwc2); // Highspeed
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} else {
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phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present
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}
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// Restart PHY clock
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dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE);
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196
src/portable/synopsys/dwc2/dwc2_common.c
Normal file
196
src/portable/synopsys/dwc2/dwc2_common.c
Normal file
@ -0,0 +1,196 @@
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2024 Ha Thach (tinyusb.org)
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
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#include "tusb_option.h"
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#define DWC2_COMMON_DEBUG 2
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#if defined(TUP_USBIP_DWC2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED)
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#include "common/tusb_common.h"
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#include "dwc2_common.h"
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static void reset_core(dwc2_regs_t* dwc2) {
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// reset core
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dwc2->grstctl |= GRSTCTL_CSRST;
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// wait for reset bit is cleared
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// TODO version 4.20a should wait for RESET DONE mask
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while (dwc2->grstctl & GRSTCTL_CSRST) {}
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// wait for AHB master IDLE
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while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {}
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// wait for device mode ?
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}
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static bool phy_hs_supported(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) {
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(void) dwc2;
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#if !TUD_OPT_HIGH_SPEED
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return false;
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#else
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return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED;
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#endif
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}
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static void phy_fs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) {
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TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n");
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// Select FS PHY
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dwc2->gusbcfg |= GUSBCFG_PHYSEL;
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// MCU specific PHY init before reset
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dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
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// Reset core after selecting PHY
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reset_core(dwc2);
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// USB turnaround time is critical for certification where long cables and 5-Hubs are used.
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// So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical,
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// these bits can be programmed to a larger value. Default is 5
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dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos);
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// MCU specific PHY update post reset
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dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED);
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// set max speed
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dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos);
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}
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static void phy_hs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) {
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uint32_t gusbcfg = dwc2->gusbcfg;
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// De-select FS PHY
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gusbcfg &= ~GUSBCFG_PHYSEL;
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if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
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TU_LOG(DWC2_COMMON_DEBUG, "Highspeed ULPI PHY init\r\n");
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// Select ULPI PHY (external)
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gusbcfg |= GUSBCFG_ULPI_UTMI_SEL;
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// ULPI is always 8-bit interface
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gusbcfg &= ~GUSBCFG_PHYIF16;
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// ULPI select single data rate
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gusbcfg &= ~GUSBCFG_DDRSEL;
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// default internal VBUS Indicator and Drive
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gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI);
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// Disable FS/LS ULPI
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gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM);
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} else {
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TU_LOG(DWC2_COMMON_DEBUG, "Highspeed UTMI+ PHY init\r\n");
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// Select UTMI+ PHY (internal)
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gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL;
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// Set 16-bit interface if supported
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if (dwc2->ghwcfg4_bm.phy_data_width) {
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gusbcfg |= GUSBCFG_PHYIF16; // 16 bit
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}else {
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gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit
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}
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}
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// Apply config
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dwc2->gusbcfg = gusbcfg;
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// mcu specific phy init
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dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
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// Reset core after selecting PHY
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reset_core(dwc2);
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// Set turn-around, must after core reset otherwise it will be clear
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// - 9 if using 8-bit PHY interface
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// - 5 if using 16-bit PHY interface
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gusbcfg &= ~GUSBCFG_TRDT_Msk;
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gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos;
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dwc2->gusbcfg = gusbcfg;
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// MCU specific PHY update post reset
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dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type);
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// Set max speed
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uint32_t dcfg = dwc2->dcfg;
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dcfg &= ~DCFG_DSPD_Msk;
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dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos;
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||||
|
||||
// XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required
|
||||
// when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347)
|
||||
if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) {
|
||||
dcfg |= DCFG_XCVRDLY;
|
||||
}
|
||||
|
||||
dwc2->dcfg = dcfg;
|
||||
}
|
||||
|
||||
static bool check_dwc2(dwc2_regs_t* dwc2) {
|
||||
#if CFG_TUSB_DEBUG >= DWC2_COMMON_DEBUG
|
||||
// print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4
|
||||
// Run 'python dwc2_info.py' and check dwc2_info.md for bit-field value and comparison with other ports
|
||||
volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid;
|
||||
TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n");
|
||||
for (size_t i = 0; i < 5; i++) {
|
||||
TU_LOG1("0x%08" PRIX32 ", ", p[i]);
|
||||
}
|
||||
TU_LOG1("0x%08" PRIX32 "\r\n", p[5]);
|
||||
#endif
|
||||
|
||||
// For some reason: GD32VF103 gsnpsid and all hwcfg register are always zero (skip it)
|
||||
(void) dwc2;
|
||||
#if !TU_CHECK_MCU(OPT_MCU_GD32VF103)
|
||||
uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK;
|
||||
TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID);
|
||||
#endif
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------
|
||||
//
|
||||
//--------------------------------------------------------------------
|
||||
bool dwc2_controller_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
|
||||
(void) rh_init;
|
||||
dwc2_regs_t* dwc2 = DWC2_REG(rhport);
|
||||
|
||||
// Check Synopsys ID register, failed if controller clock/power is not enabled
|
||||
TU_ASSERT(check_dwc2(dwc2));
|
||||
|
||||
if (phy_hs_supported(dwc2, rh_init)) {
|
||||
phy_hs_init(dwc2, rh_init); // Highspeed
|
||||
} else {
|
||||
phy_fs_init(dwc2, rh_init); // core does not support highspeed or hs phy is not present
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
#endif
|
70
src/portable/synopsys/dwc2/dwc2_common.h
Normal file
70
src/portable/synopsys/dwc2/dwc2_common.h
Normal file
@ -0,0 +1,70 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2024 Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#ifndef TUSB_DWC2_COMMON_H
|
||||
#define TUSB_DWC2_COMMON_H
|
||||
|
||||
#include "dwc2_type.h"
|
||||
|
||||
// Following symbols must be defined by port header
|
||||
// - _dwc2_controller[]: array of controllers
|
||||
// - DWC2_EP_MAX: largest EP counts of all controllers
|
||||
// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset
|
||||
// - dwc2_dcd_int_enable/dwc2_dcd_int_disable
|
||||
// - dwc2_remote_wakeup_delay
|
||||
|
||||
#if defined(TUP_USBIP_DWC2_STM32)
|
||||
#include "dwc2_stm32.h"
|
||||
#elif defined(TUP_USBIP_DWC2_ESP32)
|
||||
#include "dwc2_esp32.h"
|
||||
#elif TU_CHECK_MCU(OPT_MCU_GD32VF103)
|
||||
#include "dwc2_gd32.h"
|
||||
#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837)
|
||||
#include "dwc2_bcm.h"
|
||||
#elif TU_CHECK_MCU(OPT_MCU_EFM32GG)
|
||||
#include "dwc2_efm32.h"
|
||||
#elif TU_CHECK_MCU(OPT_MCU_XMC4000)
|
||||
#include "dwc2_xmc.h"
|
||||
#else
|
||||
#error "Unsupported MCUs"
|
||||
#endif
|
||||
|
||||
enum {
|
||||
DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller)
|
||||
};
|
||||
|
||||
TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) {
|
||||
if (rhport >= DWC2_CONTROLLER_COUNT) {
|
||||
// user mis-configured, ignore and use first controller
|
||||
rhport = 0;
|
||||
}
|
||||
return (dwc2_regs_t*)_dwc2_controller[rhport].reg_base;
|
||||
}
|
||||
|
||||
|
||||
bool dwc2_controller_init(uint8_t rhport, const tusb_rhport_init_t* rh_init);
|
||||
|
||||
#endif
|
@ -31,8 +31,8 @@
|
||||
* opensource.org/licenses/BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _TUSB_DWC2_TYPES_H_
|
||||
#define _TUSB_DWC2_TYPES_H_
|
||||
#ifndef TUSB_DWC2_TYPES_H_
|
||||
#define TUSB_DWC2_TYPES_H_
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
|
167
src/portable/synopsys/dwc2/hcd_dwc2.c
Normal file
167
src/portable/synopsys/dwc2/hcd_dwc2.c
Normal file
@ -0,0 +1,167 @@
|
||||
/*
|
||||
* The MIT License (MIT)
|
||||
*
|
||||
* Copyright (c) 2024 Ha Thach (tinyusb.org)
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
* This file is part of the TinyUSB stack.
|
||||
*/
|
||||
|
||||
#include "tusb_option.h"
|
||||
|
||||
#if CFG_TUH_ENABLED && defined(TUP_USBIP_DWC2)
|
||||
|
||||
// Debug level for DWC2
|
||||
#define DWC2_DEBUG 2
|
||||
|
||||
#include "host/hcd.h"
|
||||
#include "dwc2_common.h"
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Controller API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// optional hcd configuration, called by tuh_configure()
|
||||
bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) {
|
||||
(void) rhport;
|
||||
(void) cfg_id;
|
||||
(void) cfg_param;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// Initialize controller to host mode
|
||||
bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) {
|
||||
(void) rhport;
|
||||
(void) rh_init;
|
||||
return false;
|
||||
}
|
||||
|
||||
// Interrupt Handler
|
||||
void hcd_int_handler(uint8_t rhport, bool in_isr) {
|
||||
(void) rhport;
|
||||
(void) in_isr;
|
||||
}
|
||||
|
||||
// Enable USB interrupt
|
||||
void hcd_int_enable (uint8_t rhport) {
|
||||
(void) rhport;
|
||||
}
|
||||
|
||||
// Disable USB interrupt
|
||||
void hcd_int_disable(uint8_t rhport) {
|
||||
(void) rhport;
|
||||
}
|
||||
|
||||
// Get frame number (1ms)
|
||||
uint32_t hcd_frame_number(uint8_t rhport) {
|
||||
(void) rhport;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Port API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// Get the current connect status of roothub port
|
||||
bool hcd_port_connect_status(uint8_t rhport) {
|
||||
(void) rhport;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete.
|
||||
// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence.
|
||||
void hcd_port_reset(uint8_t rhport) {
|
||||
(void) rhport;
|
||||
}
|
||||
|
||||
// Complete bus reset sequence, may be required by some controllers
|
||||
void hcd_port_reset_end(uint8_t rhport) {
|
||||
(void) rhport;
|
||||
}
|
||||
|
||||
// Get port link speed
|
||||
tusb_speed_t hcd_port_speed_get(uint8_t rhport) {
|
||||
(void) rhport;
|
||||
|
||||
return TUSB_SPEED_FULL;
|
||||
}
|
||||
|
||||
// HCD closes all opened endpoints belong to this device
|
||||
void hcd_device_close(uint8_t rhport, uint8_t dev_addr) {
|
||||
(void) rhport;
|
||||
(void) dev_addr;
|
||||
}
|
||||
|
||||
//--------------------------------------------------------------------+
|
||||
// Endpoints API
|
||||
//--------------------------------------------------------------------+
|
||||
|
||||
// Open an endpoint
|
||||
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) {
|
||||
(void) rhport;
|
||||
(void) dev_addr;
|
||||
(void) ep_desc;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked
|
||||
bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) {
|
||||
(void) rhport;
|
||||
(void) dev_addr;
|
||||
(void) ep_addr;
|
||||
(void) buffer;
|
||||
(void) buflen;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// Abort a queued transfer. Note: it can only abort transfer that has not been started
|
||||
// Return true if a queued transfer is aborted, false if there is no transfer to abort
|
||||
bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
|
||||
(void) rhport;
|
||||
(void) dev_addr;
|
||||
(void) ep_addr;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked
|
||||
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) {
|
||||
(void) rhport;
|
||||
(void) dev_addr;
|
||||
(void) setup_packet;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
// clear stall, data toggle is also reset to DATA0
|
||||
bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) {
|
||||
(void) rhport;
|
||||
(void) dev_addr;
|
||||
(void) ep_addr;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
#endif
|
Loading…
x
Reference in New Issue
Block a user