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https://github.com/hathach/tinyusb.git
synced 2025-04-16 05:42:56 +00:00
add actual_len supported
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8aedb2ff37
commit
102b99a0e8
@ -250,6 +250,7 @@ struct
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tuh_control_xfer_cb_t complete_cb;
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tuh_control_xfer_cb_t complete_cb;
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uintptr_t user_arg;
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uintptr_t user_arg;
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volatile uint16_t actual_len;
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uint8_t daddr; // device address that is transferring
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uint8_t daddr; // device address that is transferring
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volatile uint8_t stage;
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volatile uint8_t stage;
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}_ctrl_xfer;
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}_ctrl_xfer;
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@ -306,7 +307,7 @@ void osal_task_delay(uint32_t msec)
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#endif
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#endif
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// Descriptors
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// Descriptors Async
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
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static bool _get_descriptor(uint8_t daddr, uint8_t type, uint8_t index, uint16_t language_id, void* buffer, uint16_t len,
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@ -455,7 +456,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
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}
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}
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// Asynchronous
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// Descriptor Sync
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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#define _CONTROL_SYNC_API(_async_func, _timeout, ...) \
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#define _CONTROL_SYNC_API(_async_func, _timeout, ...) \
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@ -903,13 +904,13 @@ bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t* xfer)
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usbh_unlock();
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usbh_unlock();
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TU_VERIFY(is_idle);
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TU_VERIFY(is_idle);
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const uint8_t rhport = usbh_get_rhport(daddr);
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const uint8_t rhport = usbh_get_rhport(daddr);
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TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request");
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TU_LOG2("[%u:%u] %s: ", rhport, daddr, xfer->setup->bRequest <= TUSB_REQ_SYNCH_FRAME ? tu_str_std_request[xfer->setup->bRequest] : "Unknown Request");
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TU_LOG2_VAR(&xfer->setup);
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TU_LOG2_VAR(&xfer->setup);
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TU_LOG2("\r\n");
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TU_LOG2("\r\n");
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_ctrl_xfer.actual_len = 0;
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_ctrl_xfer.daddr = daddr;
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_ctrl_xfer.daddr = daddr;
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_ctrl_xfer.request = (*xfer->setup);
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_ctrl_xfer.request = (*xfer->setup);
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_ctrl_xfer.buffer = xfer->buffer;
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_ctrl_xfer.buffer = xfer->buffer;
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@ -941,8 +942,15 @@ bool tuh_control_xfer (uint8_t daddr, tuh_control_xfer_t* xfer)
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// TODO probably some timeout to prevent hanged
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// TODO probably some timeout to prevent hanged
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}
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}
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// update result
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// update xfer result
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//xfer->result = result;
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xfer->result = result;
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if ( xfer->user_arg )
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{
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// if user_arg is not NULL, it is also updated
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*((xfer_result_t*) xfer->user_arg) = result;
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}
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xfer->actual_len = _ctrl_xfer.actual_len;
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}
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}
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return true;
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return true;
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@ -952,19 +960,16 @@ bool tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t* xfer, uint32_t tim
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{
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{
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(void) timeout_ms;
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(void) timeout_ms;
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xfer_result_t result = XFER_RESULT_INVALID;
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// clear callback for sync
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tuh_control_xfer_t xfer_sync = (*xfer);
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xfer->complete_cb = NULL;
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xfer_sync.complete_cb = NULL;
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xfer_sync.user_arg = (uintptr_t) &result;
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// TODO use timeout to wait
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// TODO use timeout to wait
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TU_VERIFY(tuh_control_xfer(daddr, &xfer_sync), XFER_RESULT_TIMEOUT);
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TU_VERIFY(tuh_control_xfer(daddr, xfer));
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return result;
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return true;
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}
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}
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TU_ATTR_ALWAYS_INLINE static inline void set_control_xfer_stage(uint8_t stage)
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TU_ATTR_ALWAYS_INLINE static inline void _set_control_xfer_stage(uint8_t stage)
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{
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{
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usbh_lock();
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usbh_lock();
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_ctrl_xfer.stage = stage;
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_ctrl_xfer.stage = stage;
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@ -982,7 +987,7 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
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.ep_addr = 0,
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.ep_addr = 0,
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.result = result,
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.result = result,
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.setup = &request,
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.setup = &request,
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.actual_len = 0,
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.actual_len = (uint32_t) _ctrl_xfer.actual_len,
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.buffer = _ctrl_xfer.buffer,
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.buffer = _ctrl_xfer.buffer,
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.complete_cb = _ctrl_xfer.complete_cb,
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.complete_cb = _ctrl_xfer.complete_cb,
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.user_arg = _ctrl_xfer.user_arg
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.user_arg = _ctrl_xfer.user_arg
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@ -1001,7 +1006,6 @@ static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
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static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
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static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
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{
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{
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(void) ep_addr;
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(void) ep_addr;
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(void) xferred_bytes;
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const uint8_t rhport = usbh_get_rhport(dev_addr);
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const uint8_t rhport = usbh_get_rhport(dev_addr);
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tusb_control_request_t const * request = &_ctrl_xfer.request;
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tusb_control_request_t const * request = &_ctrl_xfer.request;
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@ -1020,20 +1024,22 @@ static bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result
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if (request->wLength)
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if (request->wLength)
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{
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{
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// DATA stage: initial data toggle is always 1
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// DATA stage: initial data toggle is always 1
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set_control_xfer_stage(CONTROL_STAGE_DATA);
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_set_control_xfer_stage(CONTROL_STAGE_DATA);
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return hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength);
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return hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength);
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}
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}
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__attribute__((fallthrough));
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__attribute__((fallthrough));
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case CONTROL_STAGE_DATA:
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case CONTROL_STAGE_DATA:
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if (request->wLength)
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if (xferred_bytes)
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{
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{
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TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
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TU_LOG2("[%u:%u] Control data:\r\n", rhport, dev_addr);
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TU_LOG2_MEM(_ctrl_xfer.buffer, request->wLength, 2);
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TU_LOG2_MEM(_ctrl_xfer.buffer, xferred_bytes, 2);
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}
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}
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_ctrl_xfer.actual_len = xferred_bytes;
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// ACK stage: toggle is always 1
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// ACK stage: toggle is always 1
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set_control_xfer_stage(CONTROL_STAGE_ACK);
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_set_control_xfer_stage(CONTROL_STAGE_ACK);
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hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
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hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
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break;
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break;
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@ -1083,7 +1089,7 @@ static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t h
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hcd_device_close(rhport, dev_addr);
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hcd_device_close(rhport, dev_addr);
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clear_device(dev);
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clear_device(dev);
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// abort on-going control xfer if any
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// abort on-going control xfer if any
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if (_ctrl_xfer.daddr == dev_addr) set_control_xfer_stage(CONTROL_STAGE_IDLE);
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if (_ctrl_xfer.daddr == dev_addr) _set_control_xfer_stage(CONTROL_STAGE_IDLE);
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}
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}
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}
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}
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}
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}
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@ -50,7 +50,7 @@ struct tuh_control_xfer_s
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xfer_result_t result;
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xfer_result_t result;
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tusb_control_request_t const* setup;
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tusb_control_request_t const* setup;
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uint32_t actual_len;
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uint32_t actual_len; // excluding setup packet
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uint8_t* buffer;
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uint8_t* buffer;
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tuh_control_xfer_cb_t complete_cb;
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tuh_control_xfer_cb_t complete_cb;
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@ -115,7 +115,8 @@ static inline bool tuh_ready(uint8_t daddr)
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// Carry out a control transfer
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// Carry out a control transfer
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// true on success, false if there is on-going control transfer or incorrect parameters
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// true on success, false if there is on-going control transfer or incorrect parameters
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// Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
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// Note: blocking if complete callback is NULL. In this case 'xfer->result' will be updated
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// and if 'user_arg' point to a xfer_result_t variable, it will be updated as well.
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bool tuh_control_xfer(uint8_t daddr, tuh_control_xfer_t* xfer);
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bool tuh_control_xfer(uint8_t daddr, tuh_control_xfer_t* xfer);
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//bool tuh_edpt_xfer(uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
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//bool tuh_edpt_xfer(uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
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@ -123,7 +124,6 @@ bool tuh_control_xfer(uint8_t daddr, tuh_control_xfer_t* xfer);
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// Set Configuration (control transfer)
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// Set Configuration (control transfer)
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// config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
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// config_num = 0 will un-configure device. Note: config_num = config_descriptor_index + 1
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// true on success, false if there is on-going control transfer or incorrect parameters
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// true on success, false if there is on-going control transfer or incorrect parameters
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// Blocking if complete callback is NULL, in this case 'user_arg' must contain xfer_result_t variable
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bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
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bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
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tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
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tuh_control_xfer_cb_t complete_cb, uintptr_t user_arg);
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@ -132,7 +132,7 @@ bool tuh_configuration_set(uint8_t daddr, uint8_t config_num,
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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// Sync (blocking) version of tuh_control_xfer()
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// Sync (blocking) version of tuh_control_xfer()
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// return transfer result
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// xfer contents will be updated to reflect the transfer
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bool tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t * xfer, uint32_t timeout_ms);
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bool tuh_control_xfer_sync(uint8_t daddr, tuh_control_xfer_t * xfer, uint32_t timeout_ms);
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//--------------------------------------------------------------------+
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//--------------------------------------------------------------------+
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