mirror of
https://github.com/hathach/tinyusb.git
synced 2025-03-14 04:18:56 +00:00
fix incorrect merge of hcd link
This commit is contained in:
hathach
parent
2cf092464b
commit
0f8e530de1
@ -1,4 +1,4 @@
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/*
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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2021 Koji Kitayama
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@ -27,86 +27,37 @@
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#include "tusb_option.h"
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#if CFG_TUH_ENABLED && ( CFG_TUSB_MCU == OPT_MCU_RX63X || \
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CFG_TUSB_MCU == OPT_MCU_RX65X || \
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CFG_TUSB_MCU == OPT_MCU_RX72N )
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#if CFG_TUH_ENABLED && (CFG_TUSB_MCU == OPT_MCU_RX63X || \
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CFG_TUSB_MCU == OPT_MCU_RX65X || \
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CFG_TUSB_MCU == OPT_MCU_RX72N || \
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CFG_TUSB_MCU == OPT_MCU_RAXXX)
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#include "host/hcd.h"
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#include "iodefine.h"
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#include "link_type.h"
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#if TU_CHECK_MCU(OPT_MCU_RX63X, OPT_MCU_RX65X, OPT_MCU_RX72N)
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#include "link_rx.h"
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#elif TU_CHECK_MCU(OPT_MCU_RAXXX)
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#include "link_ra.h"
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#else
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#error "Unsupported MCU"
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#endif
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//--------------------------------------------------------------------+
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// MACRO TYPEDEF CONSTANT ENUM DECLARATION
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//--------------------------------------------------------------------+
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#define SYSTEM_PRCR_PRC1 (1<<1)
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#define SYSTEM_PRCR_PRKEY (0xA5u<<8)
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#define USB_DVSTCTR0_LOW (1u)
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#define USB_DVSTCTR0_FULL (2u)
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/* LINK core registers */
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#if defined(__CCRX__)
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#define LINK_REG ((LINK_REG_t __evenaccess*)LINK_REG_BASE)
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#else
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#define LINK_REG ((LINK_REG_t*)LINK_REG_BASE)
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#endif
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#define USB_FIFOSEL_TX ((uint16_t)(1u<<5))
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#define USB_FIFOSEL_BIGEND ((uint16_t)(1u<<8))
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#define USB_FIFOSEL_MBW_8 ((uint16_t)(0u<<10))
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#define USB_FIFOSEL_MBW_16 ((uint16_t)(1u<<10))
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#define USB_IS0_CTSQ ((uint16_t)(7u))
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#define USB_IS0_DVSQ ((uint16_t)(7u<<4))
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#define USB_IS0_VALID ((uint16_t)(1u<<3))
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#define USB_IS0_BRDY ((uint16_t)(1u<<8))
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#define USB_IS0_NRDY ((uint16_t)(1u<<9))
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#define USB_IS0_BEMP ((uint16_t)(1u<<10))
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#define USB_IS0_CTRT ((uint16_t)(1u<<11))
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#define USB_IS0_DVST ((uint16_t)(1u<<12))
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#define USB_IS0_SOFR ((uint16_t)(1u<<13))
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#define USB_IS0_RESM ((uint16_t)(1u<<14))
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#define USB_IS0_VBINT ((uint16_t)(1u<<15))
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#define USB_IS1_SACK ((uint16_t)(1u<<4))
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#define USB_IS1_SIGN ((uint16_t)(1u<<5))
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#define USB_IS1_EOFERR ((uint16_t)(1u<<6))
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#define USB_IS1_ATTCH ((uint16_t)(1u<<11))
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#define USB_IS1_DTCH ((uint16_t)(1u<<12))
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#define USB_IS1_BCHG ((uint16_t)(1u<<14))
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#define USB_IS1_OVRCR ((uint16_t)(1u<<15))
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#define USB_IS0_CTSQ_MSK (7u)
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#define USB_IS0_CTSQ_SETUP (1u)
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#define USB_IS0_DVSQ_DEF (1u<<4)
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#define USB_IS0_DVSQ_ADDR (2u<<4)
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#define USB_IS0_DVSQ_SUSP0 (4u<<4)
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#define USB_IS0_DVSQ_SUSP1 (5u<<4)
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#define USB_IS0_DVSQ_SUSP2 (6u<<4)
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#define USB_IS0_DVSQ_SUSP3 (7u<<4)
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#define USB_PIPECTR_PID_MSK (3u)
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#define USB_PIPECTR_PID_NAK (0u)
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#define USB_PIPECTR_PID_BUF (1u)
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#define USB_PIPECTR_PID_STALL (2u)
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#define USB_PIPECTR_CCPL (1u<<2)
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#define USB_PIPECTR_SQMON (1u<<6)
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#define USB_PIPECTR_SQCLR (1u<<8)
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#define USB_PIPECTR_ACLRM (1u<<9)
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#define USB_PIPECTR_INBUFM (1u<<14)
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#define USB_PIPECTR_BSTS (1u<<15)
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#define USB_FIFOCTR_DTLN (0x1FF)
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#define USB_FIFOCTR_FRDY (1u<<13)
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#define USB_FIFOCTR_BCLR (1u<<14)
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#define USB_FIFOCTR_BVAL (1u<<15)
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#define USB_PIPECFG_SHTNAK (1u<<7)
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#define USB_PIPECFG_DBLB (1u<<9)
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#define USB_PIPECFG_BULK (1u<<14)
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#define USB_PIPECFG_ISO (3u<<14)
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#define USB_PIPECFG_INT (2u<<14)
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#define USB_DEVADD_LOW (1u<<6)
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#define USB_DEVADD_FULL (2u<<6)
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#define FIFO_REQ_CLR (1u)
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#define FIFO_COMPLETE (1u<<1)
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// Start of definition of packed structs (used by the CCRX toolchain)
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TU_ATTR_PACKED_BEGIN
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TU_ATTR_BIT_FIELD_ORDER_BEGIN
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typedef struct {
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typedef struct TU_ATTR_PACKED {
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union {
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struct {
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uint16_t : 8;
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@ -119,7 +70,7 @@ typedef struct {
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uint16_t TRN;
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} reg_pipetre_t;
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typedef union {
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typedef union TU_ATTR_PACKED {
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struct {
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volatile uint16_t u8: 8;
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volatile uint16_t : 0;
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@ -127,8 +78,7 @@ typedef union {
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volatile uint16_t u16;
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} hw_fifo_t;
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typedef struct TU_ATTR_PACKED
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{
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typedef struct TU_ATTR_PACKED {
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void *buf; /* the start address of a transfer data buffer */
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uint16_t length; /* the number of bytes in the buffer */
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uint16_t remaining; /* the number of bytes remaining in the buffer */
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@ -156,28 +106,6 @@ typedef struct
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//--------------------------------------------------------------------+
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static hcd_data_t _hcd;
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static uint32_t disable_interrupt(void)
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{
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uint32_t pswi;
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#if defined(__CCRX__)
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pswi = get_psw() & 0x010000;
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clrpsw_i();
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#else
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pswi = __builtin_rx_mvfc(0) & 0x010000;
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__builtin_rx_clrpsw('I');
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#endif
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return pswi;
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}
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static void enable_interrupt(uint32_t pswi)
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{
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#if defined(__CCRX__)
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set_psw(get_psw() | pswi);
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#else
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__builtin_rx_mvtc(0, __builtin_rx_mvfc(0) | pswi);
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#endif
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}
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static unsigned find_pipe(unsigned xfer)
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{
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switch (xfer) {
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@ -208,58 +136,49 @@ static unsigned find_pipe(unsigned xfer)
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static volatile uint16_t* get_pipectr(unsigned num)
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{
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volatile uint16_t *ctr = NULL;
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if (num) {
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ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
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ctr += num - 1;
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return (volatile uint16_t*)&(LINK_REG->PIPE_CTR[num - 1]);
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} else {
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ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
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return (volatile uint16_t*)&(LINK_REG->DCPCTR);
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}
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return ctr;
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}
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static volatile reg_pipetre_t* get_pipetre(unsigned num)
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{
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volatile reg_pipetre_t* tre = NULL;
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if ((1 <= num) && (num <= 5)) {
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tre = (volatile reg_pipetre_t*)&USB0.PIPE1TRE.WORD;
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tre += num - 1;
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tre = (volatile reg_pipetre_t*)&(LINK_REG->PIPE_TR[num - 1].E);
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}
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return tre;
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}
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static volatile uint16_t* addr_to_pipectr(uint8_t dev_addr, unsigned ep_addr)
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{
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volatile uint16_t *ctr = NULL;
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const unsigned epn = tu_edpt_number(ep_addr);
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const unsigned epn = tu_edpt_number(ep_addr);
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if (epn) {
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const unsigned dir_in = tu_edpt_dir(ep_addr);
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const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1];
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if (num) {
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ctr = (volatile uint16_t*)&USB0.PIPE1CTR.WORD;
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ctr += num - 1;
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}
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const unsigned num = _hcd.ep[dev_addr][dir_in][epn - 1];
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return get_pipectr(num);
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} else {
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ctr = (volatile uint16_t*)&USB0.DCPCTR.WORD;
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return get_pipectr(0);
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}
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return ctr;
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}
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static unsigned edpt0_max_packet_size(void)
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{
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return USB0.DCPMAXP.BIT.MXPS;
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return LINK_REG->DCPMAXP_b.MXPS;
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}
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static unsigned edpt_max_packet_size(unsigned num)
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{
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USB0.PIPESEL.WORD = num;
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return USB0.PIPEMAXP.BIT.MXPS;
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LINK_REG->PIPESEL = num;
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return LINK_REG->PIPEMAXP_b.MXPS;
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}
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static inline void pipe_wait_for_ready(unsigned num)
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{
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while (USB0.D0FIFOSEL.BIT.CURPIPE != num) ;
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while (!USB0.D0FIFOCTR.BIT.FRDY) ;
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while (LINK_REG->D0FIFOSEL_b.CURPIPE != num) ;
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while (!LINK_REG->D0FIFOCTR_b.FRDY) ;
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}
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static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len)
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@ -290,21 +209,22 @@ static bool pipe0_xfer_in(void)
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const unsigned rem = pipe->remaining;
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const unsigned mps = edpt0_max_packet_size();
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const unsigned vld = USB0.CFIFOCTR.BIT.DTLN;
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const unsigned vld = LINK_REG->CFIFOCTR_b.DTLN;
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const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
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void *buf = pipe->buf;
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if (len) {
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USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
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pipe_read_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
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LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
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pipe_read_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
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pipe->buf = (uint8_t*)buf + len;
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}
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if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BCLR;
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if (len < mps)
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LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
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pipe->remaining = rem - len;
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if ((len < mps) || (rem == len)) {
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pipe->buf = NULL;
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return true;
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}
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USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
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LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
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return false;
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}
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@ -320,10 +240,11 @@ static bool pipe0_xfer_out(void)
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const unsigned len = TU_MIN(mps, rem);
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void *buf = pipe->buf;
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if (len) {
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pipe_write_packet(buf, (volatile void*)&USB0.CFIFO.WORD, len);
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pipe_write_packet(buf, (volatile void*)&LINK_REG->CFIFO, len);
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pipe->buf = (uint8_t*)buf + len;
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}
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if (len < mps) USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
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if (len < mps)
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LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
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pipe->remaining = rem - len;
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return false;
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}
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@ -333,20 +254,21 @@ static bool pipe_xfer_in(unsigned num)
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pipe_state_t *pipe = &_hcd.pipe[num];
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const unsigned rem = pipe->remaining;
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USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_8;
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LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_8BIT;
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const unsigned mps = edpt_max_packet_size(num);
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pipe_wait_for_ready(num);
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const unsigned vld = USB0.D0FIFOCTR.BIT.DTLN;
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const unsigned vld = LINK_REG->D0FIFOCTR_b.DTLN;
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const unsigned len = TU_MIN(TU_MIN(rem, mps), vld);
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void *buf = pipe->buf;
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if (len) {
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pipe_read_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
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pipe_read_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
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pipe->buf = (uint8_t*)buf + len;
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}
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if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BCLR;
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USB0.D0FIFOSEL.WORD = 0;
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while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
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pipe->remaining = rem - len;
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if (len < mps)
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LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BCLR_Msk;
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LINK_REG->D0FIFOSEL = 0;
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while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
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pipe->remaining = rem - len;
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if ((len < mps) || (rem == len)) {
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pipe->buf = NULL;
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return NULL != buf;
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@ -364,18 +286,19 @@ static bool pipe_xfer_out(unsigned num)
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return true;
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}
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USB0.D0FIFOSEL.WORD = num | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
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LINK_REG->D0FIFOSEL = num | LINK_REG_FIFOSEL_MBW_16BIT | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
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const unsigned mps = edpt_max_packet_size(num);
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pipe_wait_for_ready(num);
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const unsigned len = TU_MIN(rem, mps);
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void *buf = pipe->buf;
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if (len) {
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pipe_write_packet(buf, (volatile void*)&USB0.D0FIFO.WORD, len);
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pipe_write_packet(buf, (volatile void*)&LINK_REG->D0FIFO, len);
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pipe->buf = (uint8_t*)buf + len;
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}
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if (len < mps) USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
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USB0.D0FIFOSEL.WORD = 0;
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while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
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if (len < mps)
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LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
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LINK_REG->D0FIFOSEL = 0;
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while (LINK_REG->D0FIFOSEL_b.CURPIPE) ; /* if CURPIPE bits changes, check written value */
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pipe->remaining = rem - len;
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return false;
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}
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@ -387,11 +310,12 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
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/* configure fifo direction and access unit settings */
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if (dir_in) { /* IN, a byte */
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USB0.CFIFOSEL.WORD = USB_FIFOSEL_MBW_8;
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while (USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX) ;
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} else { /* OUT, 2 bytes */
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USB0.CFIFOSEL.WORD = USB_FIFOSEL_TX | USB_FIFOSEL_MBW_16 | (TU_BYTE_ORDER == TU_BIG_ENDIAN ? USB_FIFOSEL_BIGEND : 0);
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while (!(USB0.CFIFOSEL.WORD & USB_FIFOSEL_TX)) ;
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LINK_REG->CFIFOSEL = LINK_REG_FIFOSEL_MBW_8BIT;
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while (LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE) ;
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} else { /* OUT, 2 bytes */
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LINK_REG->CFIFOSEL = LINK_REG_CFIFOSEL_ISEL_WRITE | LINK_REG_FIFOSEL_MBW_16BIT |
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(TU_BYTE_ORDER == TU_BIG_ENDIAN ? LINK_REG_FIFOSEL_BIGEND : 0);
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while (!(LINK_REG->CFIFOSEL & LINK_REG_CFIFOSEL_ISEL_WRITE)) ;
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}
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pipe_state_t *pipe = &_hcd.pipe[0];
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@ -401,25 +325,25 @@ static bool process_pipe0_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer,
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if (buflen) {
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pipe->buf = buffer;
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if (!dir_in) { /* OUT */
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TU_ASSERT(USB0.DCPCTR.BIT.BSTS && (USB0.USBREQ.WORD & 0x80));
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TU_ASSERT(LINK_REG->DCPCTR_b.BSTS && (LINK_REG->USBREQ & 0x80));
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pipe0_xfer_out();
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}
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} else { /* ZLP */
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pipe->buf = NULL;
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if (!dir_in) { /* OUT */
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USB0.CFIFOCTR.WORD = USB_FIFOCTR_BVAL;
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LINK_REG->CFIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
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}
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if (dir_in == USB0.DCPCFG.BIT.DIR) {
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TU_ASSERT(USB_PIPECTR_PID_NAK == USB0.DCPCTR.BIT.PID);
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USB0.DCPCTR.BIT.SQSET = 1;
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USB0.DCPCFG.BIT.DIR = dir_in ^ 1;
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if (dir_in == LINK_REG->DCPCFG_b.DIR) {
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TU_ASSERT(LINK_REG_PIPE_CTR_PID_NAK == LINK_REG->DCPCTR_b.PID);
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LINK_REG->DCPCTR_b.SQSET = 1;
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LINK_REG->DCPCFG_b.DIR = dir_in ^ 1;
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}
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}
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USB0.DCPCTR.WORD = USB_PIPECTR_PID_BUF;
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LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_BUF;
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return true;
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}
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|
||||
static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, uint16_t buflen)
|
||||
static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void *buffer, uint16_t buflen)
|
||||
{
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned dir_in = tu_edpt_dir(ep_addr);
|
||||
@ -435,23 +359,23 @@ static bool process_pipe_xfer(uint8_t dev_addr, uint8_t ep_addr, void* buffer, u
|
||||
if (buflen) {
|
||||
pipe_xfer_out(num);
|
||||
} else { /* ZLP */
|
||||
USB0.D0FIFOSEL.WORD = num;
|
||||
LINK_REG->D0FIFOSEL = num;
|
||||
pipe_wait_for_ready(num);
|
||||
USB0.D0FIFOCTR.WORD = USB_FIFOCTR_BVAL;
|
||||
USB0.D0FIFOSEL.WORD = 0;
|
||||
while (USB0.D0FIFOSEL.BIT.CURPIPE) ; /* if CURPIPE bits changes, check written value */
|
||||
LINK_REG->D0FIFOCTR = LINK_REG_CFIFOCTR_BVAL_Msk;
|
||||
LINK_REG->D0FIFOSEL = 0;
|
||||
while (LINK_REG->D0FIFOSEL_b.CURPIPE) continue; /* if CURPIPE bits changes, check written value */
|
||||
}
|
||||
} else {
|
||||
volatile uint16_t *ctr = get_pipectr(num);
|
||||
volatile reg_pipetre_t *pt = get_pipetre(num);
|
||||
if (pt) {
|
||||
const unsigned mps = edpt_max_packet_size(num);
|
||||
if (*ctr & 0x3) *ctr = USB_PIPECTR_PID_NAK;
|
||||
if (*ctr & 0x3) *ctr = LINK_REG_PIPE_CTR_PID_NAK;
|
||||
pt->TRE = TU_BIT(8);
|
||||
pt->TRN = (buflen + mps - 1) / mps;
|
||||
pt->TRENB = 1;
|
||||
}
|
||||
*ctr = USB_PIPECTR_PID_BUF;
|
||||
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
@ -485,10 +409,10 @@ static void process_pipe_nrdy(uint8_t rhport, unsigned num)
|
||||
unsigned result;
|
||||
uint16_t volatile *ctr = get_pipectr(num);
|
||||
// TU_LOG1("NRDY %d %x\n", num, *ctr);
|
||||
switch (*ctr & USB_PIPECTR_PID_MSK) {
|
||||
switch (*ctr & LINK_REG_PIPE_CTR_PID_Msk) {
|
||||
default: return;
|
||||
case USB_PIPECTR_PID_STALL: result = XFER_RESULT_STALLED; break;
|
||||
case USB_PIPECTR_PID_NAK: result = XFER_RESULT_FAILED; break;
|
||||
case LINK_REG_PIPE_CTR_PID_STALL: result = XFER_RESULT_STALLED; break;
|
||||
case LINK_REG_PIPE_CTR_PID_NAK: result = XFER_RESULT_FAILED; break;
|
||||
}
|
||||
pipe_state_t *pipe = &_hcd.pipe[num];
|
||||
hcd_event_xfer_complete(pipe->dev, pipe->ep,
|
||||
@ -520,78 +444,60 @@ static void process_pipe_brdy(uint8_t rhport, unsigned num)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------*/
|
||||
/* Host API
|
||||
*------------------------------------------------------------------*/
|
||||
bool hcd_init(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
/* Enable USB0 */
|
||||
uint32_t pswi = disable_interrupt();
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY | SYSTEM_PRCR_PRC1;
|
||||
MSTP(USB0) = 0;
|
||||
SYSTEM.PRCR.WORD = SYSTEM_PRCR_PRKEY;
|
||||
enable_interrupt(pswi);
|
||||
USB0.SYSCFG.BIT.SCKE = 1;
|
||||
while (!USB0.SYSCFG.BIT.SCKE) ;
|
||||
USB0.SYSCFG.BIT.DPRPU = 0;
|
||||
USB0.SYSCFG.BIT.DRPD = 0;
|
||||
USB0.SYSCFG.BIT.DCFM = 1;
|
||||
|
||||
USB0.DVSTCTR0.BIT.VBUSEN = 1;
|
||||
LINK_REG->SYSCFG_b.SCKE = 1;
|
||||
while (!LINK_REG->SYSCFG_b.SCKE) ;
|
||||
LINK_REG->SYSCFG_b.DPRPU = 0;
|
||||
LINK_REG->SYSCFG_b.DRPD = 0;
|
||||
LINK_REG->SYSCFG_b.DCFM = 1;
|
||||
|
||||
USB0.SYSCFG.BIT.DRPD = 1;
|
||||
LINK_REG->DVSTCTR0_b.VBUSEN = 1;
|
||||
|
||||
LINK_REG->SYSCFG_b.DRPD = 1;
|
||||
for (volatile int i = 0; i < 30000; ++i) ;
|
||||
USB0.SYSCFG.BIT.USBE = 1;
|
||||
LINK_REG->SYSCFG_b.USBE = 1;
|
||||
|
||||
USB.DPUSR0R.BIT.FIXPHY0 = 0u; /* USB0 Transceiver Output fixed */
|
||||
#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
|
||||
USB0.PHYSLEW.LONG = 0x5;
|
||||
IR(PERIB, INTB185) = 0;
|
||||
#else
|
||||
IR(USB0, USBI0) = 0;
|
||||
#endif
|
||||
// MCU specific PHY init
|
||||
link_phy_init();
|
||||
|
||||
LINK_REG->PHYSLEW = 0x5;
|
||||
LINK_REG->DPUSR0R_FS_b.FIXPHY0 = 0u; /* Transceiver Output fixed */
|
||||
|
||||
/* Setup default control pipe */
|
||||
USB0.DCPCFG.WORD = USB_PIPECFG_SHTNAK;
|
||||
USB0.DCPMAXP.WORD = 64;
|
||||
USB0.INTENB0.WORD = USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP;
|
||||
USB0.INTENB1.WORD = USB_IS1_SACK | USB_IS1_SIGN |
|
||||
USB_IS1_ATTCH | USB_IS1_DTCH;
|
||||
USB0.BEMPENB.WORD = 1;
|
||||
USB0.NRDYENB.WORD = 1;
|
||||
USB0.BRDYENB.WORD = 1;
|
||||
LINK_REG->DCPCFG = LINK_REG_PIPECFG_SHTNAK_Msk;
|
||||
LINK_REG->DCPMAXP = 64;
|
||||
LINK_REG->INTENB0 = LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk;
|
||||
LINK_REG->INTENB1 = LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk;
|
||||
LINK_REG->BEMPENB = 1;
|
||||
LINK_REG->NRDYENB = 1;
|
||||
LINK_REG->BRDYENB = 1;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void hcd_int_enable(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
|
||||
IEN(PERIB, INTB185) = 1;
|
||||
#else
|
||||
IEN(USB0, USBI0) = 1;
|
||||
#endif
|
||||
link_int_enable(rhport);
|
||||
}
|
||||
|
||||
void hcd_int_disable(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
#if ( CFG_TUSB_MCU == OPT_MCU_RX72N )
|
||||
IEN(PERIB, INTB185) = 0;
|
||||
#else
|
||||
IEN(USB0, USBI0) = 0;
|
||||
#endif
|
||||
link_int_disable(rhport);
|
||||
}
|
||||
|
||||
uint32_t hcd_frame_number(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
/* The device must be reset at least once after connection
|
||||
/* The device must be reset at least once after connection
|
||||
* in order to start the frame counter. */
|
||||
if (_hcd.need_reset) hcd_port_reset(rhport);
|
||||
return USB0.FRMNUM.BIT.FRNM;
|
||||
return LINK_REG->FRMNUM_b.FRNM;
|
||||
}
|
||||
|
||||
/*--------------------------------------------------------------------+
|
||||
@ -605,18 +511,18 @@ bool hcd_port_connect_status(uint8_t rhport)
|
||||
|
||||
void hcd_port_reset(uint8_t rhport)
|
||||
{
|
||||
USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
|
||||
while (USB0.DCPCTR.BIT.PBUSY) ;
|
||||
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
|
||||
while (LINK_REG->DCPCTR_b.PBUSY) ;
|
||||
hcd_int_disable(rhport);
|
||||
USB0.DVSTCTR0.BIT.UACT = 0;
|
||||
if (USB0.DCPCTR.BIT.SUREQ)
|
||||
USB0.DCPCTR.BIT.SUREQCLR = 1;
|
||||
LINK_REG->DVSTCTR0_b.UACT = 0;
|
||||
if (LINK_REG->DCPCTR_b.SUREQ)
|
||||
LINK_REG->DCPCTR_b.SUREQCLR = 1;
|
||||
hcd_int_enable(rhport);
|
||||
/* Reset should be asserted 10-20ms. */
|
||||
USB0.DVSTCTR0.BIT.USBRST = 1;
|
||||
LINK_REG->DVSTCTR0_b.USBRST = 1;
|
||||
for (volatile int i = 0; i < 2400000; ++i) ;
|
||||
USB0.DVSTCTR0.BIT.USBRST = 0;
|
||||
USB0.DVSTCTR0.BIT.UACT = 1;
|
||||
LINK_REG->DVSTCTR0_b.USBRST = 0;
|
||||
LINK_REG->DVSTCTR0_b.UACT = 1;
|
||||
_hcd.need_reset = false;
|
||||
}
|
||||
|
||||
@ -628,10 +534,10 @@ void hcd_port_reset_end(uint8_t rhport)
|
||||
tusb_speed_t hcd_port_speed_get(uint8_t rhport)
|
||||
{
|
||||
(void)rhport;
|
||||
switch (USB0.DVSTCTR0.BIT.RHST) {
|
||||
switch (LINK_REG->DVSTCTR0_b.RHST) {
|
||||
default: return TUSB_SPEED_INVALID;
|
||||
case USB_DVSTCTR0_FULL: return TUSB_SPEED_FULL;
|
||||
case USB_DVSTCTR0_LOW: return TUSB_SPEED_LOW;
|
||||
case LINK_REG_DVSTCTR0_RHST_FS: return TUSB_SPEED_FULL;
|
||||
case LINK_REG_DVSTCTR0_RHST_LS: return TUSB_SPEED_LOW;
|
||||
}
|
||||
}
|
||||
|
||||
@ -647,13 +553,13 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
|
||||
unsigned num = *ep;
|
||||
if (!num || dev_addr != _hcd.pipe[num].dev) continue;
|
||||
|
||||
ctr = (uint16_t volatile*)&USB0.PIPE1CTR.WORD + num - 1;
|
||||
ctr = (uint16_t volatile*)&LINK_REG->PIPE_CTR[num - 1];
|
||||
*ctr = 0;
|
||||
USB0.NRDYENB.WORD &= ~TU_BIT(num);
|
||||
USB0.BRDYENB.WORD &= ~TU_BIT(num);
|
||||
USB0.PIPESEL.WORD = num;
|
||||
USB0.PIPECFG.WORD = 0;
|
||||
USB0.PIPEMAXP.WORD = 0;
|
||||
LINK_REG->NRDYENB &= ~TU_BIT(num);
|
||||
LINK_REG->BRDYENB &= ~TU_BIT(num);
|
||||
LINK_REG->PIPESEL = num;
|
||||
LINK_REG->PIPECFG = 0;
|
||||
LINK_REG->PIPEMAXP = 0;
|
||||
|
||||
_hcd.pipe[num].ep = 0;
|
||||
_hcd.pipe[num].dev = 0;
|
||||
@ -667,36 +573,36 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
|
||||
bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
|
||||
{
|
||||
(void)rhport;
|
||||
// TU_LOG1("S %d %x\n", dev_addr, USB0.DCPCTR.WORD);
|
||||
// TU_LOG1("S %d %x\n", dev_addr, LINK_REG->DCPCTR);
|
||||
|
||||
TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
|
||||
TU_ASSERT(0 == USB0.DCPCTR.BIT.SUREQ);
|
||||
TU_ASSERT(0 == LINK_REG->DCPCTR_b.SUREQ);
|
||||
|
||||
USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
|
||||
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
|
||||
|
||||
_hcd.pipe[0].buf = NULL;
|
||||
_hcd.pipe[0].length = 8;
|
||||
_hcd.pipe[0].buf = NULL;
|
||||
_hcd.pipe[0].length = 8;
|
||||
_hcd.pipe[0].remaining = 0;
|
||||
_hcd.pipe[0].dev = dev_addr;
|
||||
_hcd.pipe[0].dev = dev_addr;
|
||||
|
||||
while (USB0.DCPCTR.BIT.PBUSY) ;
|
||||
USB0.DCPMAXP.WORD = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
|
||||
while (LINK_REG->DCPCTR_b.PBUSY) ;
|
||||
LINK_REG->DCPMAXP = (dev_addr << 12) | _hcd.ctl_mps[dev_addr];
|
||||
|
||||
/* Set direction in advance for DATA stage */
|
||||
uint8_t const bmRequesttype = setup_packet[0];
|
||||
USB0.DCPCFG.BIT.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
|
||||
LINK_REG->DCPCFG_b.DIR = tu_edpt_dir(bmRequesttype) ? 0: 1;
|
||||
|
||||
uint16_t const* p = (uint16_t const*)(uintptr_t)&setup_packet[0];
|
||||
USB0.USBREQ.WORD = tu_htole16(p[0]);
|
||||
USB0.USBVAL = p[1];
|
||||
USB0.USBINDX = p[2];
|
||||
USB0.USBLENG = p[3];
|
||||
LINK_REG->USBREQ = tu_htole16(p[0]);
|
||||
LINK_REG->USBVAL = p[1];
|
||||
LINK_REG->USBINDX = p[2];
|
||||
LINK_REG->USBLENG = p[3];
|
||||
|
||||
USB0.DCPCTR.BIT.SUREQ = 1;
|
||||
LINK_REG->DCPCTR_b.SUREQ = 1;
|
||||
return true;
|
||||
}
|
||||
|
||||
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
|
||||
bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const *ep_desc)
|
||||
{
|
||||
(void)rhport;
|
||||
TU_ASSERT(dev_addr < 6); /* USBa can only handle addresses from 0 to 5. */
|
||||
@ -705,14 +611,14 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
|
||||
const unsigned epn = tu_edpt_number(ep_addr);
|
||||
const unsigned mps = tu_edpt_packet_size(ep_desc);
|
||||
if (0 == epn) {
|
||||
USB0.DCPCTR.WORD = USB_PIPECTR_PID_NAK;
|
||||
LINK_REG->DCPCTR = LINK_REG_PIPE_CTR_PID_NAK;
|
||||
hcd_devtree_info_t devtree;
|
||||
hcd_devtree_get_info(dev_addr, &devtree);
|
||||
uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t)&USB0.DEVADD0.WORD;
|
||||
uint16_t volatile *devadd = (uint16_t volatile *)(uintptr_t) &LINK_REG->DEVADD[0];
|
||||
devadd += dev_addr;
|
||||
while (USB0.DCPCTR.BIT.PBUSY) ;
|
||||
USB0.DCPMAXP.WORD = (dev_addr << 12) | mps;
|
||||
*devadd = (TUSB_SPEED_FULL == devtree.speed) ? USB_DEVADD_FULL : USB_DEVADD_LOW;
|
||||
while (LINK_REG->DCPCTR_b.PBUSY) ;
|
||||
LINK_REG->DCPMAXP = (dev_addr << 12) | mps;
|
||||
*devadd = (TUSB_SPEED_FULL == devtree.speed) ? LINK_REG_DEVADD_USBSPD_FS : LINK_REG_DEVADD_USBSPD_LS;
|
||||
_hcd.ctl_mps[dev_addr] = mps;
|
||||
return true;
|
||||
}
|
||||
@ -731,25 +637,25 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const
|
||||
|
||||
/* setup pipe */
|
||||
hcd_int_disable(rhport);
|
||||
USB0.PIPESEL.WORD = num;
|
||||
USB0.PIPEMAXP.WORD = (dev_addr << 12) | mps;
|
||||
LINK_REG->PIPESEL = num;
|
||||
LINK_REG->PIPEMAXP = (dev_addr << 12) | mps;
|
||||
volatile uint16_t *ctr = get_pipectr(num);
|
||||
*ctr = USB_PIPECTR_ACLRM | USB_PIPECTR_SQCLR;
|
||||
*ctr = LINK_REG_PIPE_CTR_ACLRM_Msk | LINK_REG_PIPE_CTR_SQCLR_Msk;
|
||||
*ctr = 0;
|
||||
unsigned cfg = ((1 ^ dir_in) << 4) | epn;
|
||||
if (xfer == TUSB_XFER_BULK) {
|
||||
cfg |= USB_PIPECFG_BULK | USB_PIPECFG_SHTNAK | USB_PIPECFG_DBLB;
|
||||
cfg |= LINK_REG_PIPECFG_TYPE_BULK | LINK_REG_PIPECFG_SHTNAK_Msk | LINK_REG_PIPECFG_DBLB_Msk;
|
||||
} else if (xfer == TUSB_XFER_INTERRUPT) {
|
||||
cfg |= USB_PIPECFG_INT;
|
||||
cfg |= LINK_REG_PIPECFG_TYPE_INT;
|
||||
} else {
|
||||
cfg |= USB_PIPECFG_ISO | USB_PIPECFG_DBLB;
|
||||
cfg |= LINK_REG_PIPECFG_TYPE_ISO | LINK_REG_PIPECFG_DBLB_Msk;
|
||||
}
|
||||
USB0.PIPECFG.WORD = cfg;
|
||||
USB0.BRDYSTS.WORD = 0x1FFu ^ TU_BIT(num);
|
||||
USB0.NRDYENB.WORD |= TU_BIT(num);
|
||||
USB0.BRDYENB.WORD |= TU_BIT(num);
|
||||
LINK_REG->PIPECFG = cfg;
|
||||
LINK_REG->BRDYSTS = 0x1FFu ^ TU_BIT(num);
|
||||
LINK_REG->NRDYENB |= TU_BIT(num);
|
||||
LINK_REG->BRDYENB |= TU_BIT(num);
|
||||
if (!dir_in) {
|
||||
*ctr = USB_PIPECTR_PID_BUF;
|
||||
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
hcd_int_enable(rhport);
|
||||
|
||||
@ -776,12 +682,12 @@ bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
|
||||
*ctr = pid & 2;
|
||||
*ctr = 0;
|
||||
}
|
||||
*ctr = USB_PIPECTR_SQCLR;
|
||||
*ctr = LINK_REG_PIPE_CTR_SQCLR_Msk;
|
||||
unsigned const epn = tu_edpt_number(ep_addr);
|
||||
if (!epn) return true;
|
||||
|
||||
if (!tu_edpt_dir(ep_addr)) { /* OUT */
|
||||
*ctr = USB_PIPECTR_PID_BUF;
|
||||
*ctr = LINK_REG_PIPE_CTR_PID_BUF;
|
||||
}
|
||||
return true;
|
||||
}
|
||||
@ -799,52 +705,50 @@ void hcd_int_handler(uint8_t rhport)
|
||||
20, 8, 19, 18};
|
||||
#endif
|
||||
|
||||
unsigned is1 = USB0.INTSTS1.WORD;
|
||||
unsigned is0 = USB0.INTSTS0.WORD;
|
||||
unsigned is1 = LINK_REG->INTSTS1;
|
||||
unsigned is0 = LINK_REG->INTSTS0;
|
||||
/* clear active bits except VALID (don't write 0 to already cleared bits according to the HW manual) */
|
||||
USB0.INTSTS1.WORD = ~((USB_IS1_SACK | USB_IS1_SIGN | USB_IS1_ATTCH | USB_IS1_DTCH) & is1);
|
||||
USB0.INTSTS0.WORD = ~((USB_IS0_BRDY | USB_IS0_NRDY | USB_IS0_BEMP) & is0);
|
||||
LINK_REG->INTSTS1 = ~((LINK_REG_INTSTS1_SACK_Msk | LINK_REG_INTSTS1_SIGN_Msk | LINK_REG_INTSTS1_ATTCH_Msk | LINK_REG_INTSTS1_DTCH_Msk) & is1);
|
||||
LINK_REG->INTSTS0 = ~((LINK_REG_INTSTS0_BRDY_Msk | LINK_REG_INTSTS0_NRDY_Msk | LINK_REG_INTSTS0_BEMP_Msk) & is0);
|
||||
// TU_LOG1("IS %04x %04x\n", is0, is1);
|
||||
is1 &= USB0.INTENB1.WORD;
|
||||
is0 &= USB0.INTENB0.WORD;
|
||||
is1 &= LINK_REG->INTENB1;
|
||||
is0 &= LINK_REG->INTENB0;
|
||||
|
||||
if (is1 & USB_IS1_SACK) {
|
||||
if (is1 & LINK_REG_INTSTS1_SACK_Msk) {
|
||||
/* Set DATA1 in advance for the next transfer. */
|
||||
USB0.DCPCTR.BIT.SQSET = 1;
|
||||
hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL,
|
||||
tu_edpt_addr(0, TUSB_DIR_OUT),
|
||||
8, XFER_RESULT_SUCCESS, true);
|
||||
LINK_REG->DCPCTR_b.SQSET = 1;
|
||||
hcd_event_xfer_complete(
|
||||
LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_SUCCESS, true);
|
||||
}
|
||||
if (is1 & USB_IS1_SIGN) {
|
||||
hcd_event_xfer_complete(USB0.DCPMAXP.BIT.DEVSEL,
|
||||
tu_edpt_addr(0, TUSB_DIR_OUT),
|
||||
8, XFER_RESULT_FAILED, true);
|
||||
if (is1 & LINK_REG_INTSTS1_SIGN_Msk) {
|
||||
hcd_event_xfer_complete(
|
||||
LINK_REG->DCPMAXP_b.DEVSEL, tu_edpt_addr(0, TUSB_DIR_OUT), 8, XFER_RESULT_FAILED, true);
|
||||
}
|
||||
if (is1 & USB_IS1_ATTCH) {
|
||||
USB0.DVSTCTR0.BIT.UACT = 1;
|
||||
if (is1 & LINK_REG_INTSTS1_ATTCH_Msk) {
|
||||
LINK_REG->DVSTCTR0_b.UACT = 1;
|
||||
_hcd.need_reset = true;
|
||||
USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_ATTCH) | USB_IS1_DTCH;
|
||||
LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_ATTCH_Msk) | LINK_REG_INTSTS1_DTCH_Msk;
|
||||
hcd_event_device_attach(rhport, true);
|
||||
}
|
||||
if (is1 & USB_IS1_DTCH) {
|
||||
USB0.DVSTCTR0.BIT.UACT = 0;
|
||||
if (USB0.DCPCTR.BIT.SUREQ)
|
||||
USB0.DCPCTR.BIT.SUREQCLR = 1;
|
||||
USB0.INTENB1.WORD = (USB0.INTENB1.WORD & ~USB_IS1_DTCH) | USB_IS1_ATTCH;
|
||||
if (is1 & LINK_REG_INTSTS1_DTCH_Msk) {
|
||||
LINK_REG->DVSTCTR0_b.UACT = 0;
|
||||
if (LINK_REG->DCPCTR_b.SUREQ)
|
||||
LINK_REG->DCPCTR_b.SUREQCLR = 1;
|
||||
LINK_REG->INTENB1 = (LINK_REG->INTENB1 & ~LINK_REG_INTSTS1_DTCH_Msk) | LINK_REG_INTSTS1_ATTCH_Msk;
|
||||
hcd_event_device_remove(rhport, true);
|
||||
}
|
||||
|
||||
if (is0 & USB_IS0_BEMP) {
|
||||
const unsigned s = USB0.BEMPSTS.WORD;
|
||||
USB0.BEMPSTS.WORD = 0;
|
||||
if (is0 & LINK_REG_INTSTS0_BEMP_Msk) {
|
||||
const unsigned s = LINK_REG->BEMPSTS;
|
||||
LINK_REG->BEMPSTS = 0;
|
||||
if (s & 1) {
|
||||
process_pipe0_bemp(rhport);
|
||||
}
|
||||
}
|
||||
if (is0 & USB_IS0_NRDY) {
|
||||
const unsigned m = USB0.NRDYENB.WORD;
|
||||
unsigned s = USB0.NRDYSTS.WORD & m;
|
||||
USB0.NRDYSTS.WORD = ~s;
|
||||
if (is0 & LINK_REG_INTSTS0_NRDY_Msk) {
|
||||
const unsigned m = LINK_REG->NRDYENB;
|
||||
unsigned s = LINK_REG->NRDYSTS & m;
|
||||
LINK_REG->NRDYSTS = ~s;
|
||||
while (s) {
|
||||
#if defined(__CCRX__)
|
||||
const unsigned num = Mod37BitPosition[(-s & s) % 37];
|
||||
@ -855,11 +759,11 @@ void hcd_int_handler(uint8_t rhport)
|
||||
s &= ~TU_BIT(num);
|
||||
}
|
||||
}
|
||||
if (is0 & USB_IS0_BRDY) {
|
||||
const unsigned m = USB0.BRDYENB.WORD;
|
||||
unsigned s = USB0.BRDYSTS.WORD & m;
|
||||
if (is0 & LINK_REG_INTSTS0_BRDY_Msk) {
|
||||
const unsigned m = LINK_REG->BRDYENB;
|
||||
unsigned s = LINK_REG->BRDYSTS & m;
|
||||
/* clear active bits (don't write 0 to already cleared bits according to the HW manual) */
|
||||
USB0.BRDYSTS.WORD = ~s;
|
||||
LINK_REG->BRDYSTS = ~s;
|
||||
while (s) {
|
||||
#if defined(__CCRX__)
|
||||
const unsigned num = Mod37BitPosition[(-s & s) % 37];
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user