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abstract all UDP_CSR

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hathach 2020-05-02 18:24:23 +07:00
parent 3ad0cd041b
commit 0e30afa691
1 changed files with 11 additions and 9 deletions
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20
src/portable/microchip/samg/dcd_samg.c
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@ -109,23 +109,25 @@ static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len)
#define CSR_NO_EFFECT_1_ALL (UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 | UDP_CSR_STALLSENT | UDP_CSR_RXSETUP | UDP_CSR_TXCOMP) #define CSR_NO_EFFECT_1_ALL (UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 | UDP_CSR_STALLSENT | UDP_CSR_RXSETUP | UDP_CSR_TXCOMP)
// Per Specs: CSR need synchronization each write // Per Specs: CSR need synchronization each write
static inline void csr_set(uint8_t epnum, uint32_t mask) static inline void csr_write(uint8_t epnum, uint32_t value)
{ {
uint32_t const csr = UDP->UDP_CSR[epnum] | CSR_NO_EFFECT_1_ALL | mask; uint32_t const csr = value;
UDP->UDP_CSR[epnum] = csr; UDP->UDP_CSR[epnum] = csr;
volatile uint32_t nop_count; volatile uint32_t nop_count;
for (nop_count = 0; nop_count < 20; nop_count ++) __NOP(); for (nop_count = 0; nop_count < 20; nop_count ++) __NOP();
} }
// Per Specs: CSR need synchronization each write
static inline void csr_set(uint8_t epnum, uint32_t mask)
{
csr_write(epnum, UDP->UDP_CSR[epnum] | CSR_NO_EFFECT_1_ALL | mask);
}
// Per Specs: CSR need synchronization each write // Per Specs: CSR need synchronization each write
static inline void csr_clear(uint8_t epnum, uint32_t mask) static inline void csr_clear(uint8_t epnum, uint32_t mask)
{ {
uint32_t const csr = (UDP->UDP_CSR[epnum] | CSR_NO_EFFECT_1_ALL) & ~mask; csr_write(epnum, (UDP->UDP_CSR[epnum] | CSR_NO_EFFECT_1_ALL) & ~mask);
UDP->UDP_CSR[epnum] = csr;
volatile uint32_t nop_count;
for (nop_count = 0; nop_count < 20; nop_count ++) __NOP();
} }
/*------------------------------------------------------------------*/ /*------------------------------------------------------------------*/
@ -140,7 +142,7 @@ static void bus_reset(void)
xfer_epsize_set(&_dcd_xfer[0], CFG_TUD_ENDPOINT0_SIZE); xfer_epsize_set(&_dcd_xfer[0], CFG_TUD_ENDPOINT0_SIZE);
// Enable EP0 control // Enable EP0 control
UDP->UDP_CSR[0] = UDP_CSR_EPEDS_Msk; csr_write(0, UDP_CSR_EPEDS_Msk);
// Enable interrupt : EP0, Suspend, Resume, Wakeup // Enable interrupt : EP0, Suspend, Resume, Wakeup
UDP->UDP_IER = UDP_IER_EP0INT_Msk | UDP_IER_RXSUSP_Msk | UDP_IER_RXRSM_Msk | UDP_IER_WAKEUP_Msk; UDP->UDP_IER = UDP_IER_EP0INT_Msk | UDP_IER_RXSUSP_Msk | UDP_IER_RXRSM_Msk | UDP_IER_WAKEUP_Msk;
@ -257,7 +259,7 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc)
xfer_epsize_set(&_dcd_xfer[epnum], ep_desc->wMaxPacketSize.size); xfer_epsize_set(&_dcd_xfer[epnum], ep_desc->wMaxPacketSize.size);
// Configure type and enable EP // Configure type and enable EP
UDP->UDP_CSR[epnum] = UDP_CSR_EPEDS_Msk | UDP_CSR_EPTYPE(ep_desc->bmAttributes.xfer + 4*dir); csr_write(epnum, UDP_CSR_EPEDS_Msk | UDP_CSR_EPTYPE(ep_desc->bmAttributes.xfer + 4*dir));
// Enable EP Interrupt for IN // Enable EP Interrupt for IN
if (dir == TUSB_DIR_IN) UDP->UDP_IER |= (1 << epnum); if (dir == TUSB_DIR_IN) UDP->UDP_IER |= (1 << epnum);