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add note for max3421e is not signal compatible with pca10056/95

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hathach 2024-03-22 11:12:40 +07:00
parent 60764de564
commit 08b09926a4
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GPG Key ID: 26FAB84F615C3C52
3 changed files with 13 additions and 24 deletions
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11
hw/bsp/nrf/boards/pca10056/board.h
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@ -46,11 +46,12 @@
#define UART_TX_PIN 6 #define UART_TX_PIN 6
// SPI for USB host shield // SPI for USB host shield
#define MAX3421_SCK_PIN _PINNUM(1, 15) // Pin is correct but not working probably due to signal incompatible (1.8V 3v3) with MAC3421E !?
#define MAX3421_MOSI_PIN _PINNUM(1, 13) //#define MAX3421_SCK_PIN _PINNUM(1, 15)
#define MAX3421_MISO_PIN _PINNUM(1, 14) //#define MAX3421_MOSI_PIN _PINNUM(1, 13)
#define MAX3421_CS_PIN _PINNUM(1, 12) //#define MAX3421_MISO_PIN _PINNUM(1, 14)
#define MAX3421_INTR_PIN _PINNUM(1, 11) //#define MAX3421_CS_PIN _PINNUM(1, 12)
//#define MAX3421_INTR_PIN _PINNUM(1, 11)
#ifdef __cplusplus #ifdef __cplusplus
} }

11
hw/bsp/nrf/boards/pca10095/board.h
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@ -46,11 +46,12 @@
#define UART_TX_PIN 20 #define UART_TX_PIN 20
// SPI for USB host shield // SPI for USB host shield
#define MAX3421_SCK_PIN _PINNUM(1, 15) // Pin is correct but not working probably due to signal incompatible (1.8V 3v3) with MAC3421E !?
#define MAX3421_MOSI_PIN _PINNUM(1, 13) //#define MAX3421_SCK_PIN _PINNUM(1, 15)
#define MAX3421_MISO_PIN _PINNUM(1, 14) //#define MAX3421_MOSI_PIN _PINNUM(1, 13)
#define MAX3421_CS_PIN _PINNUM(1, 12) //#define MAX3421_MISO_PIN _PINNUM(1, 14)
#define MAX3421_INTR_PIN _PINNUM(1, 11) //#define MAX3421_CS_PIN _PINNUM(1, 12)
//#define MAX3421_INTR_PIN _PINNUM(1, 11)
#ifdef __cplusplus #ifdef __cplusplus
} }

15
hw/bsp/nrf/family.c
View File

@ -292,20 +292,7 @@ void max3421_int_handler(nrfx_gpiote_pin_t pin, nrf_gpiote_polarity_t action) {
} }
static void max3421_init(void) { static void max3421_init(void) {
// MAX3421 need 3.3v signal (may not be needed) // Somehow pca10056/95 is not working probably due to signal incompatible (1.8V 3v3) with MAC3421E !?
// #if defined(UICR_REGOUT0_VOUT_Msk)
// if ((NRF_UICR->REGOUT0 & UICR_REGOUT0_VOUT_Msk) != UICR_REGOUT0_VOUT_3V3) {
// NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
// while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
//
// NRF_UICR->REGOUT0 = (NRF_UICR->REGOUT0 & ~UICR_REGOUT0_VOUT_Msk) | UICR_REGOUT0_VOUT_3V3;
//
// NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
// while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
//
// NVIC_SystemReset();
// }
// #endif
// manually manage CS // manually manage CS
nrf_gpio_cfg_output(MAX3421_CS_PIN); nrf_gpio_cfg_output(MAX3421_CS_PIN);