2019-11-11 19:42:24 +00:00
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#pragma once
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#include <stdint.h>
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#define MT_FW_RESOURCE "Firmware.bin"
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#define MT_MCU_ILM_OFFSET 0x80000
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#define MT_MCU_DLM_OFFSET 0x100000 + 0x10800
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#define MT_FW_CHUNK_SIZE 0x3800
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#define MT_DMA_COMPLETE 0xc0000000
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#define MT_FW_LOAD_IVB 0x12
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2019-11-12 17:55:50 +00:00
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#define MT_FCE_DMA_ADDR 0x0230
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#define MT_FCE_DMA_LEN 0x0234
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#define MT_USB_DMA_CFG 0x0238
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#define MT_USB_U3DMA_CFG 0x9018
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#define MT_FCE_PSE_CTRL 0x0800
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#define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0
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#define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4
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#define MT_TX_CPU_FROM_FCE_CPU_DESC_IDX 0x09a8
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#define MT_FCE_PDMA_GLOBAL_CONF 0x09c4
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#define MT_FCE_SKIP_FS 0x0a6c
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struct FwHeader
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{
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uint32_t ilmLength;
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uint32_t dlmLength;
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uint16_t buildVersion;
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uint16_t firmwareVersion;
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uint32_t padding;
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char buildTime[16];
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} __attribute__((packed));
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union DmaConfig {
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struct
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{
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uint32_t rxBulkAggTimeout : 8;
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uint32_t rxBulkAggLimit : 8;
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uint32_t udmaTxWlDrop : 1;
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uint32_t wakeupEnabled : 1;
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uint32_t rxDropOrPad : 1;
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uint32_t txClear : 1;
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uint32_t txopHalt : 1;
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uint32_t rxBulkAggEnabled : 1;
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uint32_t rxBulkEnabled : 1;
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uint32_t txBulkEnabled : 1;
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uint32_t epOutValid : 6;
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uint32_t rxBusy : 1;
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uint32_t txBusy : 1;
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} __attribute__((packed));
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uint32_t value;
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};
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