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https://github.com/RPCS3/rpcs3.git
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495 lines
13 KiB
C++
495 lines
13 KiB
C++
#pragma once
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#include "PPCThread.h"
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#include "Emu/event.h"
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#include "MFC.h"
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static const wxString spu_reg_name[128] =
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{
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"$LR", "$SP", "$2", "$3", "$4", "$5", "$6", "$7",
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"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
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"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
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"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
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"$32", "$33", "$34", "$35", "$36", "$37", "$38", "$39",
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"$40", "$41", "$42", "$43", "$44", "$45", "$46", "$47",
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"$48", "$49", "$50", "$51", "$52", "$53", "$54", "$55",
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"$56", "$57", "$58", "$59", "$60", "$61", "$62", "$63",
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"$64", "$65", "$66", "$67", "$68", "$69", "$70", "$71",
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"$72", "$73", "$74", "$75", "$76", "$77", "$78", "$79",
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"$80", "$81", "$82", "$83", "$84", "$85", "$86", "$87",
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"$88", "$89", "$90", "$91", "$92", "$93", "$94", "$95",
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"$96", "$97", "$98", "$99", "$100", "$101", "$102", "$103",
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"$104", "$105", "$106", "$107", "$108", "$109", "$110", "$111",
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"$112", "$113", "$114", "$115", "$116", "$117", "$118", "$119",
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"$120", "$121", "$122", "$123", "$124", "$125", "$126", "$127",
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};
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//SPU reg $0 is a dummy reg, and is used for certain instructions.
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static const wxString spu_specialreg_name[128] = {
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"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
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"$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
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"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
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"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31",
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"$32", "$33", "$34", "$35", "$36", "$37", "$38", "$39",
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"$40", "$41", "$42", "$43", "$44", "$45", "$46", "$47",
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"$48", "$49", "$50", "$51", "$52", "$53", "$54", "$55",
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"$56", "$57", "$58", "$59", "$60", "$61", "$62", "$63",
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"$64", "$65", "$66", "$67", "$68", "$69", "$70", "$71",
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"$72", "$73", "$74", "$75", "$76", "$77", "$78", "$79",
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"$80", "$81", "$82", "$83", "$84", "$85", "$86", "$87",
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"$88", "$89", "$90", "$91", "$92", "$93", "$94", "$95",
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"$96", "$97", "$98", "$99", "$100", "$101", "$102", "$103",
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"$104", "$105", "$106", "$107", "$108", "$109", "$110", "$111",
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"$112", "$113", "$114", "$115", "$116", "$117", "$118", "$119",
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"$120", "$121", "$122", "$123", "$124", "$125", "$126", "$127",
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};
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static const wxString spu_ch_name[128] =
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{
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"$SPU_RdEventStat", "$SPU_WrEventMask", "$SPU_WrEventAck", "$SPU_RdSigNotify1",
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"$SPU_RdSigNotify2", "$ch5", "$ch6", "$SPU_WrDec", "$SPU_RdDec",
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"$MFC_WrMSSyncReq", "$ch10", "$SPU_RdEventMask", "$MFC_RdTagMask", "$SPU_RdMachStat",
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"$SPU_WrSRR0", "$SPU_RdSRR0", "$MFC_LSA", "$MFC_EAH", "$MFC_EAL", "$MFC_Size",
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"$MFC_TagID", "$MFC_Cmd", "$MFC_WrTagMask", "$MFC_WrTagUpdate", "$MFC_RdTagStat",
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"$MFC_RdListStallStat", "$MFC_WrListStallAck", "$MFC_RdAtomicStat",
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"$SPU_WrOutMbox", "$SPU_RdInMbox", "$SPU_WrOutIntrMbox", "$ch31", "$ch32",
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"$ch33", "$ch34", "$ch35", "$ch36", "$ch37", "$ch38", "$ch39", "$ch40",
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"$ch41", "$ch42", "$ch43", "$ch44", "$ch45", "$ch46", "$ch47", "$ch48",
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"$ch49", "$ch50", "$ch51", "$ch52", "$ch53", "$ch54", "$ch55", "$ch56",
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"$ch57", "$ch58", "$ch59", "$ch60", "$ch61", "$ch62", "$ch63", "$ch64",
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"$ch65", "$ch66", "$ch67", "$ch68", "$ch69", "$ch70", "$ch71", "$ch72",
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"$ch73", "$ch74", "$ch75", "$ch76", "$ch77", "$ch78", "$ch79", "$ch80",
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"$ch81", "$ch82", "$ch83", "$ch84", "$ch85", "$ch86", "$ch87", "$ch88",
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"$ch89", "$ch90", "$ch91", "$ch92", "$ch93", "$ch94", "$ch95", "$ch96",
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"$ch97", "$ch98", "$ch99", "$ch100", "$ch101", "$ch102", "$ch103", "$ch104",
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"$ch105", "$ch106", "$ch107", "$ch108", "$ch109", "$ch110", "$ch111", "$ch112",
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"$ch113", "$ch114", "$ch115", "$ch116", "$ch117", "$ch118", "$ch119", "$ch120",
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"$ch121", "$ch122", "$ch123", "$ch124", "$ch125", "$ch126", "$ch127",
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};
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enum SPUchannels
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{
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SPU_RdEventStat = 0, //Read event status with mask applied
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SPU_WrEventMask = 1, //Write event mask
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SPU_WrEventAck = 2, //Write end of event processing
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SPU_RdSigNotify1 = 3, //Signal notification 1
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SPU_RdSigNotify2 = 4, //Signal notification 2
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SPU_WrDec = 7, //Write decrementer count
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SPU_RdDec = 8, //Read decrementer count
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SPU_RdEventMask = 11, //Read event mask
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SPU_RdMachStat = 13, //Read SPU run status
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SPU_WrSRR0 = 14, //Write SPU machine state save/restore register 0 (SRR0)
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SPU_RdSRR0 = 15, //Read SPU machine state save/restore register 0 (SRR0)
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SPU_WrOutMbox = 28, //Write outbound mailbox contents
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SPU_RdInMbox = 29, //Read inbound mailbox contents
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SPU_WrOutIntrMbox = 30, //Write outbound interrupt mailbox contents (interrupting PPU)
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};
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enum MFCchannels
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{
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MFC_WrMSSyncReq = 9, //Write multisource synchronization request
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MFC_RdTagMask = 12, //Read tag mask
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MFC_LSA = 16, //Write local memory address command parameter
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MFC_EAH = 17, //Write high order DMA effective address command parameter
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MFC_EAL = 18, //Write low order DMA effective address command parameter
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MFC_Size = 19, //Write DMA transfer size command parameter
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MFC_TagID = 20, //Write tag identifier command parameter
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MFC_Cmd = 21, //Write and enqueue DMA command with associated class ID
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MFC_WrTagMask = 22, //Write tag mask
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MFC_WrTagUpdate = 23, //Write request for conditional or unconditional tag status update
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MFC_RdTagStat = 24, //Read tag status with mask applied
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MFC_RdListStallStat = 25, //Read DMA list stall-and-notify status
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MFC_WrListStallAck = 26, //Write DMA list stall-and-notify acknowledge
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MFC_RdAtomicStat = 27, //Read completion status of last completed immediate MFC atomic update command
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};
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enum
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{
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SPU_RUNCNTL_STOP = 0,
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SPU_RUNCNTL_RUNNABLE = 1,
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};
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enum
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{
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SPU_STATUS_STOPPED = 0x0,
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SPU_STATUS_RUNNING = 0x1,
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SPU_STATUS_STOPPED_BY_STOP = 0x2,
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SPU_STATUS_STOPPED_BY_HALT = 0x4,
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SPU_STATUS_WAITING_FOR_CHANNEL = 0x8,
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SPU_STATUS_SINGLE_STEP = 0x10,
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};
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//Floating point status and control register. Unsure if this is one of the GPRs or SPRs
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//Is 128 bits, but bits 0-19, 24-28, 32-49, 56-60, 64-81, 88-92, 96-115, 120-124 are unused
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class FPSCR
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{
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public:
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u64 low;
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u64 hi;
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FPSCR() {}
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wxString ToString() const
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{
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return "FPSCR writer not yet implemented"; //wxString::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
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}
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void Reset()
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{
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memset(this, 0, sizeof(*this));
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}
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//slice -> 0 - 1 (4 slices total, only two have rounding)
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//0 -> round even
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//1 -> round towards zero (truncate)
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//2 -> round towards positive inf
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//3 -> round towards neg inf
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void setSliceRounding(u8 slice, u8 roundTo)
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{
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u64 mask = roundTo;
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switch(slice)
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{
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case 0:
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mask = mask << 20;
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break;
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case 1:
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mask = mask << 22;
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break;
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}
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//rounding is located in the low end of the FPSCR
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this->low = this->low & mask;
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}
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//Slice 0 or 1
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u8 checkSliceRounding(u8 slice)
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{
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switch(slice)
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{
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case 0:
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return this->low >> 20 & 0x3;
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case 1:
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return this->low >> 22 & 0x3;
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}
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}
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//Single Precision Exception Flags (all 3 slices)
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//slice -> slice number (0-3)
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//exception: 1 -> Overflow 2 -> Underflow 4-> Diff (could be IE^3 non compliant)
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void setSinglePrecisionExceptionFlags(u8 slice, u8 exception)
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{
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u64 mask = exception;
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switch(slice)
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{
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case 0:
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mask = mask << 29;
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this->low = this->low & mask;
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break;
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case 1:
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mask = mask << 61;
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this->low = this->low & mask;
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break;
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case 2:
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mask = mask << 29;
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this->hi = this->hi & mask;
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break;
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case 3:
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mask = mask << 61;
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this->hi = this->hi & mask;
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break;
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}
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}
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};
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union SPU_GPR_hdr
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{
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u128 _u128;
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s128 _i128;
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__m128 _m128;
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u64 _u64[2];
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s64 _i64[2];
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u32 _u32[4];
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s32 _i32[4];
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u16 _u16[8];
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s16 _i16[8];
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u8 _u8[16];
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s8 _i8[16];
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double _d[2];
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float _f[4];
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SPU_GPR_hdr() {}
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wxString ToString() const
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{
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return wxString::Format("%08x%08x%08x%08x", _u32[3], _u32[2], _u32[1], _u32[0]);
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}
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void Reset()
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{
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memset(this, 0, sizeof(*this));
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}
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};
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union SPU_SPR_hdr
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{
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u128 _u128;
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s128 _i128;
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SPU_SPR_hdr() {}
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wxString ToString() const
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{
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return wxString::Format("%16%16", _u128.hi, _u128.lo);
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}
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void Reset()
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{
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memset(this, 0, sizeof(*this));
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}
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};
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class SPUThread : public PPCThread
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{
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public:
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SPU_GPR_hdr GPR[128]; //General-Purpose Register
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SPU_SPR_hdr SPR[128]; //Special-Purpose Registers
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FPSCR FPSCR;
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template<size_t _max_count>
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class Channel
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{
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public:
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static const size_t max_count = _max_count;
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private:
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u32 m_value[max_count];
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u32 m_index;
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public:
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Channel()
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{
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Init();
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}
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void Init()
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{
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m_index = 0;
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}
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__forceinline bool Pop(u32& res)
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{
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if(!m_index) return false;
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res = m_value[--m_index];
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return true;
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}
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__forceinline bool Push(u32 value)
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{
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if(m_index >= max_count) return false;
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m_value[m_index++] = value;
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return true;
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}
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u32 GetCount() const
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{
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return m_index;
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}
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u32 GetFreeCount() const
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{
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return max_count - m_index;
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}
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void SetValue(u32 value)
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{
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m_value[0] = value;
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}
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u32 GetValue() const
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{
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return m_value[0];
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}
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};
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struct
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{
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Channel<1> LSA;
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Channel<1> EAH;
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Channel<1> EAL;
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Channel<1> Size_Tag;
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Channel<1> CMDStatus;
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Channel<1> QStatus;
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} MFC;
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struct
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{
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Channel<1> QueryType;
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Channel<1> QueryMask;
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Channel<1> TagStatus;
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} Prxy;
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struct
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{
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Channel<1> Out_MBox;
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Channel<1> OutIntr_Mbox;
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Channel<4> In_MBox;
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Channel<1> MBox_Status;
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Channel<1> RunCntl;
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Channel<1> Status;
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Channel<1> NPC;
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Channel<1> RdSigNotify1;
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Channel<1> RdSigNotify2;
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} SPU;
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u32 LSA;
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union
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{
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u64 EA;
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struct { u32 EAH, EAL; };
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};
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DMAC dmac;
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u32 GetChannelCount(u32 ch)
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{
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switch(ch)
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{
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case SPU_WrOutMbox:
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return SPU.Out_MBox.GetFreeCount();
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case SPU_RdInMbox:
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return SPU.In_MBox.GetCount();
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case SPU_WrOutIntrMbox:
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return 0;//return SPU.OutIntr_Mbox.GetFreeCount();
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default:
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ConLog.Error("%s error: unknown/illegal channel (%d).", __FUNCTION__, ch);
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break;
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}
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return 0;
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}
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void WriteChannel(u32 ch, const SPU_GPR_hdr& r)
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{
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const u32 v = r._u32[3];
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switch(ch)
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{
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case SPU_WrOutIntrMbox:
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ConLog.Warning("SPU_WrOutIntrMbox = 0x%x", v);
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while(!SPU.OutIntr_Mbox.Push(v) && !Emu.IsStopped())
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{
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Sleep(1);
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}
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break;
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case SPU_WrOutMbox:
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ConLog.Warning("SPU_WrOutMbox = 0x%x", v);
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while(!SPU.Out_MBox.Push(v) && !Emu.IsStopped())
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{
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Sleep(1);
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}
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break;
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default:
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ConLog.Error("%s error: unknown/illegal channel (%d).", __FUNCTION__, ch);
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break;
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}
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}
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void ReadChannel(SPU_GPR_hdr& r, u32 ch)
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{
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r.Reset();
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u32& v = r._u32[3];
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switch(ch)
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{
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case SPU_RdInMbox:
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if(!SPU.In_MBox.Pop(v)) v = 0;
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ConLog.Warning("%s: SPU_RdInMbox(0x%x).", __FUNCTION__, v);
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break;
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default:
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ConLog.Error("%s error: unknown/illegal channel (%d).", __FUNCTION__, ch);
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break;
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}
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}
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bool IsGoodLSA(const u32 lsa) const { return Memory.IsGoodAddr(lsa + m_offset) && lsa < 0x40000; }
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virtual u8 ReadLS8 (const u32 lsa) const { return Memory.Read8 (lsa + (m_offset & 0x3fffc)); }
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virtual u16 ReadLS16 (const u32 lsa) const { return Memory.Read16 (lsa + m_offset); }
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virtual u32 ReadLS32 (const u32 lsa) const { return Memory.Read32 (lsa + m_offset); }
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virtual u64 ReadLS64 (const u32 lsa) const { return Memory.Read64 (lsa + m_offset); }
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virtual u128 ReadLS128(const u32 lsa) const { return Memory.Read128(lsa + m_offset); }
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virtual void WriteLS8 (const u32 lsa, const u8& data) const { Memory.Write8 (lsa + m_offset, data); }
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virtual void WriteLS16 (const u32 lsa, const u16& data) const { Memory.Write16 (lsa + m_offset, data); }
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virtual void WriteLS32 (const u32 lsa, const u32& data) const { Memory.Write32 (lsa + m_offset, data); }
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virtual void WriteLS64 (const u32 lsa, const u64& data) const { Memory.Write64 (lsa + m_offset, data); }
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virtual void WriteLS128(const u32 lsa, const u128& data) const { Memory.Write128(lsa + m_offset, data); }
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public:
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SPUThread(CPUThreadType type = CPU_THREAD_SPU);
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~SPUThread();
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virtual wxString RegsToString()
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{
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wxString ret = "Registers:\n=========\n";
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for(uint i=0; i<128; ++i) ret += wxString::Format("GPR[%d] = 0x%s\n", i, GPR[i].ToString().mb_str());
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return ret;
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}
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virtual wxString ReadRegString(wxString reg)
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{
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if (reg.Contains("["))
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{
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long reg_index;
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reg.AfterFirst('[').RemoveLast().ToLong(®_index);
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if (reg.StartsWith("GPR")) return wxString::Format("%016llx%016llx", GPR[reg_index]._u64[1], GPR[reg_index]._u64[0]);
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}
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return wxEmptyString;
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}
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bool WriteRegString(wxString reg, wxString value)
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{
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while (value.Len() < 32) value = "0"+value;
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if (reg.Contains("["))
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{
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long reg_index;
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reg.AfterFirst('[').RemoveLast().ToLong(®_index);
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if (reg.StartsWith("GPR"))
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{
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unsigned long long reg_value0;
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unsigned long long reg_value1;
|
|
if (!value.SubString(16,31).ToULongLong(®_value0, 16)) return false;
|
|
if (!value.SubString(0,15).ToULongLong(®_value1, 16)) return false;
|
|
GPR[reg_index]._u64[0] = (u64)reg_value0;
|
|
GPR[reg_index]._u64[1] = (u64)reg_value1;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
public:
|
|
virtual void InitRegs();
|
|
virtual u64 GetFreeStackSize() const;
|
|
|
|
protected:
|
|
virtual void DoReset();
|
|
virtual void DoRun();
|
|
virtual void DoPause();
|
|
virtual void DoResume();
|
|
virtual void DoStop();
|
|
};
|
|
|
|
SPUThread& GetCurrentSPUThread();
|