From eb2ab73e1667b341604988d974c6c1f9f12fd8a2 Mon Sep 17 00:00:00 2001 From: DH Date: Tue, 24 Dec 2013 07:25:15 +0200 Subject: [PATCH] Implemented LWZUX, LWAX, LWAUX, LHA, LHAU, LWA, STWBRX, STHBRX. --- rpcs3/Emu/Cell/PPUDisAsm.h | 42 +++++++++++++++++++++++++++++---- rpcs3/Emu/Cell/PPUInstrTable.h | 9 +++++++ rpcs3/Emu/Cell/PPUInterpreter.h | 38 +++++++++++++++++++++++++++++ rpcs3/Emu/Cell/PPUOpcodes.h | 14 +++++++++++ 4 files changed, 98 insertions(+), 5 deletions(-) diff --git a/rpcs3/Emu/Cell/PPUDisAsm.h b/rpcs3/Emu/Cell/PPUDisAsm.h index f071b88a2b..2011dcff32 100644 --- a/rpcs3/Emu/Cell/PPUDisAsm.h +++ b/rpcs3/Emu/Cell/PPUDisAsm.h @@ -1291,7 +1291,7 @@ private: } void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) { - DisAsm_R3_OE_RC("subf", rd, ra, rb, oe, rc); + DisAsm_R3_OE_RC("subf", rd, ra, rb, oe, rc); } void LDUX(u32 rd, u32 ra, u32 rb) { @@ -1301,6 +1301,10 @@ private: { DisAsm_R2("dcbst", ra, rb); } + void LWZUX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lwzux", rd, ra, rb); + } void CNTLZD(u32 ra, u32 rs, bool rc) { DisAsm_R2_RC("cntlzd", ra, rs, rc); @@ -1482,6 +1486,10 @@ private: default: DisAsm_R1_IMM("mfspr", rd, spr); break; } } + void LWAX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lwax", rd, ra, rb); + } void DST(u32 ra, u32 rb, u32 strm, u32 t) { if(t) @@ -1511,6 +1519,10 @@ private: default: DisAsm_R1_IMM("mftb", rd, spr); break; } } + void LWAUX(u32 rd, u32 ra, u32 rb) + { + DisAsm_R3("lwaux", rd, ra, rb); + } void DSTST(u32 ra, u32 rb, u32 strm, u32 t) { if(t) @@ -1630,9 +1642,13 @@ private: { DisAsm_F1_R2("lfdux", frd, ra, rb); } - void STVLX(u32 sd, u32 ra, u32 rb) + void STVLX(u32 vs, u32 ra, u32 rb) { - DisAsm_V1_R2("stvlx", sd, ra, rb); + DisAsm_V1_R2("stvlx", vs, ra, rb); + } + void STWBRX(u32 rs, u32 ra, u32 rb) + { + DisAsm_R3("stwbrx", rs, ra, rb); } void STFSX(u32 frs, u32 ra, u32 rb) { @@ -1693,9 +1709,13 @@ private: { Write("eieio"); } - void STVLXL(u32 sd, u32 ra, u32 rb) + void STVLXL(u32 vs, u32 ra, u32 rb) { - DisAsm_V1_R2("stvlxl", sd, ra, rb); + DisAsm_V1_R2("stvlxl", vs, ra, rb); + } + void STHBRX(u32 rs, u32 ra, u32 rb) + { + DisAsm_R3("sthbrx", rs, ra, rb); } void EXTSH(u32 ra, u32 rs, bool rc) { @@ -1762,6 +1782,14 @@ private: { DisAsm_R2_IMM("lhzu", rs, ra, d); } + void LHA(u32 rs, u32 ra, s32 d) + { + DisAsm_R2_IMM("lha", rs, ra, d); + } + void LHAU(u32 rs, u32 ra, s32 d) + { + DisAsm_R2_IMM("lhau", rs, ra, d); + } void STH(u32 rs, u32 ra, s32 d) { DisAsm_R2_IMM("sth", rs, ra, d); @@ -1818,6 +1846,10 @@ private: { DisAsm_R2_IMM("ldu", rd, ra, ds); } + void LWA(u32 rd, u32 ra, s32 ds) + { + DisAsm_R2_IMM("lwa", rd, ra, ds); + } void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) { DisAsm_F3_RC("fdivs", frd, fra, frb, rc); diff --git a/rpcs3/Emu/Cell/PPUInstrTable.h b/rpcs3/Emu/Cell/PPUInstrTable.h index 3ca379c35d..c7b90aede8 100644 --- a/rpcs3/Emu/Cell/PPUInstrTable.h +++ b/rpcs3/Emu/Cell/PPUInstrTable.h @@ -250,6 +250,8 @@ namespace PPU_instr bind_instr(main_list, STBU, RS, RA, D); bind_instr(main_list, LHZ, RD, RA, D); bind_instr(main_list, LHZU, RD, RA, D); + bind_instr(main_list, LHA, RD, RA, D); + bind_instr(main_list, LHAU, RD, RA, D); bind_instr(main_list, STH, RS, RA, D); bind_instr(main_list, STHU, RS, RA, D); bind_instr(main_list, LMW, RD, RA, D); @@ -460,7 +462,9 @@ namespace PPU_instr /*0x026*/bind_instr(g1f_list, LVSR, VD, RA, RB); /*0x027*/bind_instr(g1f_list, LVEHX, VD, RA, RB); /*0x028*/bind_instr(g1f_list, SUBF, RD, RA, RB, OE, RC); + /*0x035*/bind_instr(g1f_list, LDUX, RD, RA, RB); /*0x036*/bind_instr(g1f_list, DCBST, RA, RB); + /*0x037*/bind_instr(g1f_list, LWZUX, RD, RA, RB); /*0x03a*/bind_instr(g1f_list, CNTLZD, RA, RS, RC); /*0x03c*/bind_instr(g1f_list, ANDC, RA, RS, RB, RC); /*0x047*/bind_instr(g1f_list, LVEWX, VD, RA, RB); @@ -501,10 +505,12 @@ namespace PPU_instr /*0x137*/bind_instr(g1f_list, LHZUX, RD, RA, RB); /*0x13c*/bind_instr(g1f_list, XOR, RA, RS, RB, RC); /*0x153*/bind_instr(g1f_list, MFSPR, RD, SPR); + /*0x155*/bind_instr(g1f_list, LWAX, RD, RA, RB); /*0x156*/bind_instr(g1f_list, DST, RA, RB, STRM, L_6); /*0x157*/bind_instr(g1f_list, LHAX, RD, RA, RB); /*0x167*/bind_instr(g1f_list, LVXL, VD, RA, RB); /*0x173*/bind_instr(g1f_list, MFTB, RD, SPR); + /*0x175*/bind_instr(g1f_list, LWAUX, RD, RA, RB); /*0x176*/bind_instr(g1f_list, DSTST, RA, RB, STRM, L_6); /*0x177*/bind_instr(g1f_list, LHAUX, RD, RA, RB); /*0x197*/bind_instr(g1f_list, STHX, RS, RA, RB); @@ -531,6 +537,7 @@ namespace PPU_instr /*0x257*/bind_instr(g1f_list, LFDX, FRD, RA, RB); /*0x277*/bind_instr(g1f_list, LFDUX, FRD, RA, RB); /*0x287*/bind_instr(g1f_list, STVLX, VS, RA, RB); + /*0x296*/bind_instr(g1f_list, STWBRX, RS, RA, RB); /*0x297*/bind_instr(g1f_list, STFSX, FRS, RA, RB); /*0x2a7*/bind_instr(g1f_list, STVRX, VS, RA, RB); /*0x2d7*/bind_instr(g1f_list, STFDX, FRS, RA, RB); @@ -545,6 +552,7 @@ namespace PPU_instr /*0x33b*/bind_instr(g1f_list, SRADI2, RA, RS, sh, RC); /*0x356*/bind_instr(g1f_list, EIEIO); /*0x387*/bind_instr(g1f_list, STVLXL, VS, RA, RB); + /*0x396*/bind_instr(g1f_list, STHBRX, RS, RA, RB); /*0x39a*/bind_instr(g1f_list, EXTSH, RA, RS, RC); /*0x387*/bind_instr(g1f_list, STVRXL, VS, RA, RB); /*0x3ba*/bind_instr(g1f_list, EXTSB, RA, RS, RC); @@ -555,6 +563,7 @@ namespace PPU_instr bind_instr(g3a_list, LD, RD, RA, DS); bind_instr(g3a_list, LDU, RD, RA, DS); + bind_instr(g3a_list, LWA, RD, RA, DS); bind_instr(g3b_list, FDIVS, FRD, FRA, FRB, RC); bind_instr(g3b_list, FSUBS, FRD, FRA, FRB, RC); diff --git a/rpcs3/Emu/Cell/PPUInterpreter.h b/rpcs3/Emu/Cell/PPUInterpreter.h index 970b7de510..485c055cfa 100644 --- a/rpcs3/Emu/Cell/PPUInterpreter.h +++ b/rpcs3/Emu/Cell/PPUInterpreter.h @@ -2452,6 +2452,12 @@ private: { //UNK("dcbst", false); } + void LWZUX(u32 rd, u32 ra, u32 rb) + { + const u64 addr = CPU.GPR[ra] + CPU.GPR[rb]; + CPU.GPR[rd] = Memory.Read32(addr); + CPU.GPR[ra] = addr; + } void CNTLZD(u32 ra, u32 rs, bool rc) { u32 i; @@ -2773,6 +2779,10 @@ private: { CPU.GPR[rd] = GetRegBySPR(spr); } + void LWAX(u32 rd, u32 ra, u32 rb) + { + CPU.GPR[rd] = (s64)(s32)Memory.Read32(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]); + } void DST(u32 ra, u32 rb, u32 strm, u32 t) { } @@ -2795,6 +2805,12 @@ private: default: UNK(wxString::Format("mftb r%d, %d", rd, spr)); break; } } + void LWAUX(u32 rd, u32 ra, u32 rb) + { + const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; + CPU.GPR[rd] = (s64)(s32)Memory.Read32(addr); + CPU.GPR[ra] = addr; + } void DSTST(u32 ra, u32 rb, u32 strm, u32 t) { } @@ -2981,6 +2997,10 @@ private: Memory.WriteLeft(addr, 16 - eb, CPU.VPR[vs]._u8 + eb); } + void STWBRX(u32 rs, u32 ra, u32 rb) + { + (u32&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]] = CPU.GPR[rs]; + } void STFSX(u32 frs, u32 ra, u32 rb) { Memory.Write32((ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]), CPU.FPR[frs].To32()); @@ -3065,6 +3085,10 @@ private: Memory.WriteLeft(addr, 16 - eb, CPU.VPR[vs]._u8 + eb); } + void STHBRX(u32 rs, u32 ra, u32 rb) + { + (u16&)Memory[ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]] = CPU.GPR[rs]; + } void EXTSH(u32 ra, u32 rs, bool rc) { CPU.GPR[ra] = (s64)(s16)CPU.GPR[rs]; @@ -3146,6 +3170,16 @@ private: CPU.GPR[rd] = Memory.Read16(addr); CPU.GPR[ra] = addr; } + void LHA(u32 rd, u32 ra, s32 d) + { + CPU.GPR[rd] = (s64)(s16)Memory.Read16(ra ? CPU.GPR[ra] + d : d); + } + void LHAU(u32 rd, u32 ra, s32 d) + { + const u64 addr = CPU.GPR[ra] + d; + CPU.GPR[rd] = (s64)(s16)Memory.Read16(addr); + CPU.GPR[ra] = addr; + } void STH(u32 rs, u32 ra, s32 d) { Memory.Write16(ra ? CPU.GPR[ra] + d : d, CPU.GPR[rs]); @@ -3225,6 +3259,10 @@ private: CPU.GPR[rd] = Memory.Read64(addr); CPU.GPR[ra] = addr; } + void LWA(u32 rd, u32 ra, s32 ds) + { + CPU.GPR[rd] = (s64)(s32)Memory.Read32(ra ? CPU.GPR[ra] + ds : ds); + } void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) { if(FPRdouble::IsNaN(CPU.FPR[fra])) diff --git a/rpcs3/Emu/Cell/PPUOpcodes.h b/rpcs3/Emu/Cell/PPUOpcodes.h index 219d63d7a8..71a8d3b2f1 100644 --- a/rpcs3/Emu/Cell/PPUOpcodes.h +++ b/rpcs3/Emu/Cell/PPUOpcodes.h @@ -276,6 +276,7 @@ namespace PPU_opcodes SUBF = 0x028, LDUX = 0x035, //Load Doubleword with Update Indexed DCBST = 0x036, + LWZUX = 0x037, CNTLZD = 0x03a, ANDC = 0x03c, LVEWX = 0x047, //Load Vector Element Word Indexed @@ -317,10 +318,12 @@ namespace PPU_opcodes LHZUX = 0x137, XOR = 0x13c, MFSPR = 0x153, + LWAX = 0x155, DST = 0x156, //Data Stream Touch LHAX = 0x157, LVXL = 0x167, //Load Vector Indexed Last MFTB = 0x173, + LWAUX = 0x175, DSTST = 0x176, //Data Stream Touch for Store LHAUX = 0x177, STHX = 0x197, //Store Halfword Indexed @@ -347,6 +350,7 @@ namespace PPU_opcodes LFDX = 0x257, LFDUX = 0x277, STVLX = 0x287, //Store Vector Left Indexed + STWBRX = 0x296, STFSX = 0x297, STVRX = 0x2a7, //Store Vector Right Indexed STFDX = 0x2d7, //Store Floating-Point Double Indexed @@ -361,6 +365,7 @@ namespace PPU_opcodes SRADI2 = 0x33b, //sh_5 != 0 EIEIO = 0x356, STVLXL = 0x387, //Store Vector Left Indexed Last + STHBRX = 0x396, EXTSH = 0x39a, STVRXL = 0x3a7, //Store Vector Right Indexed Last EXTSB = 0x3ba, @@ -374,6 +379,7 @@ namespace PPU_opcodes { LD = 0x0, LDU = 0x1, + LWA = 0x2, }; enum G_3bOpcodes //Field 26 - 30 @@ -660,6 +666,7 @@ public: virtual void SUBF(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) = 0; virtual void LDUX(u32 rd, u32 ra, u32 rb) = 0; virtual void DCBST(u32 ra, u32 rb) = 0; + virtual void LWZUX(u32 rd, u32 ra, u32 rb) = 0; virtual void CNTLZD(u32 ra, u32 rs, bool rc) = 0; virtual void ANDC(u32 ra, u32 rs, u32 rb, bool rc) = 0; virtual void LVEWX(u32 vd, u32 ra, u32 rb) = 0; @@ -700,10 +707,12 @@ public: virtual void LHZUX(u32 rd, u32 ra, u32 rb) = 0; virtual void XOR(u32 rs, u32 ra, u32 rb, bool rc) = 0; virtual void MFSPR(u32 rd, u32 spr) = 0; + virtual void LWAX(u32 rd, u32 ra, u32 rb) = 0; virtual void DST(u32 ra, u32 rb, u32 strm, u32 t) = 0; virtual void LHAX(u32 rd, u32 ra, u32 rb) = 0; virtual void LVXL(u32 vd, u32 ra, u32 rb) = 0; virtual void MFTB(u32 rd, u32 spr) = 0; + virtual void LWAUX(u32 rd, u32 ra, u32 rb) = 0; virtual void DSTST(u32 ra, u32 rb, u32 strm, u32 t) = 0; virtual void LHAUX(u32 rd, u32 ra, u32 rb) = 0; virtual void STHX(u32 rs, u32 ra, u32 rb) = 0; @@ -730,6 +739,7 @@ public: virtual void LFDX(u32 frd, u32 ra, u32 rb) = 0; virtual void LFDUX(u32 frd, u32 ra, u32 rb) = 0; virtual void STVLX(u32 vs, u32 ra, u32 rb) = 0; + virtual void STWBRX(u32 rs, u32 ra, u32 rb) = 0; virtual void STFSX(u32 frs, u32 ra, u32 rb) = 0; virtual void STVRX(u32 vs, u32 ra, u32 rb) = 0; virtual void STFDX(u32 frs, u32 ra, u32 rb) = 0; @@ -744,6 +754,7 @@ public: virtual void SRADI2(u32 ra, u32 rs, u32 sh, bool rc) = 0; virtual void EIEIO() = 0; virtual void STVLXL(u32 vs, u32 ra, u32 rb) = 0; + virtual void STHBRX(u32 rs, u32 ra, u32 rb) = 0; virtual void EXTSH(u32 ra, u32 rs, bool rc) = 0; virtual void STVRXL(u32 sd, u32 ra, u32 rb) = 0; virtual void EXTSB(u32 ra, u32 rs, bool rc) = 0; @@ -761,6 +772,8 @@ public: virtual void STBU(u32 rs, u32 ra, s32 d) = 0; virtual void LHZ(u32 rd, u32 ra, s32 d) = 0; virtual void LHZU(u32 rd, u32 ra, s32 d) = 0; + virtual void LHA(u32 rs, u32 ra, s32 d) = 0; + virtual void LHAU(u32 rs, u32 ra, s32 d) = 0; virtual void STH(u32 rs, u32 ra, s32 d) = 0; virtual void STHU(u32 rs, u32 ra, s32 d) = 0; virtual void LMW(u32 rd, u32 ra, s32 d) = 0; @@ -775,6 +788,7 @@ public: virtual void STFDU(u32 frs, u32 ra, s32 d) = 0; virtual void LD(u32 rd, u32 ra, s32 ds) = 0; virtual void LDU(u32 rd, u32 ra, s32 ds) = 0; + virtual void LWA(u32 rd, u32 ra, s32 ds) = 0; virtual void FDIVS(u32 frd, u32 fra, u32 frb, bool rc) = 0; virtual void FSUBS(u32 frd, u32 fra, u32 frb, bool rc) = 0; virtual void FADDS(u32 frd, u32 fra, u32 frb, bool rc) = 0;