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https://github.com/RPCS3/rpcs3.git
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spursAddWorkload
This commit is contained in:
Nekotekina
parent
ae17ef4d68
commit
c53a822c4e
@ -103,6 +103,36 @@ public:
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}
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}
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// perform atomic operation on data with additional memory barrier
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template<typename FT> __forceinline void atomic_op_sync(const FT atomic_proc) volatile
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{
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T old = read_sync();
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while (true)
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{
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T _new = old;
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atomic_proc(_new); // function should accept reference to T type
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const T val = compare_and_swap(old, _new);
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if ((atomic_type&)val == (atomic_type&)old) return;
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old = val;
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}
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}
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// perform atomic operation on data with additional memory barrier and special exit condition (if intermediate result != proceed_value)
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template<typename RT, typename FT> __forceinline RT atomic_op_sync(const RT proceed_value, const FT atomic_proc) volatile
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{
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T old = read_sync();
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while (true)
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{
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T _new = old;
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RT res = (RT)atomic_proc(_new); // function should accept reference to T type and return some value
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if (res != proceed_value) return res;
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const T val = compare_and_swap(old, _new);
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if ((atomic_type&)val == (atomic_type&)old) return proceed_value;
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old = val;
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}
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}
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// perform non-atomic operation on data directly without memory barriers
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template<typename FT> __forceinline void direct_op(const FT direct_proc) volatile
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{
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direct_proc((T&)data);
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@ -122,6 +152,13 @@ public:
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return (T&)res;
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}
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// atomic bitwise AND NOT (inverts right argument), returns previous data
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__forceinline const T _and_not(const T& right) volatile
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{
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const atomic_type res = InterlockedAnd(&data, ~(atomic_type&)(right));
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return (T&)res;
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}
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// atomic bitwise XOR, returns previous data
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__forceinline const T _xor(const T& right) volatile
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{
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@ -92,7 +92,7 @@ s64 spursInit(
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if (!isSecond)
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{
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spurs->m.wklMask.write_relaxed(be_t<u32>::make(0xffff));
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spurs->m.wklMsk1.write_relaxed(be_t<u32>::make(0xffff));
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}
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spurs->m.unk6[0xC] = 0;
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spurs->m.unk6[0xD] = 0;
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@ -762,7 +762,7 @@ s64 cellSpursGetInfo(vm::ptr<CellSpurs> spurs, vm::ptr<CellSpursInfo> info)
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s64 spursWakeUp(vm::ptr<CellSpurs> spurs)
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{
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#ifdef PRX_DEBUG
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#ifdef PRX_DEBUG_XXX
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return cb_call<s32, vm::ptr<CellSpurs>>(GetCurrentPPUThread(), libsre + 0x84D8, libsre_rtoc, spurs);
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#endif
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if (!spurs)
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@ -809,7 +809,7 @@ s32 spursAddWorkload(
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vm::ptr<CellSpursShutdownCompletionEventHook> hook,
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vm::ptr<void> hookArg)
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{
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#ifdef PRX_DEBUG
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#ifdef PRX_DEBUG_XXX
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return cb_call<s32, vm::ptr<CellSpurs>, vm::ptr<u32>, vm::ptr<const void>, u32, u64, u32, u32, u32, u32, u32, u32, u32>(GetCurrentPPUThread(), libsre + 0x96EC, libsre_rtoc,
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spurs, wid, pm, size, data, Memory.RealToVirtualAddr(priorityTable), minContention, maxContention,
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nameClass.addr(), nameInstance.addr(), hook.addr(), hookArg.addr());
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@ -833,7 +833,7 @@ s32 spursAddWorkload(
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u32 wnum;
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const u32 wmax = spurs->m.x70.read_relaxed().flags1 & 0x40 ? 0x20 : 0x10; // check isSecond (TODO: check if can be changed)
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spurs->m.wklMask.atomic_op([spurs, wmax, &wnum](be_t<u32>& value)
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spurs->m.wklMsk1.atomic_op([spurs, wmax, &wnum](be_t<u32>& value)
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{
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wnum = cntlz32(~(u32)value); // found empty position
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if (wnum < wmax)
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@ -848,10 +848,11 @@ s32 spursAddWorkload(
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return CELL_SPURS_POLICY_MODULE_ERROR_AGAIN;
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}
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u32 index = wnum % 0x10;
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if (wnum <= 15)
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{
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assert((spurs->m.wklA1[wnum] & 0xf) == 0);
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assert((spurs->m.wklB1[wnum] & 0xf) == 0);
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assert((spurs->m.wklA[wnum] & 0xf) == 0);
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assert((spurs->m.wklB[wnum] & 0xf) == 0);
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spurs->m.wklC1[wnum] = 1;
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spurs->m.wklD1[wnum] = 0;
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spurs->m.wklE1[wnum] = 0;
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@ -861,29 +862,111 @@ s32 spursAddWorkload(
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spurs->m.wklG1[wnum].wklPriority = *(be_t<u64>*)priorityTable;
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spurs->m.wklH1[wnum].nameClass = nameClass;
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spurs->m.wklH1[wnum].nameInstance = nameInstance;
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memset(spurs->m.wklF1[wnum].unk0, 0, 0x18);
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// (preserve semaphore id)
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memset(spurs->m.wklF1[wnum].unk0, 0, 0x18); // clear struct preserving semaphore id
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memset(spurs->m.wklF1[wnum].unk1, 0, 0x60);
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if (hook)
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{
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spurs->m.wklF1[wnum].hook = hook;
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spurs->m.wklF1[wnum].hookArg = hookArg;
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spurs->m.wklE1[wnum] |= 2;
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}
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spurs->m.wklY1[wnum] = 0;
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if (spurs->m.x70.read_relaxed().flags1 & 0x40)
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spurs->m.wklZ1[wnum] = 0;
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if ((spurs->m.x70.read_relaxed().flags1 & 0x40) == 0)
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{
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}
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else
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{
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spurs->m.wklZ1[wnum] = 0;
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spurs->m.wklMinCnt[wnum] = minContention > 8 ? 8 : 0;
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spurs->m.wklZ2[wnum] = 0;
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spurs->m.wklMinCnt[wnum] = minContention > 8 ? 8 : minContention;
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}
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}
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else
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{
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assert((spurs->m.wklA[index] & 0xf0) == 0);
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assert((spurs->m.wklB[index] & 0xf0) == 0);
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spurs->m.wklC2[index] = 1;
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spurs->m.wklD2[index] = 0;
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spurs->m.wklE2[index] = 0;
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spurs->m.wklG2[index].wklPm = pm;
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spurs->m.wklG2[index].wklArg = data;
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spurs->m.wklG2[index].wklSize = size;
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spurs->m.wklG2[index].wklPriority = *(be_t<u64>*)priorityTable;
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spurs->m.wklH2[index].nameClass = nameClass;
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spurs->m.wklH2[index].nameInstance = nameInstance;
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memset(spurs->m.wklF2[index].unk0, 0, 0x18); // clear struct preserving semaphore id
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memset(spurs->m.wklF2[index].unk1, 0, 0x60);
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if (hook)
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{
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spurs->m.wklF2[index].hook = hook;
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spurs->m.wklF2[index].hookArg = hookArg;
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spurs->m.wklE2[index] |= 2;
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}
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spurs->m.wklZ2[index] = 0;
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}
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u32 pos = ((~wnum * 8) | (wnum / 4)) & 0x1c;
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spurs->m.wklMaxCnt[index / 4].atomic_op([pos, maxContention](be_t<u32>& v)
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{
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v &= ~(0xf << pos);
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v |= (maxContention > 8 ? 8 : maxContention) << pos;
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});
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if (wnum <= 15)
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{
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spurs->m.x70._and_not({ be_t<u16>::make(0x8000 >> index) }); // clear bit in wklFlag1
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}
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else
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{
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spurs->m.x78._and_not({ be_t<u16>::make(0x8000 >> index) }); // clear bit in wklFlag2
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}
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spurs->m.x70.atomic_op([wnum](CellSpurs::_sub_x70& x70)
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{
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if (x70.unk7 == wnum)
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{
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x70.unk7 = 0xff;
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}
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});
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u32 res_wkl;
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spurs->m.wklMsk2.atomic_op_sync([spurs, wnum, &res_wkl](be_t<u32>& v)
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{
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CellSpurs::_sub_str3& wkl = wnum <= 15 ? spurs->m.wklG1[wnum] : spurs->m.wklG2[wnum & 0xf];
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const u32 mask = v.ToLE() & ~(0x80000000 >> wnum);
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res_wkl = 0;
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for (u32 i = 0, m = 0x80000000, k = 0; i < 32; i++, m >>= 1)
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{
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if (mask & m)
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{
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CellSpurs::_sub_str3& current = i <= 15 ? spurs->m.wklG1[i] : spurs->m.wklG2[i & 0xf];
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if (current.wklPm.addr() == wkl.wklPm.addr())
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{
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// if a workload with identical policy module found
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res_wkl = current.wklCopy.read_relaxed();
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break;
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}
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else
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{
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k |= 0x80000000 >> current.wklCopy.read_relaxed();
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res_wkl = cntlz32(~k);
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}
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}
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}
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wkl.wklCopy.exchange((u8)res_wkl);
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});
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assert(res_wkl <= 31);
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if (wnum <= 15)
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{
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spurs->m.wklC1[wnum] = 2;
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}
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else
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{
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spurs->m.wklC2[index] = 2;
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}
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spurs->m.unk23[5].exchange(-1); // write 0xff byte at 0xbd
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spurs->m.x70._and_not({ {}, -1 }); // clear byte at 0x72
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return CELL_OK;
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}
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@ -177,7 +177,6 @@ struct CellSpurs
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u8 unk0[0x20];
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be_t<u64> sem; // 0x20
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u8 unk1[0x8];
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u32 pad;
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vm::bptr<CellSpursShutdownCompletionEventHook, 1, u64> hook; // 0x30
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vm::bptr<void, 1, u64> hookArg; // 0x38
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u8 unk2[0x40];
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@ -202,6 +201,7 @@ struct CellSpurs
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vm::bptr<const void, 1, u64> wklPm; // policy module
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be_t<u64> wklArg; // spu argument
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be_t<u32> wklSize;
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atomic_t<u8> wklCopy;
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be_t<u64> wklPriority;
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};
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@ -215,9 +215,8 @@ struct CellSpurs
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struct _sub_x70
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{
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u8 unk0;
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u8 unk1;
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u8 unk2;
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be_t<u16> wklFlag1; // 0x70
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u8 unk2; // 0x72
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u8 unk3;
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u8 flags1;
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u8 unk5;
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@ -227,7 +226,8 @@ struct CellSpurs
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struct _sub_x78
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{
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u64 unk;
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be_t<u16> wklFlag2;
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u8 unk[6];
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};
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union
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@ -239,22 +239,26 @@ struct CellSpurs
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// real data
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struct
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{
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u8 wklY1[0x10];
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u8 wklZ1[0x10]; // 0x10
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u8 wklA1[0x10]; // 0x20
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u8 wklB1[0x10]; // 0x30
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u8 wklZ1[0x10]; // 0x0
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u8 wklZ2[0x10]; // 0x10
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u8 wklA[0x10]; // 0x20
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u8 wklB[0x10]; // 0x30
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u8 wklMinCnt[0x10]; // 0x40
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u8 unknown0[0x6C - 0x50];
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atomic_t<u32> wklMaxCnt[4]; // 0x50
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u8 unknown0[0x6C - 0x60];
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be_t<u32> unk18; // 0x6C
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atomic_t<_sub_x70> x70; // 0x70
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atomic_t<_sub_x78> x78; // 0x78
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u8 wklC1[0x10]; // 0x80
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u8 wklD1[0x10]; // 0x90
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u8 wklE1[0x10]; // 0xA0
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atomic_t<u32> wklMask;// 0xB0
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u8 unknown2[0xC0 - 0xB4];
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atomic_t<u32> wklMsk1;// 0xB0
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atomic_t<u32> wklMsk2;// 0xB4
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atomic_t<u8> unk23[8];// 0xB8
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u8 unk6[0x10]; // 0xC0 (SPU port at 0xc9)
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u8 unknown1[0x100 - 0x0D0];
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u8 wklC2[0x10]; // 0xD0
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u8 wklD2[0x10]; // 0xE0
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u8 wklE2[0x10]; // 0xF0
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_sub_str1 wklF1[0x10];// 0x100
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be_t<u64> unk22; // 0x900
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u8 unknown7[0x980 - 0x908];
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@ -294,9 +298,10 @@ struct CellSpurs
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u8 unknown9[0xE00 - 0xDD0];
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_sub_str4 wklH1[0x10];// 0xE00
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_sub_str2 sub3; // 0xF00
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u8 unknown6[0x1200 - 0xF80];
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u8 unknown6[0x1000 - 0xF80];
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_sub_str3 wklG2[0x10];// 0x1000
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_sub_str1 wklF2[0x10];// 0x1200
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// ...
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_sub_str4 wklH2[0x10];// 0x1A00
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} m;
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// alternative implementation
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@ -112,8 +112,7 @@ s32 cellSyncMutexUnlock(vm::ptr<CellSyncMutex> mutex)
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return CELL_SYNC_ERROR_ALIGN;
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}
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mutex->data.read_sync();
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mutex->data.atomic_op([](CellSyncMutex::data_t& mutex)
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mutex->data.atomic_op_sync([](CellSyncMutex::data_t& mutex)
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{
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mutex.m_rel++;
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});
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@ -178,8 +177,7 @@ s32 cellSyncBarrierNotify(vm::ptr<CellSyncBarrier> barrier)
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return CELL_SYNC_ERROR_ALIGN;
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}
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barrier->data.read_sync();
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while (barrier->data.atomic_op(CELL_OK, syncBarrierTryNotifyOp))
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while (barrier->data.atomic_op_sync(CELL_OK, syncBarrierTryNotifyOp))
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{
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std::this_thread::sleep_for(std::chrono::milliseconds(1)); // hack
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if (Emu.IsStopped())
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@ -204,8 +202,7 @@ s32 cellSyncBarrierTryNotify(vm::ptr<CellSyncBarrier> barrier)
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return CELL_SYNC_ERROR_ALIGN;
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}
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barrier->data.read_sync();
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return barrier->data.atomic_op(CELL_OK, syncBarrierTryNotifyOp);
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return barrier->data.atomic_op_sync(CELL_OK, syncBarrierTryNotifyOp);
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}
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s32 syncBarrierTryWaitOp(CellSyncBarrier::data_t& barrier)
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@ -239,8 +236,7 @@ s32 cellSyncBarrierWait(vm::ptr<CellSyncBarrier> barrier)
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return CELL_SYNC_ERROR_ALIGN;
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}
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barrier->data.read_sync();
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while (barrier->data.atomic_op(CELL_OK, syncBarrierTryWaitOp))
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while (barrier->data.atomic_op_sync(CELL_OK, syncBarrierTryWaitOp))
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{
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std::this_thread::sleep_for(std::chrono::milliseconds(1)); // hack
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if (Emu.IsStopped())
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@ -265,8 +261,7 @@ s32 cellSyncBarrierTryWait(vm::ptr<CellSyncBarrier> barrier)
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return CELL_SYNC_ERROR_ALIGN;
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}
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barrier->data.read_sync();
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return barrier->data.atomic_op(CELL_OK, syncBarrierTryWaitOp);
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return barrier->data.atomic_op_sync(CELL_OK, syncBarrierTryWaitOp);
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}
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s32 syncRwmInitialize(vm::ptr<CellSyncRwm> rwm, vm::ptr<void> buffer, u32 buffer_size)
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