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rsx: Fixup for byte order when passing data via vertex registers that are not inline arrays (register vertex data and push buffers)
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35a380676e
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c3415bcff2
@ -255,16 +255,28 @@ namespace rsx
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template<u32 id, u32 index, int count, int register_count, typename type>
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template<u32 id, u32 index, int count, int register_count, typename type>
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void set_vertex_data_impl(thread* rsx, u32 arg)
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void set_vertex_data_impl(thread* rsx, u32 arg)
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{
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{
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static const usz increment_per_array_index = (register_count * sizeof(type)) / sizeof(u32);
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static constexpr usz increment_per_array_index = (register_count * sizeof(type)) / sizeof(u32);
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static const usz attribute_index = index / increment_per_array_index;
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static constexpr usz attribute_index = index / increment_per_array_index;
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static const usz vertex_subreg = index % increment_per_array_index;
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static constexpr usz vertex_subreg = index % increment_per_array_index;
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const auto vtype = vertex_data_type_from_element_type<type>::type;
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constexpr auto vtype = vertex_data_type_from_element_type<type>::type;
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ensure(vtype != rsx::vertex_base_type::cmp);
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static_assert(vtype != rsx::vertex_base_type::cmp);
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static_assert(vtype != rsx::vertex_base_type::ub256);
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// Get BE data
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// Convert LE data to BE layout
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arg = std::bit_cast<u32, be_t<u32>>(arg);
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if constexpr (sizeof(type) == 4)
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{
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arg = std::bit_cast<u32, be_t<u32>>(arg);
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}
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else if constexpr (sizeof(type) == 2)
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{
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// 2 16-bit values packed in 1 32-bit word
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const auto be_data = std::bit_cast<u32, be_t<u32>>(arg);
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// After u32 swap, the components are in the wrong position
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arg = (be_data << 16) | (be_data >> 16);
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}
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if (rsx->in_begin_end)
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if (rsx->in_begin_end)
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{
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{
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