rsx: Fixup for byte order when passing data via vertex registers that are not inline arrays (register vertex data and push buffers)

This commit is contained in:
kd-11 2021-06-14 21:38:44 +03:00 committed by kd-11
parent 35a380676e
commit c3415bcff2

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@ -255,16 +255,28 @@ namespace rsx
template<u32 id, u32 index, int count, int register_count, typename type>
void set_vertex_data_impl(thread* rsx, u32 arg)
{
static const usz increment_per_array_index = (register_count * sizeof(type)) / sizeof(u32);
static constexpr usz increment_per_array_index = (register_count * sizeof(type)) / sizeof(u32);
static const usz attribute_index = index / increment_per_array_index;
static const usz vertex_subreg = index % increment_per_array_index;
static constexpr usz attribute_index = index / increment_per_array_index;
static constexpr usz vertex_subreg = index % increment_per_array_index;
const auto vtype = vertex_data_type_from_element_type<type>::type;
ensure(vtype != rsx::vertex_base_type::cmp);
constexpr auto vtype = vertex_data_type_from_element_type<type>::type;
static_assert(vtype != rsx::vertex_base_type::cmp);
static_assert(vtype != rsx::vertex_base_type::ub256);
// Get BE data
arg = std::bit_cast<u32, be_t<u32>>(arg);
// Convert LE data to BE layout
if constexpr (sizeof(type) == 4)
{
arg = std::bit_cast<u32, be_t<u32>>(arg);
}
else if constexpr (sizeof(type) == 2)
{
// 2 16-bit values packed in 1 32-bit word
const auto be_data = std::bit_cast<u32, be_t<u32>>(arg);
// After u32 swap, the components are in the wrong position
arg = (be_data << 16) | (be_data >> 16);
}
if (rsx->in_begin_end)
{