diff --git a/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp b/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp
index 0ac68ce4f9..cae580801d 100644
--- a/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp
+++ b/rpcs3/Emu/Cell/SPUASMJITRecompiler.cpp
@@ -2369,6 +2369,7 @@ void spu_recompiler::WRCH(spu_opcode_t op)
 	case SPU_WrSRR0:
 	{
 		c->mov(*addr, SPU_OFF_32(gpr, op.rt, &v128::_u32, 3));
+		c->and_(*addr, 0x3fffc);
 		c->mov(SPU_OFF_32(srr0), *addr);
 		return;
 	}
@@ -2712,7 +2713,6 @@ void spu_recompiler::BISL(spu_opcode_t op)
 void spu_recompiler::IRET(spu_opcode_t op)
 {
 	c->mov(*addr, SPU_OFF_32(srr0));
-	c->and_(*addr, 0x3fffc);
 	branch_indirect(op);
 	m_pos = -1;
 }
diff --git a/rpcs3/Emu/Cell/SPUInterpreter.cpp b/rpcs3/Emu/Cell/SPUInterpreter.cpp
index 65f7a34138..d3d8f538b7 100644
--- a/rpcs3/Emu/Cell/SPUInterpreter.cpp
+++ b/rpcs3/Emu/Cell/SPUInterpreter.cpp
@@ -508,7 +508,7 @@ bool spu_interpreter::BISL(spu_thread& spu, spu_opcode_t op)
 
 bool spu_interpreter::IRET(spu_thread& spu, spu_opcode_t op)
 {
-	spu.pc = spu_branch_target(spu.srr0);
+	spu.pc = spu.srr0;
 	set_interrupt_status(spu, op);
 	return false;
 }
diff --git a/rpcs3/Emu/Cell/SPURecompiler.cpp b/rpcs3/Emu/Cell/SPURecompiler.cpp
index aac42d8ebc..f633dc38be 100644
--- a/rpcs3/Emu/Cell/SPURecompiler.cpp
+++ b/rpcs3/Emu/Cell/SPURecompiler.cpp
@@ -5606,7 +5606,7 @@ public:
 		{
 		case SPU_WrSRR0:
 		{
-			m_ir->CreateStore(val.value, spu_ptr<u32>(&spu_thread::srr0));
+			m_ir->CreateStore(eval(val & 0x3fffc).value, spu_ptr<u32>(&spu_thread::srr0));
 			return;
 		}
 		case SPU_WrOutIntrMbox:
diff --git a/rpcs3/Emu/Cell/SPUThread.cpp b/rpcs3/Emu/Cell/SPUThread.cpp
index e3d430dea3..de3a01261d 100644
--- a/rpcs3/Emu/Cell/SPUThread.cpp
+++ b/rpcs3/Emu/Cell/SPUThread.cpp
@@ -2436,7 +2436,7 @@ bool spu_thread::set_ch_value(u32 ch, u32 value)
 	{
 	case SPU_WrSRR0:
 	{
-		srr0 = value;
+		srr0 = value & 0x3fffc;
 		return true;
 	}