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Add missing TD instruction.

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Unknown W. Brackets 2014-05-07 23:28:34 -07:00
parent d54237b0a3
commit a5c18b2a09
4 changed files with 11 additions and 0 deletions
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4
rpcs3/Emu/Cell/PPUDisAsm.h
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@ -1320,6 +1320,10 @@ private:
{
DisAsm_R3_RC("andc", ra, rs, rb, rc);
}
void TD(u32 to, u32 ra, u32 rb)
{
DisAsm_INT1_R2("td", to, ra, rb);
}
void LVEWX(u32 vd, u32 ra, u32 rb)
{
DisAsm_V1_R2("lvewx", vd, ra, rb);

1
rpcs3/Emu/Cell/PPUInstrTable.h
View File

@ -470,6 +470,7 @@ namespace PPU_instr
/*0x037*/bind_instr(g1f_list, LWZUX, RD, RA, RB);
/*0x03a*/bind_instr(g1f_list, CNTLZD, RA, RS, RC);
/*0x03c*/bind_instr(g1f_list, ANDC, RA, RS, RB, RC);
/*0x03c*/bind_instr(g1f_list, TD, TO, RA, RB);
/*0x047*/bind_instr(g1f_list, LVEWX, VD, RA, RB);
/*0x049*/bind_instr(g1f_list, MULHD, RD, RA, RB, RC);
/*0x04b*/bind_instr(g1f_list, MULHW, RD, RA, RB, RC);

4
rpcs3/Emu/Cell/PPUInterpreter.h
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@ -2518,6 +2518,10 @@ private:
CPU.GPR[ra] = CPU.GPR[rs] & ~CPU.GPR[rb];
if(rc) CPU.UpdateCR0<s64>(CPU.GPR[ra]);
}
void TD(u32 to, u32 ra, u32 rb)
{
UNK("td");
}
void LVEWX(u32 vd, u32 ra, u32 rb)
{
//const u64 addr = (ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]) & ~3ULL;

2
rpcs3/Emu/Cell/PPUOpcodes.h
View File

@ -280,6 +280,7 @@ namespace PPU_opcodes
LWZUX = 0x037,
CNTLZD = 0x03a,
ANDC = 0x03c,
TD = 0x044,
LVEWX = 0x047, //Load Vector Element Word Indexed
MULHD = 0x049,
MULHW = 0x04b,
@ -676,6 +677,7 @@ public:
virtual void LWZUX(u32 rd, u32 ra, u32 rb) = 0;
virtual void CNTLZD(u32 ra, u32 rs, bool rc) = 0;
virtual void ANDC(u32 ra, u32 rs, u32 rb, bool rc) = 0;
virtual void TD(u32 to, u32 ra, u32 rb) = 0;
virtual void LVEWX(u32 vd, u32 ra, u32 rb) = 0;
virtual void MULHD(u32 rd, u32 ra, u32 rb, bool rc) = 0;
virtual void MULHW(u32 rd, u32 ra, u32 rb, bool rc) = 0;