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PPU: Use SEQ-CST memory barrier in reservation load

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Eladash 2020-09-14 08:08:26 +03:00 committed by Megamouse
parent 8df1d74395
commit a52a16807f
1 changed files with 3 additions and 0 deletions
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3
rpcs3/Emu/Cell/PPUThread.cpp
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@ -1076,6 +1076,9 @@ static void ppu_trace(u64 addr)
template <typename T>
static T ppu_load_acquire_reservation(ppu_thread& ppu, u32 addr)
{
// Do not allow stores accessed from the same cache line to past reservation load
std::atomic_thread_fence(std::memory_order_seq_cst);
if (addr % sizeof(T))
{
fmt::throw_exception("PPU %s: Unaligned address: 0x%08x" HERE, sizeof(T) == 4 ? "LWARX" : "LDARX", addr);