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Merge pull request #264 from unknownbrackets/ppu-minor
Clean up LR updates in branches, remove CA update in ADD
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commit
a186efded2
@ -2084,9 +2084,10 @@ private:
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{
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if (CheckCondition(bo, bi))
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{
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const u64 nextLR = CPU.PC + 4;
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CPU.SetBranch(branchTarget((aa ? 0 : CPU.PC), bd), lk);
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if(lk) CPU.LR = nextLR;
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}
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if(lk) CPU.LR = CPU.PC + 4;
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}
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void SC(u32 sc_code)
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{
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@ -2108,8 +2109,9 @@ private:
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}
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void B(s32 ll, u32 aa, u32 lk)
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{
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const u64 nextLR = CPU.PC + 4;
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CPU.SetBranch(branchTarget(aa ? 0 : CPU.PC, ll), lk);
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if(lk) CPU.LR = CPU.PC + 4;
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if(lk) CPU.LR = nextLR;
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}
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void MCRF(u32 crfd, u32 crfs)
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{
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@ -2119,9 +2121,10 @@ private:
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{
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if (CheckCondition(bo, bi))
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{
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const u64 nextLR = CPU.PC + 4;
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CPU.SetBranch(branchTarget(0, CPU.LR), true);
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if(lk) CPU.LR = nextLR;
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}
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if(lk) CPU.LR = CPU.PC + 4;
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}
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void CRNOR(u32 crbd, u32 crba, u32 crbb)
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{
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@ -2171,9 +2174,10 @@ private:
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{
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if(bo & 0x10 || CPU.IsCR(bi) == (bo & 0x8))
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{
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const u64 nextLR = CPU.PC + 4;
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CPU.SetBranch(branchTarget(0, CPU.CTR), true);
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if(lk) CPU.LR = nextLR;
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}
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if(lk) CPU.LR = CPU.PC + 4;
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}
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void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc)
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{
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@ -2816,7 +2820,6 @@ private:
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const u64 RA = CPU.GPR[ra];
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const u64 RB = CPU.GPR[rb];
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CPU.GPR[rd] = RA + RB;
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CPU.XER.CA = CPU.IsCarry(RA, RB);
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if(oe) UNK("addo");
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if(rc) CPU.UpdateCR0<s64>(CPU.GPR[rd]);
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}
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