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rsx: Validate stencil op to match realhw behavior
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@ -728,6 +728,31 @@ namespace rsx
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}
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}
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void set_stencil_op(thread* rsx, u32 reg, u32 arg)
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{
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if (arg != method_registers.register_previous_value)
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{
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switch (arg)
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{
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case CELL_GCM_INVERT:
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case CELL_GCM_KEEP:
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case CELL_GCM_REPLACE:
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case CELL_GCM_INCR:
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case CELL_GCM_DECR:
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case CELL_GCM_INCR_WRAP:
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case CELL_GCM_DECR_WRAP:
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case CELL_GCM_ZERO:
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set_surface_options_dirty_bit(rsx, reg, arg);
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break;
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default:
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// Ignored on RSX
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method_registers.decode(reg, method_registers.register_previous_value);
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break;
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}
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}
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}
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template <u32 RsxFlags>
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void notify_state_changed(thread* rsx, u32, u32 arg)
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{
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@ -3097,13 +3122,13 @@ namespace rsx
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bind<NV4097_SET_TWO_SIDED_STENCIL_TEST_ENABLE, nv4097::set_surface_options_dirty_bit>();
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bind<NV4097_SET_STENCIL_TEST_ENABLE, nv4097::set_surface_options_dirty_bit>();
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bind<NV4097_SET_STENCIL_MASK, nv4097::set_surface_options_dirty_bit>();
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bind<NV4097_SET_STENCIL_OP_ZPASS, nv4097::set_surface_options_dirty_bit>();
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bind<NV4097_SET_STENCIL_OP_FAIL, nv4097::set_surface_options_dirty_bit>();
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bind<NV4097_SET_STENCIL_OP_ZFAIL, nv4097::set_surface_options_dirty_bit>();
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bind<NV4097_SET_STENCIL_OP_ZPASS, nv4097::set_stencil_op>();
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bind<NV4097_SET_STENCIL_OP_FAIL, nv4097::set_stencil_op>();
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bind<NV4097_SET_STENCIL_OP_ZFAIL, nv4097::set_stencil_op>();
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bind<NV4097_SET_BACK_STENCIL_MASK, nv4097::set_surface_options_dirty_bit>();
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bind<NV4097_SET_BACK_STENCIL_OP_ZPASS, nv4097::set_surface_options_dirty_bit>();
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bind<NV4097_SET_BACK_STENCIL_OP_FAIL, nv4097::set_surface_options_dirty_bit>();
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bind<NV4097_SET_BACK_STENCIL_OP_ZFAIL, nv4097::set_surface_options_dirty_bit>();
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bind<NV4097_SET_BACK_STENCIL_OP_ZPASS, nv4097::set_stencil_op>();
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bind<NV4097_SET_BACK_STENCIL_OP_FAIL, nv4097::set_stencil_op>();
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bind<NV4097_SET_BACK_STENCIL_OP_ZFAIL, nv4097::set_stencil_op>();
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bind<NV4097_WAIT_FOR_IDLE, nv4097::sync>();
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bind<NV4097_INVALIDATE_L2, nv4097::set_shader_program_dirty>();
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bind<NV4097_SET_SHADER_PROGRAM, nv4097::set_shader_program_dirty>();
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