mirror of
https://github.com/RPCS3/rpcs3.git
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Merge pull request #968 from achurch/ppu-interpreter-fixes
Implement FPU rounding mode and exception checking in the PPU interpreter.
This commit is contained in:
B1ackDaemon
commit
9709f7f821
@ -17,6 +17,8 @@
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#define _rotl64(x,r) (((u64)(x) << (r)) | ((u64)(x) >> (64 - (r))))
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#endif
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#include <fenv.h>
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#if 0//def _DEBUG
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#define HLE_CALL_DEBUG
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#endif
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@ -60,6 +62,26 @@ static double SilenceNaN(double x)
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return (double&)bits;
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}
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static void SetHostRoundingMode(u32 rn)
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{
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switch (rn)
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{
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case FPSCR_RN_NEAR:
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fesetround(FE_TONEAREST);
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break;
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case FPSCR_RN_ZERO:
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fesetround(FE_TOWARDZERO);
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break;
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case FPSCR_RN_PINF:
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fesetround(FE_UPWARD);
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break;
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case FPSCR_RN_MINF:
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fesetround(FE_DOWNWARD);
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break;
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}
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}
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namespace ppu_recompiler_llvm {
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class Compiler;
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}
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@ -79,6 +101,13 @@ public:
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}
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private:
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void CheckHostFPExceptions()
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{
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CPU.SetFPSCR_FI(fetestexcept(FE_INEXACT) != 0);
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if (fetestexcept(FE_UNDERFLOW)) CPU.SetFPSCRException(FPSCR_UX);
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if (fetestexcept(FE_OVERFLOW)) CPU.SetFPSCRException(FPSCR_OX);
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}
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void Exit() {}
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void SysCall()
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@ -245,6 +274,7 @@ private:
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}
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void VADDFP(u32 vd, u32 va, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float a = CheckVSCR_NJ(CPU.VPR[va]._f[w]);
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@ -441,6 +471,7 @@ private:
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}
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void VCFSX(u32 vd, u32 uimm5, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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u32 scale = 1 << uimm5;
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for (uint w = 0; w < 4; w++)
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@ -450,6 +481,7 @@ private:
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}
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void VCFUX(u32 vd, u32 uimm5, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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u32 scale = 1 << uimm5;
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for (uint w = 0; w < 4; w++)
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@ -786,8 +818,8 @@ private:
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CPU.VPR[vd]._s32[w] = (int)0x80000000;
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CPU.VSCR.SAT = 1;
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}
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else // C rounding = Round towards 0
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CPU.VPR[vd]._s32[w] = (int)result;
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else
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CPU.VPR[vd]._s32[w] = (int)trunc(result);
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}
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}
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}
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@ -804,7 +836,6 @@ private:
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}
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else
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{
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// C rounding = Round towards 0
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double result = (double)b * nScale;
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if (result > 0xffffffffu)
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{
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@ -817,7 +848,7 @@ private:
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CPU.VSCR.SAT = 1;
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}
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else
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CPU.VPR[vd]._u32[w] = (u32)result;
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CPU.VPR[vd]._u32[w] = (u32)trunc(result);
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}
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}
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}
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@ -826,6 +857,7 @@ private:
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// vd = 2^x
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// ISA : Note that the value placed into the element of vD may vary between implementations
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// and between different executions on the same implementation.
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float b = CheckVSCR_NJ(CPU.VPR[vb]._f[w]);
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@ -839,6 +871,7 @@ private:
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{
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// ISA : Note that the value placed into the element of vD may vary between implementations
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// and between different executions on the same implementation.
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float b = CheckVSCR_NJ(CPU.VPR[vb]._f[w]);
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@ -850,6 +883,7 @@ private:
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}
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void VMADDFP(u32 vd, u32 va, u32 vc, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float a = CheckVSCR_NJ(CPU.VPR[va]._f[w]);
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@ -1275,6 +1309,7 @@ private:
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}
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void VNMSUBFP(u32 vd, u32 va, u32 vc, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float a = CheckVSCR_NJ(CPU.VPR[va]._f[w]);
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@ -1568,6 +1603,7 @@ private:
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}
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void VREFP(u32 vd, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float b = CheckVSCR_NJ(CPU.VPR[vb]._f[w]);
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@ -1596,7 +1632,10 @@ private:
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if (std::isnan(b))
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CPU.VPR[vd]._f[w] = SilenceNaN(b);
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else
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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CPU.VPR[vd]._f[w] = nearbyintf(CPU.VPR[vb]._f[w]);
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}
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}
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}
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void VRFIP(u32 vd, u32 vb)
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@ -1646,6 +1685,7 @@ private:
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}
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void VRSQRTEFP(u32 vd, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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//TODO: accurate div
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@ -1846,6 +1886,7 @@ private:
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}
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void VSUBFP(u32 vd, u32 va, u32 vb)
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{
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SetHostRoundingMode(FPSCR_RN_NEAR);
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for (uint w = 0; w < 4; w++)
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{
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const float a = CheckVSCR_NJ(CPU.VPR[va]._f[w]);
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@ -3663,6 +3704,7 @@ private:
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void FSQRTS(u32 frd, u32 frb, bool rc) {FSQRT(frd, frb, rc, true);}
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void FRES(u32 frd, u32 frb, bool rc)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double b = CPU.FPR[frb];
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if(FPRdouble::IsSNaN(b))
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{
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@ -3693,7 +3735,9 @@ private:
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}
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else
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{
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feclearexcept(FE_ALL_EXCEPT);
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CPU.FPR[frd] = static_cast<float>(1.0 / b);
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CheckHostFPExceptions();
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}
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CPU.FPSCR.FPRF = CPU.FPR[frd].GetType();
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if(rc) CPU.UpdateCR1();
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@ -3797,6 +3841,7 @@ private:
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}
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void FRSP(u32 frd, u32 frb, bool rc)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double b = CPU.FPR[frb];
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if (FPRdouble::IsSNaN(b))
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{
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@ -3814,6 +3859,7 @@ private:
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{
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if (((u64&)b0 & DOUBLE_EXP) < 0x3800000000000000ULL) (u64&)b0 &= DOUBLE_SIGN;
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}
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feclearexcept(FE_ALL_EXCEPT);
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const double r = static_cast<float>(b0);
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if (FPRdouble::IsNaN(r))
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{
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@ -3823,7 +3869,7 @@ private:
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else
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{
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CPU.FPSCR.FR = fabs(r) > fabs(b);
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CPU.SetFPSCR_FI(b != r);
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CheckHostFPExceptions();
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}
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u32 type = PPCdouble(r).GetType();
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if (type == FPR_PN && r < ldexp(1.0, -126)) type = FPR_PD;
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@ -3869,6 +3915,7 @@ private:
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switch(rn)
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{
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case FPSCR_RN_NEAR:
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SetHostRoundingMode(FPSCR_RN_NEAR);
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i = (s32)nearbyint(b);
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break;
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case FPSCR_RN_ZERO:
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@ -3902,6 +3949,7 @@ private:
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void FDIV(u32 frd, u32 fra, u32 frb, bool rc) {FDIV(frd, fra, frb, rc, false);}
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void FDIV(u32 frd, u32 fra, u32 frb, bool rc, bool single)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double a = CPU.FPR[fra];
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const double b = CPU.FPR[frb];
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if(FPRdouble::IsSNaN(a) || FPRdouble::IsSNaN(b))
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@ -3960,9 +4008,11 @@ private:
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return;
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}
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}
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feclearexcept(FE_ALL_EXCEPT);
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const double res = a / b;
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if(single) CPU.FPR[frd] = (float)res;
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else CPU.FPR[frd] = res;
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CheckHostFPExceptions();
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}
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CPU.FPSCR.FPRF = CPU.FPR[frd].GetType();
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@ -3971,6 +4021,7 @@ private:
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void FSUB(u32 frd, u32 fra, u32 frb, bool rc) {FSUB(frd, fra, frb, rc, false);}
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void FSUB(u32 frd, u32 fra, u32 frb, bool rc, bool single)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double a = CPU.FPR[fra];
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const double b = CPU.FPR[frb];
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if(FPRdouble::IsSNaN(a) || FPRdouble::IsSNaN(b))
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@ -4006,9 +4057,11 @@ private:
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}
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else
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{
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feclearexcept(FE_ALL_EXCEPT);
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const double res = a - b;
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if(single) CPU.FPR[frd] = (float)res;
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else CPU.FPR[frd] = res;
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CheckHostFPExceptions();
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}
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CPU.FPSCR.FPRF = CPU.FPR[frd].GetType();
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if(rc) CPU.UpdateCR1();
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@ -4016,6 +4069,7 @@ private:
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void FADD(u32 frd, u32 fra, u32 frb, bool rc) {FADD(frd, fra, frb, rc, false);}
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void FADD(u32 frd, u32 fra, u32 frb, bool rc, bool single)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double a = CPU.FPR[fra];
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const double b = CPU.FPR[frb];
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if(FPRdouble::IsSNaN(a) || FPRdouble::IsSNaN(b))
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@ -4051,9 +4105,11 @@ private:
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}
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else
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{
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feclearexcept(FE_ALL_EXCEPT);
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const double res = a + b;
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if(single) CPU.FPR[frd] = (float)res;
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else CPU.FPR[frd] = res;
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CheckHostFPExceptions();
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}
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CPU.FPSCR.FPRF = CPU.FPR[frd].GetType();
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if(rc) CPU.UpdateCR1();
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@ -4061,6 +4117,7 @@ private:
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void FSQRT(u32 frd, u32 frb, bool rc) {FSQRT(frd, frb, rc, false);}
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void FSQRT(u32 frd, u32 frb, bool rc, bool single)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double b = CPU.FPR[frb];
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if(FPRdouble::IsSNaN(b))
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{
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@ -4091,9 +4148,11 @@ private:
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}
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else
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{
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feclearexcept(FE_ALL_EXCEPT);
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const double res = sqrt(b);
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if(single) CPU.FPR[frd] = (float)res;
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else CPU.FPR[frd] = res;
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CheckHostFPExceptions();
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}
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CPU.FPSCR.FPRF = CPU.FPR[frd].GetType();
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if(rc) CPU.UpdateCR1();
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@ -4106,6 +4165,7 @@ private:
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void FMUL(u32 frd, u32 fra, u32 frc, bool rc) {FMUL(frd, fra, frc, rc, false);}
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void FMUL(u32 frd, u32 fra, u32 frc, bool rc, bool single)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double a = CPU.FPR[fra];
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const double c = CPU.FPR[frc];
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if(FPRdouble::IsSNaN(a) || FPRdouble::IsSNaN(c))
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@ -4141,15 +4201,18 @@ private:
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}
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else
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{
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feclearexcept(FE_ALL_EXCEPT);
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const double res = a * c;
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if(single) CPU.FPR[frd] = (float)res;
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else CPU.FPR[frd] = res;
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CheckHostFPExceptions();
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}
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CPU.FPSCR.FPRF = CPU.FPR[frd].GetType();
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if(rc) CPU.UpdateCR1();
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}
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void FRSQRTE(u32 frd, u32 frb, bool rc)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double b = CPU.FPR[frb];
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if(FPRdouble::IsSNaN(b))
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{
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@ -4192,7 +4255,9 @@ private:
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}
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else
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{
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feclearexcept(FE_ALL_EXCEPT);
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CPU.FPR[frd] = 1.0 / sqrt(b);
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CheckHostFPExceptions();
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}
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CPU.FPSCR.FPRF = CPU.FPR[frd].GetType();
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if(rc) CPU.UpdateCR1();
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@ -4201,6 +4266,7 @@ private:
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void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc) {FMADD(frd, fra, frc, frb, rc, false, false, false);}
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void FMADD(u32 frd, u32 fra, u32 frc, u32 frb, bool rc, bool neg, bool sub, bool single)
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{
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SetHostRoundingMode(CPU.FPSCR.RN);
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const double a = CPU.FPR[fra];
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const double b = CPU.FPR[frb];
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const double c = CPU.FPR[frc];
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@ -4256,8 +4322,10 @@ private:
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}
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else
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{
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feclearexcept(FE_ALL_EXCEPT);
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if(single) CPU.FPR[frd] = (float)(neg ? -res : res);
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else CPU.FPR[frd] = (neg ? -res : res);
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CheckHostFPExceptions();
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}
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}
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CPU.FPSCR.FPRF = CPU.FPR[frd].GetType();
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@ -4344,6 +4412,7 @@ private:
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switch(rn)
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{
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case FPSCR_RN_NEAR:
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SetHostRoundingMode(FPSCR_RN_NEAR);
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i = (s64)nearbyint(b);
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break;
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case FPSCR_RN_ZERO:
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