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This commit is contained in:
Nekotekina 2014-01-23 22:40:49 +04:00
parent 6fb1a67a83
commit 93faac5780
6 changed files with 64 additions and 35 deletions
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75
rpcs3/Emu/Cell/PPUInterpreter.h
View File

@ -762,15 +762,14 @@ private:
int nScale = 1 << uimm5; int nScale = 1 << uimm5;
for (uint w = 0; w < 4; w++) for (uint w = 0; w < 4; w++)
{ {
// C rounding = Round towards 0 float result = CPU.VPR[vb]._f[w] * nScale;
s64 result = (s64)(CPU.VPR[vb]._f[w] * nScale);
if (result > INT_MAX) if (result > INT_MAX)
CPU.VPR[vd]._s32[w] = (int)INT_MAX; CPU.VPR[vd]._s32[w] = (int)INT_MAX;
else if (result < INT_MIN) else if (result < INT_MIN)
CPU.VPR[vd]._s32[w] = (int)INT_MIN; CPU.VPR[vd]._s32[w] = (int)INT_MIN;
else else // C rounding = Round towards 0
CPU.VPR[vd]._s32[w] = (int)result; CPU.VPR[vd]._s32[w] = (int)result;
} }
} }
@ -1580,7 +1579,7 @@ private:
{ {
for (uint w = 0; w < 4; w++) for (uint w = 0; w < 4; w++)
{ {
CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] << (CPU.VPR[vb]._u8[w*4] & 0x1f); CPU.VPR[vd]._u32[w] = CPU.VPR[va]._u32[w] << (CPU.VPR[vb]._u32[w] & 0x1f);
} }
} }
void VSPLTB(u32 vd, u32 uimm5, u32 vb) void VSPLTB(u32 vd, u32 uimm5, u32 vb)
@ -2033,9 +2032,10 @@ private:
} }
void SUBFIC(u32 rd, u32 ra, s32 simm16) void SUBFIC(u32 rd, u32 ra, s32 simm16)
{ {
s64 RA = CPU.GPR[ra]; const u64 RA = CPU.GPR[ra];
CPU.GPR[rd] = (s64)simm16 - RA; const u64 IMM = (u64)(s64)simm16;
CPU.XER.CA = RA <= simm16; CPU.GPR[rd] = IMM - RA;
CPU.XER.CA = RA > IMM;
} }
void CMPLI(u32 crfd, u32 l, u32 ra, u32 uimm16) void CMPLI(u32 crfd, u32 l, u32 ra, u32 uimm16)
{ {
@ -2068,8 +2068,10 @@ private:
} }
void BC(u32 bo, u32 bi, s32 bd, u32 aa, u32 lk) void BC(u32 bo, u32 bi, s32 bd, u32 aa, u32 lk)
{ {
if(!CheckCondition(bo, bi)) return; if (CheckCondition(bo, bi))
CPU.SetBranch(branchTarget((aa ? 0 : CPU.PC), bd), lk); {
CPU.SetBranch(branchTarget((aa ? 0 : CPU.PC), bd), lk);
}
if(lk) CPU.LR = CPU.PC + 4; if(lk) CPU.LR = CPU.PC + 4;
} }
void SC(s32 sc_code) void SC(s32 sc_code)
@ -2093,8 +2095,10 @@ private:
} }
void BCLR(u32 bo, u32 bi, u32 bh, u32 lk) void BCLR(u32 bo, u32 bi, u32 bh, u32 lk)
{ {
if(!CheckCondition(bo, bi)) return; if (CheckCondition(bo, bi))
CPU.SetBranch(branchTarget(0, CPU.LR), true); {
CPU.SetBranch(branchTarget(0, CPU.LR), true);
}
if(lk) CPU.LR = CPU.PC + 4; if(lk) CPU.LR = CPU.PC + 4;
} }
void CRNOR(u32 crbd, u32 crba, u32 crbb) void CRNOR(u32 crbd, u32 crba, u32 crbb)
@ -2146,8 +2150,8 @@ private:
if(bo & 0x10 || CPU.IsCR(bi) == (bo & 0x8)) if(bo & 0x10 || CPU.IsCR(bi) == (bo & 0x8))
{ {
CPU.SetBranch(branchTarget(0, CPU.CTR), true); CPU.SetBranch(branchTarget(0, CPU.CTR), true);
if(lk) CPU.LR = CPU.PC + 4;
} }
if(lk) CPU.LR = CPU.PC + 4;
} }
void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc) void RLWIMI(u32 ra, u32 rs, u32 sh, u32 mb, u32 me, bool rc)
{ {
@ -2452,6 +2456,7 @@ private:
void DCBST(u32 ra, u32 rb) void DCBST(u32 ra, u32 rb)
{ {
//UNK("dcbst", false); //UNK("dcbst", false);
_mm_mfence();
} }
void LWZUX(u32 rd, u32 ra, u32 rb) void LWZUX(u32 rd, u32 ra, u32 rb)
{ {
@ -2529,6 +2534,7 @@ private:
void DCBF(u32 ra, u32 rb) void DCBF(u32 ra, u32 rb)
{ {
//UNK("dcbf", false); //UNK("dcbf", false);
_mm_mfence();
} }
void LBZX(u32 rd, u32 ra, u32 rb) void LBZX(u32 rd, u32 ra, u32 rb)
{ {
@ -2574,10 +2580,26 @@ private:
} }
void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) void ADDE(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
{ {
const s64 RA = CPU.GPR[ra]; const u64 RA = CPU.GPR[ra];
const s64 RB = CPU.GPR[rb]; const u64 RB = CPU.GPR[rb];
CPU.GPR[rd] = RA + RB + CPU.XER.CA; if (CPU.XER.CA)
CPU.XER.CA = ((u64)RA + CPU.XER.CA > ~(u64)RB) | ((RA == -1) & CPU.XER.CA); {
if (RA == ~0ULL) //-1
{
CPU.GPR[rd] = RB;
CPU.XER.CA = 1;
}
else
{
CPU.GPR[rd] = RA + 1 + RB;
CPU.XER.CA = CPU.IsCarry(RA + 1, RB);
}
}
else
{
CPU.GPR[rd] = RA + RB;
CPU.XER.CA = CPU.IsCarry(RA, RB);
}
if(rc) CPU.UpdateCR0<s64>(CPU.GPR[rd]); if(rc) CPU.UpdateCR0<s64>(CPU.GPR[rd]);
if(oe) UNK("addeo"); if(oe) UNK("addeo");
} }
@ -2671,9 +2693,8 @@ private:
} }
void ADDZE(u32 rd, u32 ra, u32 oe, bool rc) void ADDZE(u32 rd, u32 ra, u32 oe, bool rc)
{ {
const s64 RA = CPU.GPR[ra]; const u64 RA = CPU.GPR[ra];
CPU.GPR[rd] = RA + CPU.XER.CA; CPU.GPR[rd] = RA + CPU.XER.CA;
CPU.XER.CA = CPU.IsCarry(RA, CPU.XER.CA); CPU.XER.CA = CPU.IsCarry(RA, CPU.XER.CA);
if(oe) ConLog.Warning("addzeo"); if(oe) ConLog.Warning("addzeo");
if(rc) CPU.UpdateCR0<s64>(CPU.GPR[rd]); if(rc) CPU.UpdateCR0<s64>(CPU.GPR[rd]);
@ -2709,7 +2730,7 @@ private:
} }
void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc) void MULLD(u32 rd, u32 ra, u32 rb, u32 oe, bool rc)
{ {
CPU.GPR[rd] = CPU.GPR[ra] * CPU.GPR[rb]; CPU.GPR[rd] = (s64)((s64)CPU.GPR[ra] * (s64)CPU.GPR[rb]);
if(rc) CPU.UpdateCR0<s64>(CPU.GPR[rd]); if(rc) CPU.UpdateCR0<s64>(CPU.GPR[rd]);
if(oe) UNK("mulldo"); if(oe) UNK("mulldo");
} }
@ -2731,6 +2752,7 @@ private:
void DCBTST(u32 th, u32 ra, u32 rb) void DCBTST(u32 th, u32 ra, u32 rb)
{ {
//UNK("dcbtst", false); //UNK("dcbtst", false);
_mm_mfence();
} }
void STBUX(u32 rs, u32 ra, u32 rb) void STBUX(u32 rs, u32 ra, u32 rb)
{ {
@ -2750,6 +2772,7 @@ private:
void DCBT(u32 ra, u32 rb, u32 th) void DCBT(u32 ra, u32 rb, u32 th)
{ {
//UNK("dcbt", false); //UNK("dcbt", false);
_mm_mfence();
} }
void LHZX(u32 rd, u32 ra, u32 rb) void LHZX(u32 rd, u32 ra, u32 rb)
{ {
@ -2786,6 +2809,7 @@ private:
} }
void DST(u32 ra, u32 rb, u32 strm, u32 t) void DST(u32 ra, u32 rb, u32 strm, u32 t)
{ {
_mm_mfence();
} }
void LHAX(u32 rd, u32 ra, u32 rb) void LHAX(u32 rd, u32 ra, u32 rb)
{ {
@ -2814,6 +2838,7 @@ private:
} }
void DSTST(u32 ra, u32 rb, u32 strm, u32 t) void DSTST(u32 ra, u32 rb, u32 strm, u32 t)
{ {
_mm_mfence();
} }
void LHAUX(u32 rd, u32 ra, u32 rb) void LHAUX(u32 rd, u32 ra, u32 rb)
{ {
@ -2823,8 +2848,7 @@ private:
} }
void STHX(u32 rs, u32 ra, u32 rb) void STHX(u32 rs, u32 ra, u32 rb)
{ {
const u64 addr = ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb]; Memory.Write16(ra ? CPU.GPR[ra] + CPU.GPR[rb] : CPU.GPR[rb], CPU.GPR[rs]);
Memory.Write16(addr, CPU.GPR[rs]);
} }
void ORC(u32 ra, u32 rs, u32 rb, bool rc) void ORC(u32 ra, u32 rs, u32 rb, bool rc)
{ {
@ -3056,12 +3080,13 @@ private:
} }
void DSS(u32 strm, u32 a) void DSS(u32 strm, u32 a)
{ {
_mm_mfence();
} }
void SRAWI(u32 ra, u32 rs, u32 sh, bool rc) void SRAWI(u32 ra, u32 rs, u32 sh, bool rc)
{ {
s32 RS = CPU.GPR[rs]; s32 RS = (u32)CPU.GPR[rs];
CPU.GPR[ra] = RS >> sh; CPU.GPR[ra] = RS >> sh;
CPU.XER.CA = (RS < 0) & ((CPU.GPR[ra] << sh) != RS); CPU.XER.CA = (RS < 0) & ((u32)(CPU.GPR[ra] << sh) != RS);
if(rc) CPU.UpdateCR0<s64>(CPU.GPR[ra]); if(rc) CPU.UpdateCR0<s64>(CPU.GPR[ra]);
} }
@ -3079,6 +3104,7 @@ private:
} }
void EIEIO() void EIEIO()
{ {
_mm_mfence();
} }
void STVLXL(u32 vs, u32 ra, u32 rb) void STVLXL(u32 vs, u32 ra, u32 rb)
{ {
@ -3121,6 +3147,7 @@ private:
void DCBZ(u32 ra, u32 rs) void DCBZ(u32 ra, u32 rs)
{ {
//UNK("dcbz", false); //UNK("dcbz", false);
_mm_mfence();
} }
void LWZ(u32 rd, u32 ra, s32 d) void LWZ(u32 rd, u32 ra, s32 d)
{ {

2
rpcs3/Emu/Cell/PPUThread.h
View File

@ -720,7 +720,7 @@ public:
const u8 IsCR(const u32 bit) const { return (GetCR(bit >> 2) & GetCRBit(bit)) ? 1 : 0; } const u8 IsCR(const u32 bit) const { return (GetCR(bit >> 2) & GetCRBit(bit)) ? 1 : 0; }
bool IsCarry(const u64 a, const u64 b) { return a > (~b); } bool IsCarry(const u64 a, const u64 b) { return a > (a + b); }
void SetFPSCRException(const FPSCR_EXP mask) void SetFPSCRException(const FPSCR_EXP mask)
{ {

4
rpcs3/Emu/Cell/SPUThread.h
View File

@ -516,11 +516,11 @@ public:
case MFC_PUT_CMD: case MFC_PUT_CMD:
case MFC_GET_CMD: case MFC_GET_CMD:
{ {
/* ConLog.Warning("DMA %s%s%s: lsa = 0x%x, ea = 0x%llx, tag = 0x%x, size = 0x%x, cmd = 0x%x", if (enable_log) ConLog.Write("DMA %s%s%s: lsa = 0x%x, ea = 0x%llx, tag = 0x%x, size = 0x%x, cmd = 0x%x",
op & MFC_PUT_CMD ? "PUT" : "GET", op & MFC_PUT_CMD ? "PUT" : "GET",
op & MFC_BARRIER_MASK ? "B" : "", op & MFC_BARRIER_MASK ? "B" : "",
op & MFC_FENCE_MASK ? "F" : "", op & MFC_FENCE_MASK ? "F" : "",
lsa, ea, tag, size, cmd); */ lsa, ea, tag, size, cmd);
MFCArgs.CMDStatus.SetValue(dmac.Cmd(cmd, tag, lsa, ea, size)); MFCArgs.CMDStatus.SetValue(dmac.Cmd(cmd, tag, lsa, ea, size));
} }
break; break;

6
rpcs3/Emu/GS/RSXThread.cpp
View File

@ -1452,8 +1452,10 @@ void RSXThread::Task()
{ {
wxCriticalSectionLocker lock(m_cs_main); wxCriticalSectionLocker lock(m_cs_main);
const u32 get = re(m_ctrl->get); u32 put, get;
const u32 put = re(m_ctrl->put); se_t<u32>::func(put, std::atomic_load((volatile std::atomic<u32>*)((u8*)m_ctrl + offsetof(CellGcmControl, put))));
se_t<u32>::func(get, std::atomic_load((volatile std::atomic<u32>*)((u8*)m_ctrl + offsetof(CellGcmControl, get))));
if(put == get || !Emu.IsRunning()) if(put == get || !Emu.IsRunning())
{ {
if(put == get) if(put == get)

10
rpcs3/Emu/SysCalls/Modules/cellDmux.h
View File

@ -100,8 +100,8 @@ struct CellDmuxResource2
{ {
struct struct
{ {
be_t<u32> spuThreadPriority; be_t<u32> noex_spuThreadPriority;
be_t<u32> numOfSpus; be_t<u32> noex_numOfSpus;
}; };
struct struct
{ {
@ -161,8 +161,8 @@ struct CellDmuxAuInfoEx
be_t<u32> auAddr; be_t<u32> auAddr;
be_t<u32> auSize; be_t<u32> auSize;
be_t<u32> reserved; be_t<u32> reserved;
bool isRap; bool isRap;
be_t<u64> userData; be_t<u64> userData;
CellCodecTimeStamp pts; CellCodecTimeStamp pts;
CellCodecTimeStamp dts; CellCodecTimeStamp dts;
}; };

2
rpcs3/Emu/SysCalls/Modules/cellSysutil.cpp
View File

@ -457,7 +457,7 @@ int cellVideoOutGetResolutionAvailability(u32 videoOut, u32 resolutionId, u32 as
int cellSysutilCheckCallback() int cellSysutilCheckCallback()
{ {
//cellSysutil.Warning("cellSysutilCheckCallback()"); cellSysutil.Warning("cellSysutilCheckCallback()");
Emu.GetCallbackManager().m_exit_callback.Check(); Emu.GetCallbackManager().m_exit_callback.Check();
return CELL_OK; return CELL_OK;