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PPU Precise/LLVM: Support NJ modes (#8617)
This commit is contained in:
Eladash
GitHub
parent
3354c800d7
commit
917069e31a
@ -359,6 +359,8 @@ public:
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}
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const g_ppu_scale_table;
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constexpr u32 ppu_inf_u32 = 0x7F800000u;
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static const f32 ppu_inf_f32 = std::bit_cast<f32>(ppu_inf_u32);
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constexpr u32 ppu_nan_u32 = 0x7FC00000u;
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static const f32 ppu_nan_f32 = std::bit_cast<f32>(ppu_nan_u32);
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static const v128 ppu_vec_nans = v128::from32p(ppu_nan_u32);
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@ -403,6 +405,14 @@ v128 vec_handle_nan(__m128 result, Args... args)
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return vec_handle_nan(v128::fromF(result), v128::fromF(args)...);
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}
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// Flush denormals to zero if NJ is 1
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inline v128 vec_handle_denormal(ppu_thread& ppu, v128 a)
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{
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const auto mask = v128::from32p(ppu.jm_mask);
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const auto nz = v128::fromV(_mm_srli_epi32(v128::eq32(mask & a, v128{}).vi, 1));
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return v128::andnot(nz, a);
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}
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bool ppu_interpreter::MFVSCR(ppu_thread& ppu, ppu_opcode_t op)
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{
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ppu.vr[op.vd] = v128::from32(0, 0, 0, u32{ppu.sat} | (u32{ppu.nj} << 16));
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@ -414,6 +424,7 @@ bool ppu_interpreter::MTVSCR(ppu_thread& ppu, ppu_opcode_t op)
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const u32 vscr = ppu.vr[op.vb]._u32[3];
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ppu.sat = (vscr & 1) != 0;
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ppu.nj = (vscr & 0x10000) != 0;
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ppu.jm_mask = ppu.nj ? ppu_inf_u32 : 0x7fff'ffff;
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return true;
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}
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@ -427,10 +438,10 @@ bool ppu_interpreter::VADDCUW(ppu_thread& ppu, ppu_opcode_t op)
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bool ppu_interpreter::VADDFP(ppu_thread& ppu, ppu_opcode_t op)
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{
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const auto a = ppu.vr[op.va];
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const auto b = ppu.vr[op.vb];
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const auto a = vec_handle_denormal(ppu, ppu.vr[op.va]);
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const auto b = vec_handle_denormal(ppu, ppu.vr[op.vb]);
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const auto result = v128::addfs(a, b);
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ppu.vr[op.vd] = vec_handle_nan(result, a, b);
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ppu.vr[op.vd] = vec_handle_denormal(ppu, vec_handle_nan(result, a, b));
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return true;
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}
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@ -958,26 +969,26 @@ bool ppu_interpreter::VLOGEFP(ppu_thread& ppu, ppu_opcode_t op)
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bool ppu_interpreter_fast::VMADDFP(ppu_thread& ppu, ppu_opcode_t op)
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{
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const auto a = ppu.vr[op.va].vf;
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const auto b = ppu.vr[op.vb].vf;
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const auto c = ppu.vr[op.vc].vf;
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const auto a = vec_handle_denormal(ppu, ppu.vr[op.va]).vf;
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const auto b = vec_handle_denormal(ppu, ppu.vr[op.vb]).vf;
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const auto c = vec_handle_denormal(ppu, ppu.vr[op.vc]).vf;
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const auto result = _mm_add_ps(_mm_mul_ps(a, c), b);
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ppu.vr[op.vd] = vec_handle_nan(result);
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ppu.vr[op.vd] = vec_handle_denormal(ppu, vec_handle_nan(result));
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return true;
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}
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bool ppu_interpreter_precise::VMADDFP(ppu_thread& ppu, ppu_opcode_t op)
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{
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const auto a = ppu.vr[op.va];
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const auto b = ppu.vr[op.vb];
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const auto c = ppu.vr[op.vc];
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ppu.vr[op.rd] = vec_handle_nan(v128::fma32f(a, c, b), a, b, c);
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const auto a = vec_handle_denormal(ppu, ppu.vr[op.va]);
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const auto b = vec_handle_denormal(ppu, ppu.vr[op.vb]);
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const auto c = vec_handle_denormal(ppu, ppu.vr[op.vc]);
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ppu.vr[op.rd] = vec_handle_denormal(ppu, vec_handle_nan(v128::fma32f(a, c, b), a, b, c));
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return true;
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}
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bool ppu_interpreter::VMAXFP(ppu_thread& ppu, ppu_opcode_t op)
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{
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ppu.vr[op.vd] = vec_handle_nan(_mm_max_ps(ppu.vr[op.va].vf, ppu.vr[op.vb].vf));
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ppu.vr[op.vd] = vec_handle_denormal(ppu, vec_handle_nan(_mm_max_ps(ppu.vr[op.va].vf, ppu.vr[op.vb].vf)));
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return true;
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}
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@ -1123,7 +1134,7 @@ bool ppu_interpreter::VMINFP(ppu_thread& ppu, ppu_opcode_t op)
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const auto a = ppu.vr[op.va].vf;
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const auto b = ppu.vr[op.vb].vf;
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const auto result = _mm_or_ps(_mm_min_ps(a, b), _mm_min_ps(b, a));
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ppu.vr[op.vd] = vec_handle_nan(result, a, b);
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ppu.vr[op.vd] = vec_handle_denormal(ppu, vec_handle_nan(result, a, b));
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return true;
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}
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@ -1463,18 +1474,18 @@ bool ppu_interpreter_fast::VNMSUBFP(ppu_thread& ppu, ppu_opcode_t op)
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const auto a = _mm_sub_ps(_mm_mul_ps(ppu.vr[op.va].vf, ppu.vr[op.vc].vf), ppu.vr[op.vb].vf);
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const auto b = _mm_set1_ps(-0.0f);
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const auto result = _mm_xor_ps(a, b);
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ppu.vr[op.vd] = vec_handle_nan(result, a, b);
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ppu.vr[op.vd] = vec_handle_nan(result);
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return true;
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}
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bool ppu_interpreter_precise::VNMSUBFP(ppu_thread& ppu, ppu_opcode_t op)
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{
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const auto m = _mm_set1_ps(-0.0f);
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const auto a = ppu.vr[op.va];
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const auto c = ppu.vr[op.vc];
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const auto a = vec_handle_denormal(ppu, ppu.vr[op.va]);
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const auto c = vec_handle_denormal(ppu, ppu.vr[op.vc]);
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const auto b = v128::fromF(_mm_xor_ps(ppu.vr[op.vb].vf, m));
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const auto r = v128::fromF(_mm_xor_ps(v128::fma32f(a, c, b).vf, m));
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ppu.vr[op.rd] = vec_handle_nan(r, a, b, c);
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ppu.vr[op.rd] = vec_handle_denormal(ppu, vec_handle_nan(r, a, b, c));
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return true;
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}
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@ -1874,15 +1885,15 @@ bool ppu_interpreter_precise::VPKUWUS(ppu_thread& ppu, ppu_opcode_t op)
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bool ppu_interpreter::VREFP(ppu_thread& ppu, ppu_opcode_t op)
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{
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const auto a = _mm_set_ps(1.0f, 1.0f, 1.0f, 1.0f);
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const auto b = ppu.vr[op.vb].vf;
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const auto b = vec_handle_denormal(ppu, ppu.vr[op.vb]).vf;
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const auto result = _mm_div_ps(a, b);
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ppu.vr[op.vd] = vec_handle_nan(result, a, b);
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ppu.vr[op.vd] = vec_handle_denormal(ppu, vec_handle_nan(result, a, b));
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return true;
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}
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bool ppu_interpreter::VRFIM(ppu_thread& ppu, ppu_opcode_t op)
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{
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const auto b = ppu.vr[op.vb];
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const auto b = vec_handle_denormal(ppu, ppu.vr[op.vb]);
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v128 d;
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for (uint w = 0; w < 4; w++)
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@ -1890,7 +1901,7 @@ bool ppu_interpreter::VRFIM(ppu_thread& ppu, ppu_opcode_t op)
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d._f[w] = std::floor(b._f[w]);
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}
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ppu.vr[op.vd] = vec_handle_nan(d, b);
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ppu.vr[op.vd] = vec_handle_denormal(ppu, vec_handle_nan(d, b));
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return true;
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}
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@ -1904,13 +1915,13 @@ bool ppu_interpreter::VRFIN(ppu_thread& ppu, ppu_opcode_t op)
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d._f[w] = std::nearbyint(b._f[w]);
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}
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ppu.vr[op.vd] = vec_handle_nan(d, b);
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ppu.vr[op.vd] = vec_handle_denormal(ppu, vec_handle_nan(d, b));
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return true;
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}
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bool ppu_interpreter::VRFIP(ppu_thread& ppu, ppu_opcode_t op)
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{
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const auto b = ppu.vr[op.vb];
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const auto b = vec_handle_denormal(ppu, ppu.vr[op.vb]);
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v128 d;
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for (uint w = 0; w < 4; w++)
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@ -1918,7 +1929,7 @@ bool ppu_interpreter::VRFIP(ppu_thread& ppu, ppu_opcode_t op)
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d._f[w] = std::ceil(b._f[w]);
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}
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ppu.vr[op.vd] = vec_handle_nan(d, b);
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ppu.vr[op.vd] = vec_handle_denormal(ppu, vec_handle_nan(d, b));
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return true;
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}
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@ -1932,7 +1943,7 @@ bool ppu_interpreter::VRFIZ(ppu_thread& ppu, ppu_opcode_t op)
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d._f[w] = std::truncf(b._f[w]);
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}
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ppu.vr[op.vd] = vec_handle_nan(d, b);
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ppu.vr[op.vd] = vec_handle_denormal(ppu, vec_handle_nan(d, b));
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return true;
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}
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@ -1978,9 +1989,9 @@ bool ppu_interpreter::VRLW(ppu_thread& ppu, ppu_opcode_t op)
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bool ppu_interpreter::VRSQRTEFP(ppu_thread& ppu, ppu_opcode_t op)
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{
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const auto a = _mm_set_ps(1.0f, 1.0f, 1.0f, 1.0f);
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const auto b = ppu.vr[op.vb].vf;
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const auto b = vec_handle_denormal(ppu, ppu.vr[op.vb]).vf;
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const auto result = _mm_div_ps(a, _mm_sqrt_ps(b));
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ppu.vr[op.vd] = vec_handle_nan(result, a, b);
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ppu.vr[op.vd] = vec_handle_denormal(ppu, vec_handle_nan(result, a, b));
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return true;
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}
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@ -2277,10 +2288,10 @@ bool ppu_interpreter::VSUBCUW(ppu_thread& ppu, ppu_opcode_t op)
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bool ppu_interpreter::VSUBFP(ppu_thread& ppu, ppu_opcode_t op)
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{
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const auto a = ppu.vr[op.va];
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const auto b = ppu.vr[op.vb];
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const auto a = vec_handle_denormal(ppu, ppu.vr[op.va]);
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const auto b = vec_handle_denormal(ppu, ppu.vr[op.vb]);
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const auto result = v128::subfs(a, b);
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ppu.vr[op.vd] = vec_handle_nan(result, a, b);
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ppu.vr[op.vd] = vec_handle_denormal(ppu, vec_handle_nan(result, a, b));
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return true;
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}
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@ -1613,6 +1613,7 @@ extern void ppu_initialize(const ppu_module& info)
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non_win32,
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accurate_fma,
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accurate_ppu_vector_nan,
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java_mode_handling,
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__bitset_enum_max
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};
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@ -1630,6 +1631,10 @@ extern void ppu_initialize(const ppu_module& info)
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{
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settings += ppu_settings::accurate_ppu_vector_nan;
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}
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if (g_cfg.core.llvm_ppu_jm_handling)
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{
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settings += ppu_settings::java_mode_handling;
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}
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// Write version, hash, CPU, settings
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fmt::append(obj_name, "v3-tane-%s-%s-%s.obj", fmt::base57(output, 16), fmt::base57(settings), jit_compiler::cpu(g_cfg.core.llvm_cpu));
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@ -186,7 +186,10 @@ public:
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exception, the corresponding element in the target vr is cleared to '0'. In both cases, the '0'
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has the same sign as the denormalized or underflowing value.
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*/
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bool nj = false;
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bool nj = true;
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// Optimization: precomputed java-mode mask for handling denormals
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u32 jm_mask = 0x7f80'0000;
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u32 raddr{0}; // Reservation addr
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u64 rtime{0};
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@ -46,6 +46,8 @@ PPUTranslator::PPUTranslator(LLVMContext& context, Module* _module, const ppu_mo
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thread_struct.insert(thread_struct.end(), 3, GetType<bool>()); // so, ov, ca
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thread_struct.insert(thread_struct.end(), 1, GetType<u8>()); // cnt
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thread_struct.insert(thread_struct.end(), 2, GetType<bool>()); // sat, nj
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thread_struct.emplace_back(ArrayType::get(GetType<char>(), 2)); // Padding
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thread_struct.insert(thread_struct.end(), 1, GetType<u32>()); // jm_mask
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m_thread_type = StructType::create(m_context, thread_struct, "context_t");
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@ -231,6 +233,25 @@ Value* PPUTranslator::VecHandleNan(Value* val)
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return val;
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}
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Value* PPUTranslator::VecHandleDenormal(Value* val)
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{
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const auto type = val->getType();
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const auto value = type == GetType<u32[4]>() ? val : m_ir->CreateBitCast(val, GetType<u32[4]>());
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const auto mask = SExt(m_ir->CreateICmpEQ(m_ir->CreateAnd(value, Broadcast(RegLoad(m_jm_mask), 4)), ConstantVector::getSplat(4, m_ir->getInt32(0))), GetType<s32[4]>());
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const auto nz = m_ir->CreateLShr(mask, 1);
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const auto result = m_ir->CreateAnd(m_ir->CreateNot(nz), value);
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return type == GetType<u32[4]>() ? result : m_ir->CreateBitCast(result, type);
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}
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Value* PPUTranslator::VecHandleResult(Value* val)
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{
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val = g_cfg.core.llvm_ppu_accurate_vector_nan ? VecHandleNan(val) : val;
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val = g_cfg.core.llvm_ppu_jm_handling ? VecHandleDenormal(val) : val;
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return val;
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}
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Value* PPUTranslator::GetAddr(u64 _add)
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{
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if (m_reloc)
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@ -609,7 +630,9 @@ void PPUTranslator::MFVSCR(ppu_opcode_t op)
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void PPUTranslator::MTVSCR(ppu_opcode_t op)
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{
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const auto vscr = m_ir->CreateExtractElement(GetVr(op.vb, VrType::vi32), m_ir->getInt32(m_is_be ? 3 : 0));
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RegStore(Trunc(m_ir->CreateLShr(vscr, 16), GetType<bool>()), m_nj);
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const auto nj = Trunc(m_ir->CreateLShr(vscr, 16), GetType<bool>());
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RegStore(nj, m_nj);
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if (g_cfg.core.llvm_ppu_jm_handling) RegStore(m_ir->CreateSelect(nj, m_ir->getInt32(0x7f80'0000), m_ir->getInt32(0x7fff'ffff)), m_jm_mask);
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RegStore(Trunc(vscr, GetType<bool>()), m_sat);
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}
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@ -625,7 +648,7 @@ void PPUTranslator::VADDFP(ppu_opcode_t op)
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const auto a = get_vr<f32[4]>(op.va);
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const auto b = get_vr<f32[4]>(op.vb);
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set_vr(op.vd, vec_handle_nan(a + b));
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set_vr(op.vd, vec_handle_result(a + b));
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}
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void PPUTranslator::VADDSBS(ppu_opcode_t op)
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@ -930,7 +953,7 @@ void PPUTranslator::VMADDFP(ppu_opcode_t op)
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if (data == v128{})
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{
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set_vr(op.vd, vec_handle_nan(a * c));
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set_vr(op.vd, vec_handle_result(a * c));
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ppu_log.notice("LLVM: VMADDFP with 0 addend at [0x%08x]", m_addr + (m_reloc ? m_reloc->addr : 0));
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return;
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}
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@ -938,7 +961,7 @@ void PPUTranslator::VMADDFP(ppu_opcode_t op)
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if (m_use_fma)
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{
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SetVr(op.vd, VecHandleNan(m_ir->CreateCall(get_intrinsic<f32[4]>(llvm::Intrinsic::fma), { a.value, c.value, b.value })));
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SetVr(op.vd, VecHandleResult(m_ir->CreateCall(get_intrinsic<f32[4]>(llvm::Intrinsic::fma), { a.value, c.value, b.value })));
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return;
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}
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@ -948,13 +971,13 @@ void PPUTranslator::VMADDFP(ppu_opcode_t op)
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const auto xc = m_ir->CreateFPExt(c.value, get_type<f64[4]>());
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const auto xr = m_ir->CreateCall(get_intrinsic<f64[4]>(llvm::Intrinsic::fmuladd), {xa, xc, xb});
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SetVr(op.vd, VecHandleNan(m_ir->CreateFPTrunc(xr, get_type<f32[4]>())));
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SetVr(op.vd, VecHandleResult(m_ir->CreateFPTrunc(xr, get_type<f32[4]>())));
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}
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void PPUTranslator::VMAXFP(ppu_opcode_t op)
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{
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const auto ab = GetVrs(VrType::vf, op.va, op.vb);
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SetVr(op.vd, VecHandleNan(m_ir->CreateSelect(m_ir->CreateFCmpOGT(ab[0], ab[1]), ab[0], ab[1])));
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SetVr(op.vd, VecHandleResult(m_ir->CreateSelect(m_ir->CreateFCmpOGT(ab[0], ab[1]), ab[0], ab[1])));
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}
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void PPUTranslator::VMAXSB(ppu_opcode_t op)
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@ -1026,7 +1049,7 @@ void PPUTranslator::VMHRADDSHS(ppu_opcode_t op)
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void PPUTranslator::VMINFP(ppu_opcode_t op)
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{
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const auto ab = GetVrs(VrType::vf, op.va, op.vb);
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SetVr(op.vd, VecHandleNan(m_ir->CreateSelect(m_ir->CreateFCmpOLT(ab[0], ab[1]), ab[0], ab[1])));
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SetVr(op.vd, VecHandleResult(m_ir->CreateSelect(m_ir->CreateFCmpOLT(ab[0], ab[1]), ab[0], ab[1])));
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}
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void PPUTranslator::VMINSB(ppu_opcode_t op)
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@ -1236,7 +1259,7 @@ void PPUTranslator::VNMSUBFP(ppu_opcode_t op)
|
||||
|
||||
if (data == v128{})
|
||||
{
|
||||
set_vr(op.vd, vec_handle_nan(-a * c));
|
||||
set_vr(op.vd, vec_handle_result(-a * c));
|
||||
ppu_log.notice("LLVM: VNMSUBFP with 0 addend at [0x%08x]", m_addr + (m_reloc ? m_reloc->addr : 0));
|
||||
return;
|
||||
}
|
||||
@ -1245,7 +1268,7 @@ void PPUTranslator::VNMSUBFP(ppu_opcode_t op)
|
||||
// Differs from the emulated path with regards to negative zero
|
||||
if (m_use_fma)
|
||||
{
|
||||
SetVr(op.vd, VecHandleNan(m_ir->CreateFNeg(m_ir->CreateCall(get_intrinsic<f32[4]>(llvm::Intrinsic::fma), { a.value, c.value, m_ir->CreateFNeg(b.value) }))));
|
||||
SetVr(op.vd, VecHandleResult(m_ir->CreateFNeg(m_ir->CreateCall(get_intrinsic<f32[4]>(llvm::Intrinsic::fma), { a.value, c.value, m_ir->CreateFNeg(b.value) }))));
|
||||
return;
|
||||
}
|
||||
|
||||
@ -1255,7 +1278,7 @@ void PPUTranslator::VNMSUBFP(ppu_opcode_t op)
|
||||
const auto xc = m_ir->CreateFPExt(c.value, get_type<f64[4]>());
|
||||
|
||||
const auto xr = m_ir->CreateFNeg(m_ir->CreateFSub(m_ir->CreateFMul(xa, xc), xb));
|
||||
SetVr(op.vd, VecHandleNan(m_ir->CreateFPTrunc(xr, get_type<f32[4]>())));
|
||||
SetVr(op.vd, VecHandleResult(m_ir->CreateFPTrunc(xr, get_type<f32[4]>())));
|
||||
}
|
||||
|
||||
void PPUTranslator::VNOR(ppu_opcode_t op)
|
||||
@ -1361,28 +1384,28 @@ void PPUTranslator::VPKUWUS(ppu_opcode_t op)
|
||||
|
||||
void PPUTranslator::VREFP(ppu_opcode_t op)
|
||||
{
|
||||
const auto result = VecHandleNan(m_ir->CreateFDiv(ConstantVector::getSplat(4, ConstantFP::get(GetType<f32>(), 1.0)), GetVr(op.vb, VrType::vf)));
|
||||
const auto result = VecHandleResult(m_ir->CreateFDiv(ConstantVector::getSplat(4, ConstantFP::get(GetType<f32>(), 1.0)), GetVr(op.vb, VrType::vf)));
|
||||
SetVr(op.vd, result);
|
||||
}
|
||||
|
||||
void PPUTranslator::VRFIM(ppu_opcode_t op)
|
||||
{
|
||||
SetVr(op.vd, VecHandleNan(Call(GetType<f32[4]>(), "llvm.floor.v4f32", GetVr(op.vb, VrType::vf))));
|
||||
SetVr(op.vd, VecHandleResult(Call(GetType<f32[4]>(), "llvm.floor.v4f32", GetVr(op.vb, VrType::vf))));
|
||||
}
|
||||
|
||||
void PPUTranslator::VRFIN(ppu_opcode_t op)
|
||||
{
|
||||
SetVr(op.vd, VecHandleNan(Call(GetType<f32[4]>(), "llvm.nearbyint.v4f32", GetVr(op.vb, VrType::vf))));
|
||||
SetVr(op.vd, VecHandleResult(Call(GetType<f32[4]>(), "llvm.nearbyint.v4f32", GetVr(op.vb, VrType::vf))));
|
||||
}
|
||||
|
||||
void PPUTranslator::VRFIP(ppu_opcode_t op)
|
||||
{
|
||||
SetVr(op.vd, VecHandleNan(Call(GetType<f32[4]>(), "llvm.ceil.v4f32", GetVr(op.vb, VrType::vf))));
|
||||
SetVr(op.vd, VecHandleResult(Call(GetType<f32[4]>(), "llvm.ceil.v4f32", GetVr(op.vb, VrType::vf))));
|
||||
}
|
||||
|
||||
void PPUTranslator::VRFIZ(ppu_opcode_t op)
|
||||
{
|
||||
SetVr(op.vd, VecHandleNan(Call(GetType<f32[4]>(), "llvm.trunc.v4f32", GetVr(op.vb, VrType::vf))));
|
||||
SetVr(op.vd, VecHandleResult(Call(GetType<f32[4]>(), "llvm.trunc.v4f32", GetVr(op.vb, VrType::vf))));
|
||||
}
|
||||
|
||||
void PPUTranslator::VRLB(ppu_opcode_t op)
|
||||
@ -1407,7 +1430,7 @@ void PPUTranslator::VRSQRTEFP(ppu_opcode_t op)
|
||||
{
|
||||
const auto result = m_ir->CreateFDiv(ConstantVector::getSplat(4, ConstantFP::get(GetType<f32>(), 1.0)), Call(GetType<f32[4]>(), "llvm.sqrt.v4f32", GetVr(op.vb, VrType::vf)));
|
||||
|
||||
SetVr(op.vd, VecHandleNan(result));
|
||||
SetVr(op.vd, VecHandleResult(result));
|
||||
}
|
||||
|
||||
void PPUTranslator::VSEL(ppu_opcode_t op)
|
||||
@ -1565,7 +1588,7 @@ void PPUTranslator::VSUBFP(ppu_opcode_t op)
|
||||
{
|
||||
const auto a = get_vr<f32[4]>(op.va);
|
||||
const auto b = get_vr<f32[4]>(op.vb);
|
||||
SetVr(op.vd, VecHandleNan(eval(a - b).eval(m_ir)));
|
||||
SetVr(op.vd, VecHandleResult(eval(a - b).eval(m_ir)));
|
||||
}
|
||||
|
||||
void PPUTranslator::VSUBSBS(ppu_opcode_t op)
|
||||
|
||||
@ -52,9 +52,9 @@ class PPUTranslator final : public cpu_translator
|
||||
|
||||
llvm::Value* m_mtocr_table{};
|
||||
|
||||
llvm::Value* m_globals[173];
|
||||
llvm::Value* m_globals[175];
|
||||
llvm::Value** const m_g_cr = m_globals + 99;
|
||||
llvm::Value* m_locals[173];
|
||||
llvm::Value* m_locals[175];
|
||||
llvm::Value** const m_gpr = m_locals + 3;
|
||||
llvm::Value** const m_fpr = m_locals + 35;
|
||||
llvm::Value** const m_vr = m_locals + 67;
|
||||
@ -77,6 +77,7 @@ class PPUTranslator final : public cpu_translator
|
||||
DEF_VALUE(m_cnt, m_g_cnt, 170) // XER.CNT
|
||||
DEF_VALUE(m_sat, m_g_sat, 171) // VSCR.SAT bit, sticky saturation flag
|
||||
DEF_VALUE(m_nj, m_g_nj, 172) // VSCR.NJ bit, non-Java mode
|
||||
DEF_VALUE(m_jm_mask, m_g_jm_mask, 174) // Java-Mode helper mask
|
||||
|
||||
#undef DEF_VALUE
|
||||
public:
|
||||
@ -102,15 +103,14 @@ public:
|
||||
}
|
||||
|
||||
llvm::Value* VecHandleNan(llvm::Value* val);
|
||||
llvm::Value* VecHandleDenormal(llvm::Value* val);
|
||||
llvm::Value* VecHandleResult(llvm::Value* val);
|
||||
|
||||
template <typename T>
|
||||
auto vec_handle_nan(T&& expr)
|
||||
auto vec_handle_result(T&& expr)
|
||||
{
|
||||
value_t<typename T::type> result;
|
||||
if (g_cfg.core.llvm_ppu_accurate_vector_nan)
|
||||
result.value = VecHandleNan(expr.eval(m_ir));
|
||||
else
|
||||
result.value = expr.eval(m_ir);
|
||||
result.value = VecHandleResult(expr.eval(m_ir));
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
@ -52,6 +52,7 @@ struct cfg_root : cfg::node
|
||||
cfg::_bool spu_accurate_xfloat{ this, "Accurate xfloat", false };
|
||||
cfg::_bool spu_approx_xfloat{ this, "Approximate xfloat", true };
|
||||
cfg::_bool llvm_accurate_dfma{ this, "LLVM Accurate DFMA", true }; // Enable accurate double-precision FMA for CPUs which do not support it natively
|
||||
cfg::_bool llvm_ppu_jm_handling{ this, "PPU LLVM Java Mode Handling", false }; // Respect current Java Mode for alti-vec ops by PPU LLVM
|
||||
cfg::_bool llvm_ppu_accurate_vector_nan{ this, "PPU LLVM Accurate Vector NaN values", false };
|
||||
cfg::_int<-64, 64> stub_ppu_traps{ this, "Stub PPU Traps", 0, true }; // Hack, skip PPU traps for rare cases where the trap is continueable (specify relative instructions to skip)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user