From 8eae8cb86c740317abe3b9e88e73d661d210d67b Mon Sep 17 00:00:00 2001
From: kd-11 <karokidii@gmail.com>
Date: Sun, 21 Jan 2024 04:14:14 +0300
Subject: [PATCH] rsx: Do not emit rounding code when not needed

---
 .../GLSLSnippets/RSXProg/RSXFragmentPrologue.glsl    | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/rpcs3/Emu/RSX/Program/GLSLSnippets/RSXProg/RSXFragmentPrologue.glsl b/rpcs3/Emu/RSX/Program/GLSLSnippets/RSXProg/RSXFragmentPrologue.glsl
index 5b388e3187..4b842dbdfd 100644
--- a/rpcs3/Emu/RSX/Program/GLSLSnippets/RSXProg/RSXFragmentPrologue.glsl
+++ b/rpcs3/Emu/RSX/Program/GLSLSnippets/RSXProg/RSXFragmentPrologue.glsl
@@ -6,11 +6,6 @@ R"(
 #else
 // Mixed types. We have fp16 outputs
 #define _mrt_color_t f16vec4
-f16vec4 round_to_8bit(const in f16vec4 v4)
-{
-	uvec4 raw = uvec4(floor(fma(v4, f16vec4(255.), f16vec4(0.5))));
-	return f16vec4(raw) / f16vec4(255.);
-}
 #endif
 
 #if defined(_ENABLE_ROP_OUTPUT_ROUNDING) || defined(_ENABLE_PROGRAMMABLE_BLENDING)
@@ -20,6 +15,13 @@ vec4 round_to_8bit(const in vec4 v4)
 	uvec4 raw = uvec4(floor(fma(v4, vec4(255.), vec4(0.5))));
 	return vec4(raw) / vec4(255.);
 }
+#ifndef _32_BIT_OUTPUT
+f16vec4 round_to_8bit(const in f16vec4 v4)
+{
+	uvec4 raw = uvec4(floor(fma(v4, f16vec4(255.), f16vec4(0.5))));
+	return f16vec4(raw) / f16vec4(255.);
+}
+#endif
 #endif
 
 #ifdef _DISABLE_EARLY_DISCARD