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SPU LLVM: split LLVM IR dump to spu-ir.log
Also move disasm to spu_recompiler_base::dump. Interleave disasm with block target info for convenience.
This commit is contained in:
parent
ea554ae828
commit
82295d131a
@ -474,6 +474,7 @@ spu_runtime::spu_runtime()
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if (g_cfg.core.spu_debug)
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{
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fs::file(m_cache_path + "spu.log", fs::rewrite);
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fs::file(m_cache_path + "spu-ir.log", fs::rewrite);
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}
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LOG_SUCCESS(SPU, "SPU Recompiler Runtime initialized...");
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@ -3037,8 +3038,36 @@ const std::vector<u32>& spu_recompiler_base::analyse(const be_t<u32>* ls, u32 en
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void spu_recompiler_base::dump(std::string& out)
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{
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SPUDisAsm dis_asm(CPUDisAsm_InterpreterMode);
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dis_asm.offset = reinterpret_cast<const u8*>(result.data() + 1);
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if (g_cfg.core.spu_block_size != spu_block_size_type::giga)
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{
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dis_asm.offset -= result[0];
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}
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std::string hash;
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{
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sha1_context ctx;
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u8 output[20];
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sha1_starts(&ctx);
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sha1_update(&ctx, reinterpret_cast<const u8*>(result.data() + 1), result.size() * 4 - 4);
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sha1_finish(&ctx, output);
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fmt::append(hash, "%s", fmt::base57(output));
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}
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fmt::append(out, "========== SPU BLOCK 0x%05x (size %u, %s) ==========\n", result[0], result.size() - 1, hash);
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for (auto& bb : m_bbs)
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{
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for (u32 pos = bb.first, end = bb.first + bb.second.size * 4; pos < end; pos += 4)
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{
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dis_asm.dump_pc = pos;
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dis_asm.disasm(pos);
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fmt::append(out, ">%s\n", dis_asm.last_opcode);
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}
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if (m_block_info[bb.first / 4])
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{
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fmt::append(out, "A: [0x%05x] %s\n", bb.first, m_entry_info[bb.first / 4] ? (m_ret_info[bb.first / 4] ? "Chunk" : "Entry") : "Block");
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@ -3059,6 +3088,8 @@ void spu_recompiler_base::dump(std::string& out)
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{
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fmt::append(out, "A: [0x%05x] ?\n", bb.first);
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}
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out += '\n';
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}
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for (auto& f : m_funcs)
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@ -4050,6 +4081,8 @@ public:
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return nullptr;
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}
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std::string log;
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if (m_cache && g_cfg.core.spu_cache)
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{
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m_cache->add(func);
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@ -4076,14 +4109,6 @@ public:
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LOG_NOTICE(SPU, "Building function 0x%x... (size %u, %s)", func[0], func.size() - 1, m_hash);
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}
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SPUDisAsm dis_asm(CPUDisAsm_InterpreterMode);
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dis_asm.offset = reinterpret_cast<const u8*>(func.data() + 1);
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if (g_cfg.core.spu_block_size != spu_block_size_type::giga)
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{
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dis_asm.offset -= func[0];
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}
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m_pos = func[0];
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m_base = func[0];
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m_size = (func.size() - 1) * 4;
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@ -4092,31 +4117,6 @@ public:
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if (g_cfg.core.spu_debug)
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{
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std::string log;
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fmt::append(log, "========== SPU BLOCK 0x%05x (size %u, %s) ==========\n\n", func[0], func.size() - 1, m_hash);
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// Disassemble if necessary
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for (u32 i = 1; i < func.size(); i++)
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{
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const u32 pos = start + (i - 1) * 4;
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// Disasm
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dis_asm.dump_pc = pos;
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dis_asm.disasm(pos);
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if (func[i])
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{
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log += '>';
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log += dis_asm.last_opcode;
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log += '\n';
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}
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else
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{
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fmt::append(log, ">[%08x] xx xx xx xx: <hole>\n", pos);
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}
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}
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log += '\n';
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this->dump(log);
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fs::file(m_spurt->get_cache_path() + "spu.log", fs::write + fs::append).write(log);
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}
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@ -4622,8 +4622,6 @@ public:
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m_function_queue.clear();
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m_function_table = nullptr;
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std::string log;
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raw_string_ostream out(log);
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if (g_cfg.core.spu_debug)
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@ -4640,7 +4638,7 @@ public:
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if (g_cfg.core.spu_debug)
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{
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fs::file(m_spurt->get_cache_path() + "spu.log", fs::write + fs::append).write(log);
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fs::file(m_spurt->get_cache_path() + "spu-ir.log", fs::write + fs::append).write(log);
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}
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fmt::raw_error("Compilation failed");
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@ -4669,7 +4667,7 @@ public:
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if (g_cfg.core.spu_debug)
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{
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out.flush();
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fs::file(m_spurt->get_cache_path() + "spu.log", fs::write + fs::append).write(log);
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fs::file(m_spurt->get_cache_path() + "spu-ir.log", fs::write + fs::append).write(log);
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}
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return fn;
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@ -5006,7 +5004,7 @@ public:
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if (g_cfg.core.spu_debug)
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{
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fs::file(m_spurt->get_cache_path() + "spu.log", fs::write + fs::append).write(log);
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fs::file(m_spurt->get_cache_path() + "spu-ir.log", fs::write + fs::append).write(log);
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}
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fmt::raw_error("Compilation failed");
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@ -5035,7 +5033,7 @@ public:
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if (g_cfg.core.spu_debug)
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{
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out.flush();
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fs::file(m_spurt->get_cache_path() + "spu.log", fs::write + fs::append).write(log);
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fs::file(m_spurt->get_cache_path() + "spu-ir.log", fs::write + fs::append).write(log);
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}
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return spu_runtime::g_interpreter;
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