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Merge pull request #309 from raven02/patch-7

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Fix opcodes STR/SFL for both VP and FP
This commit is contained in:
B1ackDaemon 2014-06-03 23:08:44 +03:00
commit 77f818fa23
2 changed files with 6 additions and 5 deletions
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6
rpcs3/Emu/GS/GL/GLFragmentProgram.cpp
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@ -293,8 +293,8 @@ void GLFragmentDecompilerThread::Task()
//case 0x1e: break; // LIT (compute light coefficients)
case 0x1f: AddCode("(" + GetSRC(src0) + " * (" + GetSRC(src1) + " - " + GetSRC(src2) + ") +" + GetSRC(src2) + ")"); break; // LRP (linear interpolation)
case 0x20: AddCode("vec4(1.0)"); break; // STR (set on true)
case 0x21: AddCode("vec4(0.0)"); break; // SFL (set on false)
case 0x20: AddCode("vec4(equal(" + GetSRC(src0) + ", vec4(1)))"); break; // STR (set on true)
case 0x21: AddCode("vec4(equal(" + GetSRC(src0) + ", vec4(0)))"); break; // SFL (set on false)
case 0x22: AddCode("cos(" + GetSRC(src0) + ")"); break; // COS
case 0x23: AddCode("sin(" + GetSRC(src0) + ")"); break; // SIN
//case 0x24: break; // PK2 (pack two 16-bit floats)
@ -326,7 +326,7 @@ void GLFragmentDecompilerThread::Task()
case 0x3e: break; // FENCB
default:
ConLog.Error("Unknown opcode 0x%x (inst %d)", opcode, m_size / (4 * 4));
ConLog.Error("Unknown fp opcode 0x%x (inst %d)", opcode, m_size / (4 * 4));
//Emu.Pause();
break;
}

5
rpcs3/Emu/GS/GL/GLVertexProgram.cpp
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@ -408,14 +408,15 @@ void GLVertexDecompilerThread::Task()
case 0x0a: AddVecCode("max(" + GetSRC(0) + ", " + GetSRC(1) + ")"); break; //MAX
case 0x0b: AddVecCode("vec4(lessThan(" + GetSRC(0) + ", " + GetSRC(1) + "))"); break; //SLT
case 0x0c: AddVecCode("vec4(greaterThanEqual(" + GetSRC(0) + ", " + GetSRC(1) + "))"); break; //SGE
//case 0x0d: break;
case 0x0e: AddVecCode("fract(" + GetSRC(0) + ")"); break; //FRC
case 0x0f: AddVecCode("floor(" + GetSRC(0) + ")"); break; //FLR
case 0x10: AddVecCode("vec4(equal(" + GetSRC(0) + ", " + GetSRC(1) + "))"); break; //SEQ
//case 0x11: AddVecCode("vec4(equal(" + GetSRC(0) + ", vec4(0, 0, 0, 0)))"); break; //SFL
case 0x11: AddVecCode("vec4(equal(" + GetSRC(0) + ", vec4(0)))"); break; //SFL
case 0x12: AddVecCode("vec4(greaterThan(" + GetSRC(0) + ", " + GetSRC(1) + "))"); break; //SGT
case 0x13: AddVecCode("vec4(lessThanEqual(" + GetSRC(0) + ", " + GetSRC(1) + "))"); break; //SLE
case 0x14: AddVecCode("vec4(notEqual(" + GetSRC(0) + ", " + GetSRC(1) + "))"); break; //SNE
//case 0x15: AddVecCode("vec4(notEqual(" + GetSRC(0) + ", vec4(0, 0, 0, 0)))"); break; //STR
case 0x15: AddVecCode("vec4(equal(" + GetSRC(0) + ", vec4(1)))"); break; //STR
case 0x16: AddVecCode("sign(" + GetSRC(0) + ")"); break; //SSG
default: