SPU LLVM: Hook up 128 bit spu verification

- Also fix FMA enablement for sapphirerapids
This commit is contained in:
Malcolm Jestadt 2021-11-05 17:05:04 -04:00 committed by Ivan
parent f9abe40494
commit 7573d7289b
3 changed files with 21 additions and 10 deletions

View File

@ -85,6 +85,14 @@ void cpu_translator::initialize(llvm::LLVMContext& context, llvm::ExecutionEngin
m_use_ssse3 = false; m_use_ssse3 = false;
} }
// Test AVX feature (TODO)
if (cpu == "sandybridge" ||
cpu == "ivybridge" ||
cpu == "bdver1")
{
m_use_avx = true;
}
// Test FMA feature (TODO) // Test FMA feature (TODO)
if (cpu == "haswell" || if (cpu == "haswell" ||
cpu == "broadwell" || cpu == "broadwell" ||
@ -96,19 +104,16 @@ void cpu_translator::initialize(llvm::LLVMContext& context, llvm::ExecutionEngin
cpu.startswith("znver")) cpu.startswith("znver"))
{ {
m_use_fma = true; m_use_fma = true;
m_use_avx = true;
} }
// Test AVX-512 feature (TODO) // Test AVX-512 feature (TODO)
if (cpu == "skylake-avx512" || if (cpu == "skylake-avx512" ||
cpu == "cascadelake" || cpu == "cascadelake" ||
cpu == "cannonlake" || cpu == "cannonlake" ||
cpu == "cooperlake" || cpu == "cooperlake")
cpu == "icelake" ||
cpu == "icelake-client" ||
cpu == "icelake-server" ||
cpu == "tigerlake" ||
cpu == "rocketlake")
{ {
m_use_avx = true;
m_use_fma = true; m_use_fma = true;
m_use_avx512 = true; m_use_avx512 = true;
} }
@ -129,6 +134,9 @@ void cpu_translator::initialize(llvm::LLVMContext& context, llvm::ExecutionEngin
cpu == "rocketlake" || cpu == "rocketlake" ||
cpu == "sapphirerapids") cpu == "sapphirerapids")
{ {
m_use_avx = true;
m_use_fma = true;
m_use_avx512 = true;
m_use_avx512_icl = true; m_use_avx512_icl = true;
m_use_vnni = true; m_use_vnni = true;
} }

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@ -2886,6 +2886,9 @@ protected:
// Allow FMA // Allow FMA
bool m_use_fma = false; bool m_use_fma = false;
// Allow AVX
bool m_use_avx = false;
// Allow skylake-x tier AVX-512 // Allow skylake-x tier AVX-512
bool m_use_avx512 = false; bool m_use_avx512 = false;

View File

@ -4485,13 +4485,13 @@ public:
elements = 16; elements = 16;
dwords = 8; dwords = 8;
} }
else if (true) else if (m_use_avx)
{ {
stride = 32; stride = 32;
elements = 8; elements = 8;
dwords = 4; dwords = 4;
} }
else // TODO: Use this path when the cpu doesn't support AVX else
{ {
stride = 16; stride = 16;
elements = 4; elements = 4;
@ -4539,7 +4539,7 @@ public:
{ {
vls = m_ir->CreateAlignedLoad(_ptr<u32[16]>(data_addr, j - starta), llvm::MaybeAlign{4}); vls = m_ir->CreateAlignedLoad(_ptr<u32[16]>(data_addr, j - starta), llvm::MaybeAlign{4});
} }
else if (true) else if (m_use_avx)
{ {
vls = m_ir->CreateAlignedLoad(_ptr<u32[8]>(data_addr, j - starta), llvm::MaybeAlign{4}); vls = m_ir->CreateAlignedLoad(_ptr<u32[8]>(data_addr, j - starta), llvm::MaybeAlign{4});
} }
@ -4573,7 +4573,7 @@ public:
{ {
acc = m_ir->CreateBitCast(acc, get_type<u64[8]>()); acc = m_ir->CreateBitCast(acc, get_type<u64[8]>());
} }
else if (true) else if (m_use_avx)
{ {
acc = m_ir->CreateBitCast(acc, get_type<u64[4]>()); acc = m_ir->CreateBitCast(acc, get_type<u64[4]>());
} }