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rsx: Improve framebuffer check heuristics for contested memory buffers
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33f3a3e014
commit
63f261a66d
@ -169,6 +169,7 @@ void GLGSRender::init_buffers(bool skip_reading)
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const u16 clip_y = rsx::method_registers.surface_clip_origin_y();
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framebuffer_status_valid = false;
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m_framebuffer_state_contested = false;
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if (clip_horizontal == 0 || clip_vertical == 0)
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{
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@ -207,10 +208,22 @@ void GLGSRender::init_buffers(bool skip_reading)
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if (surface_addresses[index] == depth_address &&
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zeta_pitch >= required_z_pitch)
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{
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//LOG_ERROR(RSX, "Some game dev set up the MRT to write to the same address as depth and color attachment. Not sure how to deal with that so the draw is discarded.");
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//framebuffer_status_valid = false;
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depth_address = 0;
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break;
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LOG_TRACE(RSX, "Framebuffer at 0x%X has aliasing color/depth targets, zeta_pitch = %d, color_pitch=%d", depth_address, zeta_pitch, pitchs[index]);
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m_framebuffer_state_contested = true;
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if (rsx::method_registers.depth_test_enabled() ||
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(!rsx::method_registers.color_write_enabled() && rsx::method_registers.depth_write_enabled()) ||
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!!(rsx::method_registers.shader_control() & CELL_GCM_SHADER_CONTROL_DEPTH_EXPORT))
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{
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// Use address for depth data
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surface_addresses[index] = 0;
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}
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else
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{
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// Use address for color data
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depth_address = 0;
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break;
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}
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}
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}
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@ -188,6 +188,7 @@ namespace rsx
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bool m_transform_constants_dirty;
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bool m_textures_dirty[16];
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bool m_vertex_textures_dirty[4];
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bool m_framebuffer_state_contested = false;
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protected:
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std::array<u32, 4> get_color_surface_addresses() const;
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@ -2315,6 +2315,7 @@ void VKGSRender::prepare_rtts()
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u32 clip_y = rsx::method_registers.surface_clip_origin_y();
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framebuffer_status_valid = false;
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m_framebuffer_state_contested = false;
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if (clip_width == 0 || clip_height == 0)
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{
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@ -2354,10 +2355,23 @@ void VKGSRender::prepare_rtts()
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if (surface_addresses[index] == zeta_address &&
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zeta_pitch >= required_z_pitch)
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{
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//LOG_ERROR(RSX, "Some game dev set up the MRT to write to the same address as depth and color attachment. Not sure how to deal with that so the draw is discarded.");
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//framebuffer_status_valid = false;
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zeta_address = 0;
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break;
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LOG_TRACE(RSX, "Framebuffer at 0x%X has aliasing color/depth targets, zeta_pitch = %d, color_pitch=%d", zeta_address, zeta_pitch, surface_pitchs[index]);
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m_framebuffer_state_contested = true;
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if (rsx::method_registers.depth_test_enabled() ||
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(!rsx::method_registers.color_write_enabled() && rsx::method_registers.depth_write_enabled()) ||
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!!(rsx::method_registers.shader_control() & CELL_GCM_SHADER_CONTROL_DEPTH_EXPORT))
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{
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// Use address for color data
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zeta_address = 0;
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break;
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}
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else
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{
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// Use address for depth data
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// TODO: create a temporary render buffer for this to keep MRT outputs aligned
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surface_addresses[index] = 0;
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}
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}
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}
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@ -3196,6 +3196,11 @@ struct registers_decoder<NV4097_SET_COLOR_MASK>
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{
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return bool(m_data.color_a);
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}
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bool color_write_enabled() const
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{
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return m_data.raw_data != 0;
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}
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};
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static std::string dump(decoded_type &&decoded_values)
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@ -471,6 +471,12 @@ namespace rsx
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rsx->m_rtts_dirty = true;
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}
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void set_surface_options_dirty_bit(thread* rsx, u32, u32)
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{
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if (rsx->m_framebuffer_state_contested)
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rsx->m_rtts_dirty = true;
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}
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template<u32 index>
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struct set_texture_dirty_bit
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{
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@ -1598,6 +1604,9 @@ namespace rsx
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bind<NV4097_SET_ZCULL_STATS_ENABLE, nv4097::set_zcull_stats_enable>();
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bind<NV4097_SET_ZPASS_PIXEL_COUNT_ENABLE, nv4097::set_zcull_pixel_count_enable>();
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bind<NV4097_CLEAR_ZCULL_SURFACE, nv4097::clear_zcull>();
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bind<NV4097_SET_DEPTH_TEST_ENABLE, nv4097::set_surface_options_dirty_bit>();
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bind<NV4097_SET_DEPTH_MASK, nv4097::set_surface_options_dirty_bit>();
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bind<NV4097_SET_COLOR_MASK, nv4097::set_surface_options_dirty_bit>();
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//NV308A
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bind_range<NV308A_COLOR, 1, 256, nv308a::color>();
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@ -345,6 +345,11 @@ namespace rsx
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return decode<NV4097_SET_COLOR_MASK>().color_a();
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}
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bool color_write_enabled() const
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{
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return decode<NV4097_SET_COLOR_MASK>().color_write_enabled();
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}
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u8 clear_color_b() const
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{
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return decode<NV4097_SET_COLOR_CLEAR_VALUE>().blue();
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