mirror of
https://github.com/RPCS3/rpcs3.git
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Some code moved to ARMv7Decoder.cpp
This commit is contained in:
Nekotekina
parent
ab501842c8
commit
6069be7a93
628
rpcs3/Emu/ARMv7/ARMv7Decoder.cpp
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628
rpcs3/Emu/ARMv7/ARMv7Decoder.cpp
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@ -0,0 +1,628 @@
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#include "stdafx.h"
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#include "Utilities/Log.h"
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#include "ARMv7Thread.h"
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#include "ARMv7Interpreter.h"
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#include "ARMv7Opcodes.h"
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#include "ARMv7Decoder.h"
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struct ARMv7_opcode_t
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{
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u32 mask;
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u32 code;
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u32 length; // 2 or 4
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const char* name;
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ARMv7_encoding type;
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void(*func)(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type);
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};
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// single 16-bit value
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#define ARMv7_OP2(mask, code, type, name) { (u32)((mask) << 16), (u32)((code) << 16), 2, #name "_" #type, type, ARMv7_instrs::name }
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// two 16-bit values
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#define ARMv7_OP4(mask0, mask1, code0, code1, type, name) { (u32)((mask0) << 16) | (mask1), (u32)((code0) << 16) | (code1), 4, #name "_" #type, type, ARMv7_instrs::name }
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const ARMv7_opcode_t ARMv7_opcode_table[] =
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{
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ARMv7_OP2(0xffff, 0x0000, T1, NULL_OP), // ???
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ARMv7_OP4(0xffff, 0x0000, 0xf870, 0x0000, T1, HACK), // "Undefined" Thumb opcode
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ARMv7_OP4(0x0ff0, 0x00f0, 0x0070, 0x0090, A1, HACK), // "Undefined" ARM opcode
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ARMv7_OP4(0xfbe0, 0x8000, 0xf140, 0x0000, T1, ADC_IMM),
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ARMv7_OP4(0x0fe0, 0x0000, 0x02a0, 0x0000, A1, ADC_IMM),
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ARMv7_OP2(0xffc0, 0x4040, T1, ADC_REG),
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ARMv7_OP4(0xffe0, 0x8000, 0xeb40, 0x0000, T2, ADC_REG),
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ARMv7_OP4(0x0fe0, 0x0010, 0x00a0, 0x0000, A1, ADC_REG),
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ARMv7_OP4(0x0fe0, 0x0090, 0x00a0, 0x0010, A1, ADC_RSR),
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ARMv7_OP2(0xf800, 0xa800, T1, ADD_SPI),
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ARMv7_OP2(0xff80, 0xb000, T2, ADD_SPI),
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ARMv7_OP4(0xfbef, 0x8000, 0xf10d, 0x0000, T3, ADD_SPI),
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ARMv7_OP4(0xfbff, 0x8000, 0xf20d, 0x0000, T4, ADD_SPI),
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ARMv7_OP4(0x0fef, 0x0000, 0x028d, 0x0000, A1, ADD_SPI),
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ARMv7_OP2(0xff78, 0x4468, T1, ADD_SPR),
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ARMv7_OP2(0xff87, 0x4485, T2, ADD_SPR),
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ARMv7_OP4(0xffef, 0x8000, 0xeb0d, 0x0000, T3, ADD_SPR),
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ARMv7_OP4(0x0fef, 0x0010, 0x008d, 0x0000, A1, ADD_SPR),
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ARMv7_OP2(0xfe00, 0x1c00, T1, ADD_IMM),
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ARMv7_OP2(0xf800, 0x3000, T2, ADD_IMM),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf100, 0x0000, T3, ADD_IMM),
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ARMv7_OP4(0xfbf0, 0x8000, 0xf200, 0x0000, T4, ADD_IMM),
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ARMv7_OP4(0x0fe0, 0x0000, 0x0280, 0x0000, A1, ADD_IMM),
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ARMv7_OP2(0xfe00, 0x1800, T1, ADD_REG),
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ARMv7_OP2(0xff00, 0x4400, T2, ADD_REG),
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ARMv7_OP4(0xffe0, 0x8000, 0xeb00, 0x0000, T3, ADD_REG),
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ARMv7_OP4(0x0fe0, 0x0010, 0x0080, 0x0000, A1, ADD_REG),
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ARMv7_OP4(0x0fe0, 0x0090, 0x0080, 0x0010, A1, ADD_RSR),
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ARMv7_OP2(0xf800, 0xa000, T1, ADR),
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ARMv7_OP4(0xfbff, 0x8000, 0xf2af, 0x0000, T2, ADR),
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ARMv7_OP4(0xfbff, 0x8000, 0xf20f, 0x0000, T3, ADR),
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ARMv7_OP4(0x0fff, 0x0000, 0x028f, 0x0000, A1, ADR),
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ARMv7_OP4(0x0fff, 0x0000, 0x024f, 0x0000, A2, ADR),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf000, 0x0000, T1, AND_IMM),
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ARMv7_OP4(0x0fe0, 0x0000, 0x0200, 0x0000, A1, AND_IMM),
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ARMv7_OP2(0xffc0, 0x4000, T1, AND_REG),
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ARMv7_OP4(0xffe0, 0x8000, 0xea00, 0x0000, T2, AND_REG),
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ARMv7_OP4(0x0fe0, 0x0010, 0x0000, 0x0000, A1, AND_REG),
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ARMv7_OP4(0x0fe0, 0x0090, 0x0000, 0x0010, A1, AND_RSR),
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ARMv7_OP2(0xf800, 0x1000, T1, ASR_IMM),
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ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0020, T2, ASR_IMM),
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ARMv7_OP4(0x0fef, 0x0070, 0x01a0, 0x0040, A1, ASR_IMM),
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ARMv7_OP2(0xffc0, 0x4100, T1, ASR_REG),
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ARMv7_OP4(0xffe0, 0xf0f0, 0xfa40, 0xf000, T2, ASR_REG),
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ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0050, A1, ASR_REG),
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ARMv7_OP2(0xf000, 0xd000, T1, B),
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ARMv7_OP2(0xf800, 0xe000, T2, B),
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ARMv7_OP4(0xf800, 0xd000, 0xf000, 0x8000, T3, B),
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ARMv7_OP4(0xf800, 0xd000, 0xf000, 0x9000, T4, B),
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ARMv7_OP4(0x0f00, 0x0000, 0x0a00, 0x0000, A1, B),
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ARMv7_OP4(0xffff, 0x8020, 0xf36f, 0x0000, T1, BFC),
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ARMv7_OP4(0x0fe0, 0x007f, 0x07c0, 0x001f, A1, BFC),
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ARMv7_OP4(0xfff0, 0x8020, 0xf360, 0x0000, T1, BFI),
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ARMv7_OP4(0x0fe0, 0x0070, 0x07c0, 0x0010, A1, BFI),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf020, 0x0000, T1, BIC_IMM),
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ARMv7_OP4(0x0fe0, 0x0000, 0x03c0, 0x0000, A1, BIC_IMM),
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ARMv7_OP2(0xffc0, 0x4380, T1, BIC_REG),
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ARMv7_OP4(0xffe0, 0x8000, 0xea20, 0x0000, T2, BIC_REG),
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ARMv7_OP4(0x0fe0, 0x0010, 0x01c0, 0x0000, A1, BIC_REG),
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ARMv7_OP4(0x0fe0, 0x0090, 0x01c0, 0x0010, A1, BIC_RSR),
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ARMv7_OP2(0xff00, 0xbe00, T1, BKPT),
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ARMv7_OP4(0x0ff0, 0x00f0, 0x0120, 0x0070, A1, BKPT),
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ARMv7_OP4(0xf800, 0xd000, 0xf000, 0xd000, T1, BL),
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ARMv7_OP4(0x0f00, 0x0000, 0x0b00, 0x0000, A1, BL),
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ARMv7_OP2(0xff80, 0x4780, T1, BLX),
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ARMv7_OP4(0xf800, 0xc001, 0xf000, 0xc000, T2, BLX),
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ARMv7_OP4(0x0fff, 0xfff0, 0x012f, 0xff30, A1, BLX),
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ARMv7_OP4(0xfe00, 0x0000, 0xfa00, 0x0000, A2, BLX),
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ARMv7_OP2(0xff87, 0x4700, T1, BX),
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ARMv7_OP4(0x0fff, 0xfff0, 0x012f, 0xff10, A1, BX),
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ARMv7_OP2(0xf500, 0xb100, T1, CB_Z),
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ARMv7_OP4(0xfff0, 0xf0f0, 0xfab0, 0xf080, T1, CLZ),
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ARMv7_OP4(0x0fff, 0x0ff0, 0x016f, 0x0f10, A1, CLZ),
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ARMv7_OP4(0xfbf0, 0x8f00, 0xf110, 0x0f00, T1, CMN_IMM),
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ARMv7_OP4(0x0ff0, 0xf000, 0x0370, 0x0000, A1, CMN_IMM),
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ARMv7_OP2(0xffc0, 0x42c0, T1, CMN_REG),
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ARMv7_OP4(0xfff0, 0x8f00, 0xeb10, 0x0f00, T2, CMN_REG),
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ARMv7_OP4(0x0ff0, 0xf010, 0x0170, 0x0000, A1, CMN_REG),
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ARMv7_OP4(0x0ff0, 0xf090, 0x0170, 0x0010, A1, CMN_RSR),
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ARMv7_OP2(0xf800, 0x2800, T1, CMP_IMM),
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ARMv7_OP4(0xfbf0, 0x8f00, 0xf1b0, 0x0f00, T2, CMP_IMM),
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ARMv7_OP4(0x0ff0, 0xf000, 0x0350, 0x0000, A1, CMP_IMM),
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ARMv7_OP2(0xffc0, 0x4280, T1, CMP_REG),
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ARMv7_OP2(0xff00, 0x4500, T2, CMP_REG),
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ARMv7_OP4(0xfff0, 0x8f00, 0xebb0, 0x0f00, T3, CMP_REG),
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ARMv7_OP4(0x0ff0, 0xf010, 0x0150, 0x0000, A1, CMP_REG),
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ARMv7_OP4(0x0ff0, 0xf090, 0x0150, 0x0010, A1, CMP_RSR),
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ARMv7_OP4(0xfbe0, 0x8000, 0xf080, 0x0000, T1, EOR_IMM),
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ARMv7_OP4(0x0fe0, 0x0000, 0x0220, 0x0000, A1, EOR_IMM),
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ARMv7_OP2(0xffc0, 0x4040, T1, EOR_REG),
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ARMv7_OP4(0xffe0, 0x8000, 0xea80, 0x0000, T2, EOR_REG),
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ARMv7_OP4(0x0fe0, 0x0010, 0x0020, 0x0000, A1, EOR_REG),
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ARMv7_OP4(0x0fe0, 0x0090, 0x0020, 0x0010, A1, EOR_RSR),
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ARMv7_OP2(0xff00, 0xbf00, T1, IT),
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ARMv7_OP4(0xfff0, 0x0f00, 0xe850, 0x0f00, T1, LDREX),
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ARMv7_OP4(0x0ff0, 0x0fff, 0x0190, 0x0f9f, A1, LDREX),
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ARMv7_OP4(0xfff0, 0x0fff, 0xe8d0, 0x0f4f, T1, LDREXB),
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ARMv7_OP4(0x0ff0, 0x0fff, 0x01d0, 0x0f9f, A1, LDREXB),
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ARMv7_OP4(0xfff0, 0x00ff, 0xe8d0, 0x007f, T1, LDREXD),
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ARMv7_OP4(0x0ff0, 0x0fff, 0x01b0, 0x0f9f, A1, LDREXD),
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ARMv7_OP4(0xfff0, 0x0fff, 0xe8d0, 0x0f5f, T1, LDREXH),
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ARMv7_OP4(0x0ff0, 0x0fff, 0x01f0, 0x0f9f, A1, LDREXH),
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ARMv7_OP2(0xf800, 0xc800, T1, LDM),
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ARMv7_OP4(0xffd0, 0x2000, 0xe890, 0x0000, T2, LDM),
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ARMv7_OP4(0x0fd0, 0x0000, 0x0890, 0x0000, A1, LDM),
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ARMv7_OP4(0x0fd0, 0x0000, 0x0810, 0x0000, A1, LDMDA),
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ARMv7_OP4(0xffd0, 0x2000, 0xe910, 0x0000, T1, LDMDB),
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ARMv7_OP4(0x0fd0, 0x0000, 0x0910, 0x0000, A1, LDMDB),
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ARMv7_OP4(0x0fd0, 0x0000, 0x0990, 0x0000, A1, LDMIB),
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ARMv7_OP2(0xf800, 0x6800, T1, LDR_IMM),
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ARMv7_OP2(0xf800, 0x9800, T2, LDR_IMM),
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ARMv7_OP4(0xfff0, 0x0000, 0xf8d0, 0x0000, T3, LDR_IMM),
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ARMv7_OP4(0xfff0, 0x0800, 0xf850, 0x0800, T4, LDR_IMM),
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ARMv7_OP4(0x0e50, 0x0000, 0x0410, 0x0000, A1, LDR_IMM),
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ARMv7_OP2(0xf800, 0x4800, T1, LDR_LIT),
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ARMv7_OP4(0xff7f, 0x0000, 0xf85f, 0x0000, T2, LDR_LIT),
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ARMv7_OP4(0x0f7f, 0x0000, 0x051f, 0x0000, A1, LDR_LIT),
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ARMv7_OP2(0xfe00, 0x5800, T1, LDR_REG),
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ARMv7_OP4(0xfff0, 0x0fc0, 0xf850, 0x0000, T2, LDR_REG),
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ARMv7_OP4(0x0e50, 0x0010, 0x0610, 0x0000, A1, LDR_REG),
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ARMv7_OP2(0xf800, 0x7800, T1, LDRB_IMM),
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ARMv7_OP4(0xfff0, 0x0000, 0xf890, 0x0000, T2, LDRB_IMM),
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ARMv7_OP4(0xfff0, 0x0800, 0xf810, 0x0800, T3, LDRB_IMM),
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ARMv7_OP4(0x0e50, 0x0000, 0x0450, 0x0000, A1, LDRB_IMM),
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ARMv7_OP4(0xff7f, 0x0000, 0xf81f, 0x0000, T1, LDRB_LIT),
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ARMv7_OP4(0x0f7f, 0x0000, 0x055f, 0x0000, A1, LDRB_LIT),
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ARMv7_OP2(0xfe00, 0x5c00, T1, LDRB_REG),
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ARMv7_OP4(0xfff0, 0x0fc0, 0xf810, 0x0000, T2, LDRB_REG),
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ARMv7_OP4(0x0e50, 0x0010, 0x0650, 0x0000, A1, LDRB_REG),
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ARMv7_OP4(0xfe50, 0x0000, 0xe850, 0x0000, T1, LDRD_IMM),
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ARMv7_OP4(0x0e50, 0x00f0, 0x0040, 0x00d0, A1, LDRD_IMM),
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ARMv7_OP4(0xfe7f, 0x0000, 0xe85f, 0x0000, T1, LDRD_LIT),
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ARMv7_OP4(0x0f7f, 0x00f0, 0x014f, 0x00d0, A1, LDRD_LIT),
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ARMv7_OP4(0x0e50, 0x0ff0, 0x0000, 0x00d0, A1, LDRD_REG),
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ARMv7_OP4(0xfff0, 0x0000, 0xf990, 0x0000, T1, LDRSB_IMM),
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ARMv7_OP4(0xfff0, 0x0800, 0xf910, 0x0800, T2, LDRSB_IMM),
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ARMv7_OP4(0x0e50, 0x00f0, 0x0050, 0x00d0, A1, LDRSB_IMM),
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ARMv7_OP4(0xff7f, 0x0000, 0xf91f, 0x0000, T1, LDRSB_LIT),
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ARMv7_OP4(0x0f7f, 0x00f0, 0x015f, 0x00d0, A1, LDRSB_LIT),
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ARMv7_OP2(0xfe00, 0x5600, T1, LDRSB_REG),
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ARMv7_OP4(0xfff0, 0x0fc0, 0xf910, 0x0000, T2, LDRSB_REG),
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ARMv7_OP4(0x0e50, 0x0ff0, 0x0010, 0x00d0, A1, LDRSB_REG),
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ARMv7_OP4(0xfff0, 0x0000, 0xf9b0, 0x0000, T1, LDRSH_IMM),
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ARMv7_OP4(0xfff0, 0x0800, 0xf930, 0x0800, T2, LDRSH_IMM),
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ARMv7_OP4(0x0e50, 0x00f0, 0x0050, 0x00f0, A1, LDRSH_IMM),
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ARMv7_OP4(0xff7f, 0x0000, 0xf93f, 0x0000, T1, LDRSH_LIT),
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ARMv7_OP4(0x0f7f, 0x00f0, 0x015f, 0x00f0, A1, LDRSH_LIT),
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ARMv7_OP2(0xfe00, 0x5e00, T1, LDRSH_REG),
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ARMv7_OP4(0xfff0, 0x0fc0, 0xf930, 0x0000, T2, LDRSH_REG),
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ARMv7_OP4(0x0e50, 0x0ff0, 0x0010, 0x00f0, A1, LDRSH_REG),
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ARMv7_OP2(0xf800, 0x0000, T1, LSL_IMM),
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ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0000, T2, LSL_IMM),
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ARMv7_OP4(0x0fef, 0x0070, 0x01a0, 0x0000, A1, LSL_IMM),
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ARMv7_OP2(0xffc0, 0x4080, T1, LSL_REG),
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ARMv7_OP4(0xffe0, 0xf0f0, 0xfa00, 0xf000, T2, LSL_REG),
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ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0010, A1, LSL_REG),
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ARMv7_OP2(0xf800, 0x0800, T1, LSR_IMM),
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ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0010, T2, LSR_IMM),
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ARMv7_OP4(0x0fef, 0x0030, 0x01a0, 0x0020, A1, LSR_IMM),
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ARMv7_OP2(0xffc0, 0x40c0, T1, LSR_REG),
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ARMv7_OP4(0xffe0, 0xf0f0, 0xfa20, 0xf000, T2, LSR_REG),
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ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0030, A1, LSR_REG),
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ARMv7_OP4(0xfff0, 0x00f0, 0xfb00, 0x0000, T1, MLA),
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ARMv7_OP4(0x0fe0, 0x00f0, 0x0020, 0x0090, A1, MLA),
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ARMv7_OP4(0xfff0, 0x00f0, 0xfb00, 0x0010, T1, MLS),
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ARMv7_OP4(0x0ff0, 0x00f0, 0x0060, 0x0090, A1, MLS),
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ARMv7_OP2(0xf800, 0x2000, T1, MOV_IMM),
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ARMv7_OP4(0xfbef, 0x8000, 0xf04f, 0x0000, T2, MOV_IMM),
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ARMv7_OP4(0xfbf0, 0x8000, 0xf240, 0x0000, T3, MOV_IMM),
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ARMv7_OP4(0x0fef, 0x0000, 0x03a0, 0x0000, A1, MOV_IMM),
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ARMv7_OP4(0x0ff0, 0x0000, 0x0300, 0x0000, A2, MOV_IMM),
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ARMv7_OP2(0xff00, 0x4600, T1, MOV_REG),
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ARMv7_OP2(0xffc0, 0x0000, T2, MOV_REG),
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ARMv7_OP4(0xffef, 0xf0f0, 0xea4f, 0x0000, T3, MOV_REG),
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ARMv7_OP4(0x0fef, 0x0ff0, 0x01a0, 0x0000, A1, MOV_REG),
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ARMv7_OP4(0xfbf0, 0x8000, 0xf2c0, 0x0000, T1, MOVT),
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ARMv7_OP4(0x0ff0, 0x0000, 0x0340, 0x0000, A1, MOVT),
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ARMv7_OP4(0xffff, 0xf0ff, 0xf3ef, 0x8000, T1, MRS),
|
||||
ARMv7_OP4(0x0fff, 0x0fff, 0x010f, 0x0000, A1, MRS),
|
||||
ARMv7_OP4(0x0ff3, 0xf000, 0x0320, 0xf000, A1, MSR_IMM),
|
||||
ARMv7_OP4(0xfff0, 0xf3ff, 0xf380, 0x8000, T1, MSR_REG),
|
||||
ARMv7_OP4(0x0ff3, 0xfff0, 0x0120, 0xf000, A1, MSR_REG),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0x4340, T1, MUL),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfb00, 0xf000, T2, MUL),
|
||||
ARMv7_OP4(0x0fe0, 0xf0f0, 0x0000, 0x0090, A1, MUL),
|
||||
|
||||
ARMv7_OP4(0xfbef, 0x8000, 0xf06f, 0x0000, T1, MVN_IMM),
|
||||
ARMv7_OP4(0x0fef, 0x0000, 0x03e0, 0x0000, A1, MVN_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x43c0, T1, MVN_REG),
|
||||
ARMv7_OP4(0xffef, 0x8000, 0xea6f, 0x0000, T2, MVN_REG),
|
||||
ARMv7_OP4(0xffef, 0x0010, 0x01e0, 0x0000, A1, MVN_REG),
|
||||
ARMv7_OP4(0x0fef, 0x0090, 0x01e0, 0x0010, A1, MVN_RSR),
|
||||
|
||||
ARMv7_OP2(0xffff, 0xbf00, T1, NOP),
|
||||
ARMv7_OP4(0xffff, 0xffff, 0xf3af, 0x8000, T2, NOP),
|
||||
ARMv7_OP4(0x0fff, 0xffff, 0x0320, 0xf000, A1, NOP),
|
||||
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf060, 0x0000, T1, ORN_IMM),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xea60, 0x0000, T1, ORN_REG),
|
||||
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf040, 0x0000, T1, ORR_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x0380, 0x0000, A1, ORR_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4300, T1, ORR_REG),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xea40, 0x0000, T2, ORR_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x0180, 0x0000, A1, ORR_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x0180, 0x0010, A1, ORR_RSR),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x8010, 0xeac0, 0x0000, T1, PKH),
|
||||
ARMv7_OP4(0x0ff0, 0x0030, 0x0680, 0x0010, A1, PKH),
|
||||
|
||||
ARMv7_OP2(0xfe00, 0xbc00, T1, POP),
|
||||
ARMv7_OP4(0xffff, 0x0000, 0xe8bd, 0x0000, T2, POP),
|
||||
ARMv7_OP4(0xffff, 0x0fff, 0xf85d, 0x0b04, T3, POP),
|
||||
ARMv7_OP4(0x0fff, 0x0000, 0x08bd, 0x0000, A1, POP),
|
||||
ARMv7_OP4(0x0fff, 0x0fff, 0x049d, 0x0004, A2, POP),
|
||||
|
||||
ARMv7_OP2(0xfe00, 0xb400, T1, PUSH),
|
||||
ARMv7_OP4(0xffff, 0x0000, 0xe92d, 0x0000, T2, PUSH), // had an error in arch ref
|
||||
ARMv7_OP4(0xffff, 0x0fff, 0xf84d, 0x0d04, T3, PUSH),
|
||||
ARMv7_OP4(0x0fff, 0x0000, 0x092d, 0x0000, A1, PUSH),
|
||||
ARMv7_OP4(0x0fff, 0x0fff, 0x052d, 0x0004, A2, PUSH),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf080, T1, QADD),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0100, 0x0050, A1, QADD),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf010, T1, QADD16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f10, A1, QADD16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf010, T1, QADD8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f90, A1, QADD8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf010, T1, QASX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f30, A1, QASX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf090, T1, QDADD),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0140, 0x0050, A1, QDADD),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf0b0, T1, QDSUB),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0160, 0x0050, A1, QDSUB),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf010, T1, QSAX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f50, A1, QSAX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf0a0, T1, QSUB),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0120, 0x0050, A1, QSUB),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf010, T1, QSUB16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f70, A1, QSUB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf010, T1, QSUB8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0ff0, A1, QSUB8),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf0a0, T1, RBIT),
|
||||
ARMv7_OP4(0x0fff, 0x0ff0, 0x06ff, 0x0f30, A1, RBIT),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0xba00, T1, REV),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf080, T2, REV),
|
||||
ARMv7_OP4(0x0fff, 0x0ff0, 0x06bf, 0x0f30, A1, REV),
|
||||
ARMv7_OP2(0xffc0, 0xba40, T1, REV16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf090, T2, REV16),
|
||||
ARMv7_OP4(0x0fff, 0x0ff0, 0x06bf, 0x0fb0, A1, REV16),
|
||||
ARMv7_OP2(0xffc0, 0xbac0, T1, REVSH),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf0b0, T2, REVSH),
|
||||
ARMv7_OP4(0x0fff, 0x0ff0, 0x06ff, 0x0fb0, A1, REVSH),
|
||||
|
||||
ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0030, T1, ROR_IMM),
|
||||
ARMv7_OP4(0x0fef, 0x0070, 0x01a0, 0x0060, A1, ROR_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x41c0, T1, ROR_REG),
|
||||
ARMv7_OP4(0xffe0, 0xf0f0, 0xfa60, 0xf000, T2, ROR_REG),
|
||||
ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0070, A1, ROR_REG),
|
||||
ARMv7_OP4(0xffef, 0xf0f0, 0xea4f, 0x0030, T1, RRX),
|
||||
ARMv7_OP4(0x0fef, 0x0ff0, 0x01a0, 0x0060, A1, RRX),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0x4240, T1, RSB_IMM),
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf1c0, 0x0000, T2, RSB_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x0260, 0x0000, A1, RSB_IMM),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xebc0, 0x0000, T1, RSB_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x0060, 0x0000, A1, RSB_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x0060, 0x0010, A1, RSB_RSR),
|
||||
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x02e0, 0x0000, A1, RSC_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x00e0, 0x0000, A1, RSC_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x00e0, 0x0010, A1, RSC_RSR),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf000, T1, SADD16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f10, A1, SADD16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf000, T1, SADD8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f90, A1, SADD8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf000, T1, SASX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f30, A1, SASX),
|
||||
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf160, 0x0000, T1, SBC_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x02c0, 0x0000, A1, SBC_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4180, T1, SBC_REG),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xeb60, 0x0000, T2, SBC_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x00c0, 0x0000, A1, SBC_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x00c0, 0x0010, A1, SBC_RSR),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x8020, 0xf340, 0x0000, T1, SBFX),
|
||||
ARMv7_OP4(0x0fe0, 0x0070, 0x07a0, 0x0050, A1, SBFX),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfb90, 0xf0f0, T1, SDIV), // ???
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf080, T1, SEL),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0680, 0x0fb0, A1, SEL),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf020, T1, SHADD16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f10, A1, SHADD16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf020, T1, SHADD8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f90, A1, SHADD8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf020, T1, SHASX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f30, A1, SHASX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf020, T1, SHSAX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f50, A1, SHSAX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf020, T1, SHSUB16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f70, A1, SHSUB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf020, T1, SHSUB8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0ff0, A1, SHSUB8),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x00c0, 0xfb10, 0x0000, T1, SMLA__),
|
||||
ARMv7_OP4(0x0ff0, 0x0090, 0x0100, 0x0080, A1, SMLA__),
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfb20, 0x0000, T1, SMLAD),
|
||||
ARMv7_OP4(0x0ff0, 0x00d0, 0x0700, 0x0010, A1, SMLAD),
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfbc0, 0x0000, T1, SMLAL),
|
||||
ARMv7_OP4(0x0fe0, 0x00f0, 0x00e0, 0x0090, A1, SMLAL),//???
|
||||
ARMv7_OP4(0xfff0, 0x00c0, 0xfbc0, 0x0080, T1, SMLAL__),
|
||||
ARMv7_OP4(0x0ff0, 0x0090, 0x0140, 0x0080, A1, SMLAL__),
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfbc0, 0x00c0, T1, SMLALD),
|
||||
ARMv7_OP4(0x0ff0, 0x00d0, 0x0740, 0x0010, A1, SMLALD),
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfb30, 0x0000, T1, SMLAW_),
|
||||
ARMv7_OP4(0x0ff0, 0x00b0, 0x0120, 0x0080, A1, SMLAW_),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfb40, 0x0000, T1, SMLSD),
|
||||
ARMv7_OP4(0x0ff0, 0x00d0, 0x0700, 0x0050, A1, SMLSD),
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfbd0, 0x00c0, T1, SMLSLD),
|
||||
ARMv7_OP4(0x0ff0, 0x00d0, 0x0740, 0x0050, A1, SMLSLD),
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfb50, 0x0000, T1, SMMLA),
|
||||
ARMv7_OP4(0x0ff0, 0x00d0, 0x0750, 0x0010, A1, SMMLA),
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfb60, 0x0000, T1, SMMLS),
|
||||
ARMv7_OP4(0x0ff0, 0x00d0, 0x0750, 0x00d0, A1, SMMLS),
|
||||
ARMv7_OP4(0xfff0, 0xf0e0, 0xfb50, 0xf000, T1, SMMUL),
|
||||
ARMv7_OP4(0x0ff0, 0xf0d0, 0x0750, 0xf010, A1, SMMUL),
|
||||
ARMv7_OP4(0xfff0, 0xf0e0, 0xfb20, 0xf000, T1, SMUAD),
|
||||
ARMv7_OP4(0x0ff0, 0xf0d0, 0x0700, 0xf010, A1, SMUAD),
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfb10, 0xf000, T1, SMUL__),
|
||||
ARMv7_OP4(0x0ff0, 0xf090, 0x0160, 0x0080, A1, SMUL__),//???
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfb80, 0x0000, T1, SMULL),
|
||||
ARMv7_OP4(0x0fe0, 0x00f0, 0x00c0, 0x0090, A1, SMULL),
|
||||
ARMv7_OP4(0xfff0, 0xf0e0, 0xfb30, 0xf000, T1, SMULW_),
|
||||
ARMv7_OP4(0x0ff0, 0xf0b0, 0x0120, 0x00a0, A1, SMULW_),//???
|
||||
ARMv7_OP4(0xfff0, 0xf0e0, 0xfb40, 0xf000, T1, SMUSD),
|
||||
ARMv7_OP4(0x0ff0, 0xf0d0, 0x0700, 0xf050, A1, SMUSD),
|
||||
ARMv7_OP4(0xffd0, 0x8020, 0xf300, 0x0000, T1, SSAT),
|
||||
ARMv7_OP4(0x0fe0, 0x0030, 0x06a0, 0x0010, A1, SSAT),
|
||||
ARMv7_OP4(0xfff0, 0xf0e0, 0xf320, 0x0000, T1, SSAT16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x06a0, 0x0f30, A1, SSAT16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf000, T1, SSAX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f50, A1, SSAX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf000, T1, SSUB16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f70, A1, SSUB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf000, T1, SSUB8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0ff0, A1, SSUB8),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x0000, 0xe840, 0x0000, T1, STREX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0180, 0x0f90, A1, STREX),
|
||||
ARMv7_OP4(0xfff0, 0x0ff0, 0xe8c0, 0x0f40, T1, STREXB),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x01c0, 0x0f90, A1, STREXB),
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xe8c0, 0x0070, T1, STREXD),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x01a0, 0x0f90, A1, STREXD),
|
||||
ARMv7_OP4(0xfff0, 0x0ff0, 0xe8c0, 0x0f50, T1, STREXH),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x01e0, 0x0f90, A1, STREXH),
|
||||
|
||||
ARMv7_OP2(0xf800, 0xc000, T1, STM),
|
||||
ARMv7_OP4(0xffd0, 0xa000, 0xe880, 0x0000, T2, STM),
|
||||
ARMv7_OP4(0x0fd0, 0x0000, 0x0880, 0x0000, A1, STM),
|
||||
ARMv7_OP4(0x0fd0, 0x0000, 0x0800, 0x0000, A1, STMDA),
|
||||
ARMv7_OP4(0xffd0, 0xa000, 0xe900, 0x0000, T1, STMDB),
|
||||
ARMv7_OP4(0x0fd0, 0x0000, 0x0900, 0x0000, A1, STMDB),
|
||||
ARMv7_OP4(0x0fd0, 0x0000, 0x0980, 0x0000, A1, STMIB),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x6000, T1, STR_IMM),
|
||||
ARMv7_OP2(0xf800, 0x9000, T2, STR_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0000, 0xf8c0, 0x0000, T3, STR_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0800, 0xf840, 0x0800, T4, STR_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x0000, 0x0400, 0x0000, A1, STR_IMM),
|
||||
ARMv7_OP2(0xfe00, 0x5000, T1, STR_REG),
|
||||
ARMv7_OP4(0xfff0, 0x0fc0, 0xf840, 0x0000, T2, STR_REG),
|
||||
ARMv7_OP4(0x0e50, 0x0010, 0x0600, 0x0000, A1, STR_REG),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x7000, T1, STRB_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0000, 0xf880, 0x0000, T2, STRB_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0800, 0xf800, 0x0800, T3, STRB_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x0000, 0x0440, 0x0000, A1, STRB_IMM),
|
||||
ARMv7_OP2(0xfe00, 0x5400, T1, STRB_REG),
|
||||
ARMv7_OP4(0xfff0, 0x0fc0, 0xf800, 0x0000, T2, STRB_REG),
|
||||
ARMv7_OP4(0x0e50, 0x0010, 0x0640, 0x0000, A1, STRB_REG),
|
||||
|
||||
ARMv7_OP4(0xfe50, 0x0000, 0xe840, 0x0000, T1, STRD_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x00f0, 0x0040, 0x00f0, A1, STRD_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x0ff0, 0x0000, 0x00f0, A1, STRD_REG),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x8000, T1, STRH_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0000, 0xf8a0, 0x0000, T2, STRH_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0800, 0xf820, 0x0800, T3, STRH_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x00f0, 0x0040, 0x00b0, A1, STRH_IMM),
|
||||
ARMv7_OP2(0xfe00, 0x5200, T1, STRH_REG),
|
||||
ARMv7_OP4(0xfff0, 0x0fc0, 0xf820, 0x0000, T2, STRH_REG),
|
||||
ARMv7_OP4(0x0e50, 0x0ff0, 0x0000, 0x00b0, A1, STRH_REG),
|
||||
|
||||
ARMv7_OP2(0xff80, 0xb080, T1, SUB_SPI),
|
||||
ARMv7_OP4(0xfbef, 0x8000, 0xf1ad, 0x0000, T2, SUB_SPI),
|
||||
ARMv7_OP4(0xfbff, 0x8000, 0xf2ad, 0x0000, T3, SUB_SPI),
|
||||
ARMv7_OP4(0x0fef, 0x0000, 0x024d, 0x0000, A1, SUB_SPI),
|
||||
ARMv7_OP4(0xffef, 0x8000, 0xebad, 0x0000, T1, SUB_SPR),
|
||||
ARMv7_OP4(0x0fef, 0x0010, 0x004d, 0x0000, A1, SUB_SPR),
|
||||
ARMv7_OP2(0xfe00, 0x1e00, T1, SUB_IMM),
|
||||
ARMv7_OP2(0xf800, 0x3800, T2, SUB_IMM),
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf1a0, 0x0000, T3, SUB_IMM),
|
||||
ARMv7_OP4(0xfbf0, 0x8000, 0xf2a0, 0x0000, T4, SUB_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x0240, 0x0000, A1, SUB_IMM),
|
||||
ARMv7_OP2(0xfe00, 0x1a00, T1, SUB_REG),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xeba0, 0x0000, T2, SUB_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x0040, 0x0000, A1, SUB_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x0040, 0x0010, A1, SUB_RSR),
|
||||
|
||||
ARMv7_OP2(0xff00, 0xdf00, T1, SVC),
|
||||
ARMv7_OP4(0x0f00, 0x0000, 0x0f00, 0x0000, A1, SVC),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfa40, 0xf080, T1, SXTAB),
|
||||
ARMv7_OP4(0x0ff0, 0x03f0, 0x06a0, 0x0070, A1, SXTAB),
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfa20, 0xf080, T1, SXTAB16),
|
||||
ARMv7_OP4(0x0ff0, 0x03f0, 0x0680, 0x0070, A1, SXTAB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfa00, 0xf080, T1, SXTAH),
|
||||
ARMv7_OP4(0x0ff0, 0x03f0, 0x06b0, 0x0070, A1, SXTAH),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0xb240, T1, SXTB),
|
||||
ARMv7_OP4(0xffff, 0xf0c0, 0xfa4f, 0xf080, T2, SXTB),
|
||||
ARMv7_OP4(0x0fff, 0x03f0, 0x06af, 0x0070, A1, SXTB),
|
||||
|
||||
ARMv7_OP4(0xffff, 0xf0c0, 0xfa2f, 0xf080, T1, SXTB16),
|
||||
ARMv7_OP4(0x0fff, 0x03f0, 0x068f, 0x0070, A1, SXTB16),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0xb200, T1, SXTH),
|
||||
ARMv7_OP4(0xffff, 0xf0c0, 0xfa0f, 0xf080, T2, SXTH),
|
||||
ARMv7_OP4(0x0fff, 0x03f0, 0x06bf, 0x0070, A1, SXTH),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xffe0, 0xe8d0, 0xf000, T1, TB_),
|
||||
|
||||
ARMv7_OP4(0xfbf0, 0x8f00, 0xf090, 0x0f00, T1, TEQ_IMM),
|
||||
ARMv7_OP4(0x0ff0, 0xf000, 0x0330, 0x0000, A1, TEQ_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x8f00, 0xea90, 0x0f00, T1, TEQ_REG),
|
||||
ARMv7_OP4(0x0ff0, 0xf010, 0x0130, 0x0000, A1, TEQ_REG),
|
||||
ARMv7_OP4(0x0ff0, 0xf090, 0x0130, 0x0010, A1, TEQ_RSR),
|
||||
|
||||
ARMv7_OP4(0xfbf0, 0x8f00, 0xf010, 0x0f00, T1, TST_IMM),
|
||||
ARMv7_OP4(0x0ff0, 0xf000, 0x0310, 0x0000, A1, TST_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4200, T1, TST_REG),
|
||||
ARMv7_OP4(0xfff0, 0x8f00, 0xea10, 0x0f00, T2, TST_REG),
|
||||
ARMv7_OP4(0x0ff0, 0xf010, 0x0110, 0x0000, A1, TST_REG),
|
||||
ARMv7_OP4(0x0ff0, 0xf090, 0x0110, 0x0010, A1, TST_RSR),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf040, T1, UADD16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f10, A1, UADD16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf040, T1, UADD8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f90, A1, UADD8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf040, T1, UASX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f30, A1, UASX),
|
||||
ARMv7_OP4(0xfff0, 0x8020, 0xf3c0, 0x0000, T1, UBFX),
|
||||
ARMv7_OP4(0x0fe0, 0x0070, 0x07e0, 0x0050, A1, UBFX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfbb0, 0xf0f0, T1, UDIV),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf060, T1, UHADD16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f10, A1, UHADD16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf060, T1, UHADD8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f90, A1, UHADD8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf060, T1, UHASX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f30, A1, UHASX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf060, T1, UHSAX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f50, A1, UHSAX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf060, T1, UHSUB16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f70, A1, UHSUB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf060, T1, UHSUB8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0ff0, A1, UHSUB8),
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfbe0, 0x0060, T1, UMAAL),
|
||||
ARMv7_OP4(0x0ff0, 0x00f0, 0x0040, 0x0090, A1, UMAAL),
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfbe0, 0x0000, T1, UMLAL),
|
||||
ARMv7_OP4(0x0fe0, 0x00f0, 0x00a0, 0x0090, A1, UMLAL),
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfba0, 0x0000, T1, UMULL),
|
||||
ARMv7_OP4(0x0fe0, 0x00f0, 0x0080, 0x0090, A1, UMULL),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf050, T1, UQADD16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f10, A1, UQADD16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf050, T1, UQADD8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f90, A1, UQADD8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf050, T1, UQASX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f30, A1, UQASX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf050, T1, UQSAX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f50, A1, UQSAX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf050, T1, UQSUB16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f70, A1, UQSUB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf050, T1, UQSUB8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0ff0, A1, UQSUB8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfb70, 0xf000, T1, USAD8),
|
||||
ARMv7_OP4(0x0ff0, 0xf0f0, 0x0780, 0xf010, A1, USAD8),
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfb70, 0x0000, T1, USADA8),
|
||||
ARMv7_OP4(0x0ff0, 0x00f0, 0x0780, 0x0010, A1, USADA8),
|
||||
ARMv7_OP4(0xffd0, 0x8020, 0xf380, 0x0000, T1, USAT),
|
||||
ARMv7_OP4(0x0fe0, 0x0030, 0x06e0, 0x0010, A1, USAT),
|
||||
ARMv7_OP4(0xfff0, 0xf0e0, 0xf3a0, 0x0000, T1, USAT16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x06e0, 0x0f30, A1, USAT16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf040, T1, USAX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f50, A1, USAX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf040, T1, USUB16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f70, A1, USUB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf040, T1, USUB8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0ff0, A1, USUB8),
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfa50, 0xf080, T1, UXTAB),
|
||||
ARMv7_OP4(0x0ff0, 0x03f0, 0x06e0, 0x0070, A1, UXTAB),
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfa30, 0xf080, T1, UXTAB16),
|
||||
ARMv7_OP4(0x0ff0, 0x03f0, 0x06c0, 0x0070, A1, UXTAB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfa10, 0xf080, T1, UXTAH),
|
||||
ARMv7_OP4(0x0ff0, 0x03f0, 0x06f0, 0x0070, A1, UXTAH),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0xb2c0, T1, UXTB),
|
||||
ARMv7_OP4(0xffff, 0xf0c0, 0xfa5f, 0xf080, T2, UXTB),
|
||||
ARMv7_OP4(0x0fff, 0x03f0, 0x06ef, 0x0070, A1, UXTB),
|
||||
|
||||
ARMv7_OP4(0xffff, 0xf0c0, 0xfa3f, 0xf080, T1, UXTB16),
|
||||
ARMv7_OP4(0x0fff, 0x03f0, 0x06cf, 0x0070, A1, UXTB16),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0xb280, T1, UXTH),
|
||||
ARMv7_OP4(0xffff, 0xf0c0, 0xfa1f, 0xf080, T2, UXTH),
|
||||
ARMv7_OP4(0x0fff, 0x03f0, 0x06ff, 0x0070, A1, UXTH),
|
||||
|
||||
ARMv7_OP4(0xef80, 0x0f10, 0xef00, 0x0710, T1, VABA_),
|
||||
ARMv7_OP4(0xfe80, 0x0f10, 0xf200, 0x0710, A1, VABA_),
|
||||
ARMv7_OP4(0xef80, 0x0f50, 0xef80, 0x0500, T2, VABA_),
|
||||
ARMv7_OP4(0xfe80, 0x0f50, 0xf280, 0x0500, A2, VABA_),
|
||||
|
||||
// TODO: vector instructions
|
||||
|
||||
ARMv7_OP2(0xffff, 0xbf20, T1, WFE),
|
||||
ARMv7_OP4(0xffff, 0xffff, 0xf3af, 0x8002, T2, WFE),
|
||||
ARMv7_OP4(0x0fff, 0xffff, 0x0320, 0xf002, A1, WFE),
|
||||
ARMv7_OP2(0xffff, 0xbf30, T1, WFI),
|
||||
ARMv7_OP4(0xffff, 0xffff, 0xf3af, 0x8003, T2, WFI),
|
||||
ARMv7_OP4(0x0fff, 0xffff, 0x0320, 0xf003, A1, WFI),
|
||||
ARMv7_OP2(0xffff, 0xbf10, T1, YIELD),
|
||||
ARMv7_OP4(0xffff, 0xffff, 0xf3af, 0x8001, T2, YIELD),
|
||||
ARMv7_OP4(0x0fff, 0xffff, 0x0320, 0xf001, A1, YIELD),
|
||||
};
|
||||
|
||||
u8 ARMv7Decoder::DecodeMemory(const u32 address)
|
||||
{
|
||||
ARMv7Code code;
|
||||
code.code0 = vm::psv::read16(address & ~1);
|
||||
code.code1 = vm::psv::read16(address + 2 & ~1);
|
||||
u32 arg = address & 0x1 ? code.data : (u32)code.code0 << 16 | code.code1;
|
||||
|
||||
//LOG_NOTICE(GENERAL, "code0 = 0x%04x, code1 = 0x%04x, data = 0x%08x, arg = 0x%08x", code.code0, code.code1, code.data, arg);
|
||||
|
||||
// old decoding algorithm
|
||||
|
||||
for (auto& opcode : ARMv7_opcode_table)
|
||||
{
|
||||
if ((opcode.type < A1) == ((address & 0x1) == 0) && (arg & opcode.mask) == opcode.code)
|
||||
{
|
||||
code.data = opcode.length == 2 ? code.code0 : arg;
|
||||
(*opcode.func)(m_thr.context, code, opcode.type);
|
||||
//LOG_NOTICE(ARMv7, "%s, %s", opcode.name, m_thr.RegsToString());
|
||||
return opcode.length;
|
||||
}
|
||||
}
|
||||
|
||||
ARMv7_instrs::UNK(m_thr.context, code);
|
||||
return address & 0x1 ? 4 : 2;
|
||||
|
||||
|
||||
//execute_main_group(&m_thr);
|
||||
//// LOG_NOTICE(GENERAL, "%s, %d \n\n", m_thr.m_last_instr_name, m_thr.m_last_instr_size);
|
||||
//m_thr.m_last_instr_name = "Unknown";
|
||||
//return m_thr.m_last_instr_size;
|
||||
}
|
||||
@ -1,10 +1,7 @@
|
||||
#pragma once
|
||||
|
||||
#include "Emu/CPU/CPUDecoder.h"
|
||||
#include "ARMv7Thread.h"
|
||||
#include "ARMv7Interpreter.h"
|
||||
#include "ARMv7Opcodes.h"
|
||||
#include "Utilities/Log.h"
|
||||
|
||||
class ARMv7Thread;
|
||||
|
||||
class ARMv7Decoder : public CPUDecoder
|
||||
{
|
||||
@ -15,35 +12,5 @@ public:
|
||||
{
|
||||
}
|
||||
|
||||
virtual u8 DecodeMemory(const u32 address)
|
||||
{
|
||||
ARMv7Code code;
|
||||
code.code0 = vm::psv::read16(address & ~1);
|
||||
code.code1 = vm::psv::read16(address + 2 & ~1);
|
||||
u32 arg = address & 0x1 ? code.data : (u32)code.code0 << 16 | code.code1;
|
||||
|
||||
//LOG_NOTICE(GENERAL, "code0 = 0x%04x, code1 = 0x%04x, data = 0x%08x, arg = 0x%08x", code.code0, code.code1, code.data, arg);
|
||||
|
||||
// old decoding algorithm
|
||||
|
||||
for (auto& opcode : ARMv7_opcode_table)
|
||||
{
|
||||
if ((opcode.type < A1) == ((address & 0x1) == 0) && (arg & opcode.mask) == opcode.code)
|
||||
{
|
||||
code.data = opcode.length == 2 ? code.code0 : arg;
|
||||
(*opcode.func)(m_thr.context, code, opcode.type);
|
||||
//LOG_NOTICE(ARMv7, "%s, %s", opcode.name, m_thr.RegsToString());
|
||||
return opcode.length;
|
||||
}
|
||||
}
|
||||
|
||||
ARMv7_instrs::UNK(m_thr.context, code);
|
||||
return address & 0x1 ? 4 : 2;
|
||||
|
||||
|
||||
//execute_main_group(&m_thr);
|
||||
//// LOG_NOTICE(GENERAL, "%s, %d \n\n", m_thr.m_last_instr_name, m_thr.m_last_instr_size);
|
||||
//m_thr.m_last_instr_name = "Unknown";
|
||||
//return m_thr.m_last_instr_size;
|
||||
}
|
||||
};
|
||||
virtual u8 DecodeMemory(const u32 address);
|
||||
};
|
||||
|
||||
@ -516,600 +516,3 @@ namespace ARMv7_instrs
|
||||
void WFI(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type);
|
||||
void YIELD(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type);
|
||||
};
|
||||
|
||||
|
||||
// old instructions table for debugging and information, delete this later
|
||||
using namespace ARMv7_instrs;
|
||||
|
||||
struct ARMv7_opcode_t
|
||||
{
|
||||
u32 mask;
|
||||
u32 code;
|
||||
u32 length; // 2 or 4
|
||||
const char* name;
|
||||
ARMv7_encoding type;
|
||||
void(*func)(ARMv7Context& context, const ARMv7Code code, const ARMv7_encoding type);
|
||||
};
|
||||
|
||||
// single 16-bit value
|
||||
#define ARMv7_OP2(mask, code, type, name) { (u32)((mask) << 16), (u32)((code) << 16), 2, #name "_" #type, type, name }
|
||||
// two 16-bit values
|
||||
#define ARMv7_OP4(mask0, mask1, code0, code1, type, name) { (u32)((mask0) << 16) | (mask1), (u32)((code0) << 16) | (code1), 4, #name "_" #type, type, name }
|
||||
|
||||
static const ARMv7_opcode_t ARMv7_opcode_table[] =
|
||||
{
|
||||
ARMv7_OP2(0xffff, 0x0000, T1, NULL_OP), // ???
|
||||
|
||||
ARMv7_OP4(0xffff, 0x0000, 0xf870, 0x0000, T1, HACK), // "Undefined" Thumb opcode
|
||||
ARMv7_OP4(0x0ff0, 0x00f0, 0x0070, 0x0090, A1, HACK), // "Undefined" ARM opcode
|
||||
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf140, 0x0000, T1, ADC_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x02a0, 0x0000, A1, ADC_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4040, T1, ADC_REG),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xeb40, 0x0000, T2, ADC_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x00a0, 0x0000, A1, ADC_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x00a0, 0x0010, A1, ADC_RSR),
|
||||
|
||||
ARMv7_OP2(0xf800, 0xa800, T1, ADD_SPI),
|
||||
ARMv7_OP2(0xff80, 0xb000, T2, ADD_SPI),
|
||||
ARMv7_OP4(0xfbef, 0x8000, 0xf10d, 0x0000, T3, ADD_SPI),
|
||||
ARMv7_OP4(0xfbff, 0x8000, 0xf20d, 0x0000, T4, ADD_SPI),
|
||||
ARMv7_OP4(0x0fef, 0x0000, 0x028d, 0x0000, A1, ADD_SPI),
|
||||
ARMv7_OP2(0xff78, 0x4468, T1, ADD_SPR),
|
||||
ARMv7_OP2(0xff87, 0x4485, T2, ADD_SPR),
|
||||
ARMv7_OP4(0xffef, 0x8000, 0xeb0d, 0x0000, T3, ADD_SPR),
|
||||
ARMv7_OP4(0x0fef, 0x0010, 0x008d, 0x0000, A1, ADD_SPR),
|
||||
ARMv7_OP2(0xfe00, 0x1c00, T1, ADD_IMM),
|
||||
ARMv7_OP2(0xf800, 0x3000, T2, ADD_IMM),
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf100, 0x0000, T3, ADD_IMM),
|
||||
ARMv7_OP4(0xfbf0, 0x8000, 0xf200, 0x0000, T4, ADD_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x0280, 0x0000, A1, ADD_IMM),
|
||||
ARMv7_OP2(0xfe00, 0x1800, T1, ADD_REG),
|
||||
ARMv7_OP2(0xff00, 0x4400, T2, ADD_REG),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xeb00, 0x0000, T3, ADD_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x0080, 0x0000, A1, ADD_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x0080, 0x0010, A1, ADD_RSR),
|
||||
|
||||
ARMv7_OP2(0xf800, 0xa000, T1, ADR),
|
||||
ARMv7_OP4(0xfbff, 0x8000, 0xf2af, 0x0000, T2, ADR),
|
||||
ARMv7_OP4(0xfbff, 0x8000, 0xf20f, 0x0000, T3, ADR),
|
||||
ARMv7_OP4(0x0fff, 0x0000, 0x028f, 0x0000, A1, ADR),
|
||||
ARMv7_OP4(0x0fff, 0x0000, 0x024f, 0x0000, A2, ADR),
|
||||
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf000, 0x0000, T1, AND_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x0200, 0x0000, A1, AND_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4000, T1, AND_REG),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xea00, 0x0000, T2, AND_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x0000, 0x0000, A1, AND_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x0000, 0x0010, A1, AND_RSR),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x1000, T1, ASR_IMM),
|
||||
ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0020, T2, ASR_IMM),
|
||||
ARMv7_OP4(0x0fef, 0x0070, 0x01a0, 0x0040, A1, ASR_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4100, T1, ASR_REG),
|
||||
ARMv7_OP4(0xffe0, 0xf0f0, 0xfa40, 0xf000, T2, ASR_REG),
|
||||
ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0050, A1, ASR_REG),
|
||||
|
||||
ARMv7_OP2(0xf000, 0xd000, T1, B),
|
||||
ARMv7_OP2(0xf800, 0xe000, T2, B),
|
||||
ARMv7_OP4(0xf800, 0xd000, 0xf000, 0x8000, T3, B),
|
||||
ARMv7_OP4(0xf800, 0xd000, 0xf000, 0x9000, T4, B),
|
||||
ARMv7_OP4(0x0f00, 0x0000, 0x0a00, 0x0000, A1, B),
|
||||
|
||||
ARMv7_OP4(0xffff, 0x8020, 0xf36f, 0x0000, T1, BFC),
|
||||
ARMv7_OP4(0x0fe0, 0x007f, 0x07c0, 0x001f, A1, BFC),
|
||||
ARMv7_OP4(0xfff0, 0x8020, 0xf360, 0x0000, T1, BFI),
|
||||
ARMv7_OP4(0x0fe0, 0x0070, 0x07c0, 0x0010, A1, BFI),
|
||||
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf020, 0x0000, T1, BIC_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x03c0, 0x0000, A1, BIC_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4380, T1, BIC_REG),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xea20, 0x0000, T2, BIC_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x01c0, 0x0000, A1, BIC_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x01c0, 0x0010, A1, BIC_RSR),
|
||||
|
||||
ARMv7_OP2(0xff00, 0xbe00, T1, BKPT),
|
||||
ARMv7_OP4(0x0ff0, 0x00f0, 0x0120, 0x0070, A1, BKPT),
|
||||
|
||||
ARMv7_OP4(0xf800, 0xd000, 0xf000, 0xd000, T1, BL),
|
||||
ARMv7_OP4(0x0f00, 0x0000, 0x0b00, 0x0000, A1, BL),
|
||||
ARMv7_OP2(0xff80, 0x4780, T1, BLX),
|
||||
ARMv7_OP4(0xf800, 0xc001, 0xf000, 0xc000, T2, BLX),
|
||||
ARMv7_OP4(0x0fff, 0xfff0, 0x012f, 0xff30, A1, BLX),
|
||||
ARMv7_OP4(0xfe00, 0x0000, 0xfa00, 0x0000, A2, BLX),
|
||||
|
||||
ARMv7_OP2(0xff87, 0x4700, T1, BX),
|
||||
ARMv7_OP4(0x0fff, 0xfff0, 0x012f, 0xff10, A1, BX),
|
||||
|
||||
ARMv7_OP2(0xf500, 0xb100, T1, CB_Z),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfab0, 0xf080, T1, CLZ),
|
||||
ARMv7_OP4(0x0fff, 0x0ff0, 0x016f, 0x0f10, A1, CLZ),
|
||||
|
||||
ARMv7_OP4(0xfbf0, 0x8f00, 0xf110, 0x0f00, T1, CMN_IMM),
|
||||
ARMv7_OP4(0x0ff0, 0xf000, 0x0370, 0x0000, A1, CMN_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x42c0, T1, CMN_REG),
|
||||
ARMv7_OP4(0xfff0, 0x8f00, 0xeb10, 0x0f00, T2, CMN_REG),
|
||||
ARMv7_OP4(0x0ff0, 0xf010, 0x0170, 0x0000, A1, CMN_REG),
|
||||
ARMv7_OP4(0x0ff0, 0xf090, 0x0170, 0x0010, A1, CMN_RSR),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x2800, T1, CMP_IMM),
|
||||
ARMv7_OP4(0xfbf0, 0x8f00, 0xf1b0, 0x0f00, T2, CMP_IMM),
|
||||
ARMv7_OP4(0x0ff0, 0xf000, 0x0350, 0x0000, A1, CMP_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4280, T1, CMP_REG),
|
||||
ARMv7_OP2(0xff00, 0x4500, T2, CMP_REG),
|
||||
ARMv7_OP4(0xfff0, 0x8f00, 0xebb0, 0x0f00, T3, CMP_REG),
|
||||
ARMv7_OP4(0x0ff0, 0xf010, 0x0150, 0x0000, A1, CMP_REG),
|
||||
ARMv7_OP4(0x0ff0, 0xf090, 0x0150, 0x0010, A1, CMP_RSR),
|
||||
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf080, 0x0000, T1, EOR_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x0220, 0x0000, A1, EOR_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4040, T1, EOR_REG),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xea80, 0x0000, T2, EOR_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x0020, 0x0000, A1, EOR_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x0020, 0x0010, A1, EOR_RSR),
|
||||
|
||||
ARMv7_OP2(0xff00, 0xbf00, T1, IT),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x0f00, 0xe850, 0x0f00, T1, LDREX),
|
||||
ARMv7_OP4(0x0ff0, 0x0fff, 0x0190, 0x0f9f, A1, LDREX),
|
||||
ARMv7_OP4(0xfff0, 0x0fff, 0xe8d0, 0x0f4f, T1, LDREXB),
|
||||
ARMv7_OP4(0x0ff0, 0x0fff, 0x01d0, 0x0f9f, A1, LDREXB),
|
||||
ARMv7_OP4(0xfff0, 0x00ff, 0xe8d0, 0x007f, T1, LDREXD),
|
||||
ARMv7_OP4(0x0ff0, 0x0fff, 0x01b0, 0x0f9f, A1, LDREXD),
|
||||
ARMv7_OP4(0xfff0, 0x0fff, 0xe8d0, 0x0f5f, T1, LDREXH),
|
||||
ARMv7_OP4(0x0ff0, 0x0fff, 0x01f0, 0x0f9f, A1, LDREXH),
|
||||
|
||||
ARMv7_OP2(0xf800, 0xc800, T1, LDM),
|
||||
ARMv7_OP4(0xffd0, 0x2000, 0xe890, 0x0000, T2, LDM),
|
||||
ARMv7_OP4(0x0fd0, 0x0000, 0x0890, 0x0000, A1, LDM),
|
||||
ARMv7_OP4(0x0fd0, 0x0000, 0x0810, 0x0000, A1, LDMDA),
|
||||
ARMv7_OP4(0xffd0, 0x2000, 0xe910, 0x0000, T1, LDMDB),
|
||||
ARMv7_OP4(0x0fd0, 0x0000, 0x0910, 0x0000, A1, LDMDB),
|
||||
ARMv7_OP4(0x0fd0, 0x0000, 0x0990, 0x0000, A1, LDMIB),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x6800, T1, LDR_IMM),
|
||||
ARMv7_OP2(0xf800, 0x9800, T2, LDR_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0000, 0xf8d0, 0x0000, T3, LDR_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0800, 0xf850, 0x0800, T4, LDR_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x0000, 0x0410, 0x0000, A1, LDR_IMM),
|
||||
ARMv7_OP2(0xf800, 0x4800, T1, LDR_LIT),
|
||||
ARMv7_OP4(0xff7f, 0x0000, 0xf85f, 0x0000, T2, LDR_LIT),
|
||||
ARMv7_OP4(0x0f7f, 0x0000, 0x051f, 0x0000, A1, LDR_LIT),
|
||||
ARMv7_OP2(0xfe00, 0x5800, T1, LDR_REG),
|
||||
ARMv7_OP4(0xfff0, 0x0fc0, 0xf850, 0x0000, T2, LDR_REG),
|
||||
ARMv7_OP4(0x0e50, 0x0010, 0x0610, 0x0000, A1, LDR_REG),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x7800, T1, LDRB_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0000, 0xf890, 0x0000, T2, LDRB_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0800, 0xf810, 0x0800, T3, LDRB_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x0000, 0x0450, 0x0000, A1, LDRB_IMM),
|
||||
ARMv7_OP4(0xff7f, 0x0000, 0xf81f, 0x0000, T1, LDRB_LIT),
|
||||
ARMv7_OP4(0x0f7f, 0x0000, 0x055f, 0x0000, A1, LDRB_LIT),
|
||||
ARMv7_OP2(0xfe00, 0x5c00, T1, LDRB_REG),
|
||||
ARMv7_OP4(0xfff0, 0x0fc0, 0xf810, 0x0000, T2, LDRB_REG),
|
||||
ARMv7_OP4(0x0e50, 0x0010, 0x0650, 0x0000, A1, LDRB_REG),
|
||||
|
||||
ARMv7_OP4(0xfe50, 0x0000, 0xe850, 0x0000, T1, LDRD_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x00f0, 0x0040, 0x00d0, A1, LDRD_IMM),
|
||||
ARMv7_OP4(0xfe7f, 0x0000, 0xe85f, 0x0000, T1, LDRD_LIT),
|
||||
ARMv7_OP4(0x0f7f, 0x00f0, 0x014f, 0x00d0, A1, LDRD_LIT),
|
||||
ARMv7_OP4(0x0e50, 0x0ff0, 0x0000, 0x00d0, A1, LDRD_REG),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x0000, 0xf990, 0x0000, T1, LDRSB_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0800, 0xf910, 0x0800, T2, LDRSB_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x00f0, 0x0050, 0x00d0, A1, LDRSB_IMM),
|
||||
ARMv7_OP4(0xff7f, 0x0000, 0xf91f, 0x0000, T1, LDRSB_LIT),
|
||||
ARMv7_OP4(0x0f7f, 0x00f0, 0x015f, 0x00d0, A1, LDRSB_LIT),
|
||||
ARMv7_OP2(0xfe00, 0x5600, T1, LDRSB_REG),
|
||||
ARMv7_OP4(0xfff0, 0x0fc0, 0xf910, 0x0000, T2, LDRSB_REG),
|
||||
ARMv7_OP4(0x0e50, 0x0ff0, 0x0010, 0x00d0, A1, LDRSB_REG),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x0000, 0xf9b0, 0x0000, T1, LDRSH_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0800, 0xf930, 0x0800, T2, LDRSH_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x00f0, 0x0050, 0x00f0, A1, LDRSH_IMM),
|
||||
ARMv7_OP4(0xff7f, 0x0000, 0xf93f, 0x0000, T1, LDRSH_LIT),
|
||||
ARMv7_OP4(0x0f7f, 0x00f0, 0x015f, 0x00f0, A1, LDRSH_LIT),
|
||||
ARMv7_OP2(0xfe00, 0x5e00, T1, LDRSH_REG),
|
||||
ARMv7_OP4(0xfff0, 0x0fc0, 0xf930, 0x0000, T2, LDRSH_REG),
|
||||
ARMv7_OP4(0x0e50, 0x0ff0, 0x0010, 0x00f0, A1, LDRSH_REG),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x0000, T1, LSL_IMM),
|
||||
ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0000, T2, LSL_IMM),
|
||||
ARMv7_OP4(0x0fef, 0x0070, 0x01a0, 0x0000, A1, LSL_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4080, T1, LSL_REG),
|
||||
ARMv7_OP4(0xffe0, 0xf0f0, 0xfa00, 0xf000, T2, LSL_REG),
|
||||
ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0010, A1, LSL_REG),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x0800, T1, LSR_IMM),
|
||||
ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0010, T2, LSR_IMM),
|
||||
ARMv7_OP4(0x0fef, 0x0030, 0x01a0, 0x0020, A1, LSR_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x40c0, T1, LSR_REG),
|
||||
ARMv7_OP4(0xffe0, 0xf0f0, 0xfa20, 0xf000, T2, LSR_REG),
|
||||
ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0030, A1, LSR_REG),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfb00, 0x0000, T1, MLA),
|
||||
ARMv7_OP4(0x0fe0, 0x00f0, 0x0020, 0x0090, A1, MLA),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfb00, 0x0010, T1, MLS),
|
||||
ARMv7_OP4(0x0ff0, 0x00f0, 0x0060, 0x0090, A1, MLS),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x2000, T1, MOV_IMM),
|
||||
ARMv7_OP4(0xfbef, 0x8000, 0xf04f, 0x0000, T2, MOV_IMM),
|
||||
ARMv7_OP4(0xfbf0, 0x8000, 0xf240, 0x0000, T3, MOV_IMM),
|
||||
ARMv7_OP4(0x0fef, 0x0000, 0x03a0, 0x0000, A1, MOV_IMM),
|
||||
ARMv7_OP4(0x0ff0, 0x0000, 0x0300, 0x0000, A2, MOV_IMM),
|
||||
ARMv7_OP2(0xff00, 0x4600, T1, MOV_REG),
|
||||
ARMv7_OP2(0xffc0, 0x0000, T2, MOV_REG),
|
||||
ARMv7_OP4(0xffef, 0xf0f0, 0xea4f, 0x0000, T3, MOV_REG),
|
||||
ARMv7_OP4(0x0fef, 0x0ff0, 0x01a0, 0x0000, A1, MOV_REG),
|
||||
ARMv7_OP4(0xfbf0, 0x8000, 0xf2c0, 0x0000, T1, MOVT),
|
||||
ARMv7_OP4(0x0ff0, 0x0000, 0x0340, 0x0000, A1, MOVT),
|
||||
|
||||
ARMv7_OP4(0xffff, 0xf0ff, 0xf3ef, 0x8000, T1, MRS),
|
||||
ARMv7_OP4(0x0fff, 0x0fff, 0x010f, 0x0000, A1, MRS),
|
||||
ARMv7_OP4(0x0ff3, 0xf000, 0x0320, 0xf000, A1, MSR_IMM),
|
||||
ARMv7_OP4(0xfff0, 0xf3ff, 0xf380, 0x8000, T1, MSR_REG),
|
||||
ARMv7_OP4(0x0ff3, 0xfff0, 0x0120, 0xf000, A1, MSR_REG),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0x4340, T1, MUL),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfb00, 0xf000, T2, MUL),
|
||||
ARMv7_OP4(0x0fe0, 0xf0f0, 0x0000, 0x0090, A1, MUL),
|
||||
|
||||
ARMv7_OP4(0xfbef, 0x8000, 0xf06f, 0x0000, T1, MVN_IMM),
|
||||
ARMv7_OP4(0x0fef, 0x0000, 0x03e0, 0x0000, A1, MVN_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x43c0, T1, MVN_REG),
|
||||
ARMv7_OP4(0xffef, 0x8000, 0xea6f, 0x0000, T2, MVN_REG),
|
||||
ARMv7_OP4(0xffef, 0x0010, 0x01e0, 0x0000, A1, MVN_REG),
|
||||
ARMv7_OP4(0x0fef, 0x0090, 0x01e0, 0x0010, A1, MVN_RSR),
|
||||
|
||||
ARMv7_OP2(0xffff, 0xbf00, T1, NOP),
|
||||
ARMv7_OP4(0xffff, 0xffff, 0xf3af, 0x8000, T2, NOP),
|
||||
ARMv7_OP4(0x0fff, 0xffff, 0x0320, 0xf000, A1, NOP),
|
||||
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf060, 0x0000, T1, ORN_IMM),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xea60, 0x0000, T1, ORN_REG),
|
||||
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf040, 0x0000, T1, ORR_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x0380, 0x0000, A1, ORR_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4300, T1, ORR_REG),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xea40, 0x0000, T2, ORR_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x0180, 0x0000, A1, ORR_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x0180, 0x0010, A1, ORR_RSR),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x8010, 0xeac0, 0x0000, T1, PKH),
|
||||
ARMv7_OP4(0x0ff0, 0x0030, 0x0680, 0x0010, A1, PKH),
|
||||
|
||||
ARMv7_OP2(0xfe00, 0xbc00, T1, POP),
|
||||
ARMv7_OP4(0xffff, 0x0000, 0xe8bd, 0x0000, T2, POP),
|
||||
ARMv7_OP4(0xffff, 0x0fff, 0xf85d, 0x0b04, T3, POP),
|
||||
ARMv7_OP4(0x0fff, 0x0000, 0x08bd, 0x0000, A1, POP),
|
||||
ARMv7_OP4(0x0fff, 0x0fff, 0x049d, 0x0004, A2, POP),
|
||||
|
||||
ARMv7_OP2(0xfe00, 0xb400, T1, PUSH),
|
||||
ARMv7_OP4(0xffff, 0x0000, 0xe92d, 0x0000, T2, PUSH), // had an error in arch ref
|
||||
ARMv7_OP4(0xffff, 0x0fff, 0xf84d, 0x0d04, T3, PUSH),
|
||||
ARMv7_OP4(0x0fff, 0x0000, 0x092d, 0x0000, A1, PUSH),
|
||||
ARMv7_OP4(0x0fff, 0x0fff, 0x052d, 0x0004, A2, PUSH),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf080, T1, QADD),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0100, 0x0050, A1, QADD),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf010, T1, QADD16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f10, A1, QADD16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf010, T1, QADD8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f90, A1, QADD8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf010, T1, QASX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f30, A1, QASX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf090, T1, QDADD),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0140, 0x0050, A1, QDADD),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf0b0, T1, QDSUB),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0160, 0x0050, A1, QDSUB),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf010, T1, QSAX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f50, A1, QSAX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf0a0, T1, QSUB),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0120, 0x0050, A1, QSUB),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf010, T1, QSUB16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0f70, A1, QSUB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf010, T1, QSUB8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0620, 0x0ff0, A1, QSUB8),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf0a0, T1, RBIT),
|
||||
ARMv7_OP4(0x0fff, 0x0ff0, 0x06ff, 0x0f30, A1, RBIT),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0xba00, T1, REV),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf080, T2, REV),
|
||||
ARMv7_OP4(0x0fff, 0x0ff0, 0x06bf, 0x0f30, A1, REV),
|
||||
ARMv7_OP2(0xffc0, 0xba40, T1, REV16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf090, T2, REV16),
|
||||
ARMv7_OP4(0x0fff, 0x0ff0, 0x06bf, 0x0fb0, A1, REV16),
|
||||
ARMv7_OP2(0xffc0, 0xbac0, T1, REVSH),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf0b0, T2, REVSH),
|
||||
ARMv7_OP4(0x0fff, 0x0ff0, 0x06ff, 0x0fb0, A1, REVSH),
|
||||
|
||||
ARMv7_OP4(0xffef, 0x8030, 0xea4f, 0x0030, T1, ROR_IMM),
|
||||
ARMv7_OP4(0x0fef, 0x0070, 0x01a0, 0x0060, A1, ROR_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x41c0, T1, ROR_REG),
|
||||
ARMv7_OP4(0xffe0, 0xf0f0, 0xfa60, 0xf000, T2, ROR_REG),
|
||||
ARMv7_OP4(0x0fef, 0x00f0, 0x01a0, 0x0070, A1, ROR_REG),
|
||||
ARMv7_OP4(0xffef, 0xf0f0, 0xea4f, 0x0030, T1, RRX),
|
||||
ARMv7_OP4(0x0fef, 0x0ff0, 0x01a0, 0x0060, A1, RRX),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0x4240, T1, RSB_IMM),
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf1c0, 0x0000, T2, RSB_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x0260, 0x0000, A1, RSB_IMM),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xebc0, 0x0000, T1, RSB_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x0060, 0x0000, A1, RSB_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x0060, 0x0010, A1, RSB_RSR),
|
||||
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x02e0, 0x0000, A1, RSC_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x00e0, 0x0000, A1, RSC_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x00e0, 0x0010, A1, RSC_RSR),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf000, T1, SADD16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f10, A1, SADD16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf000, T1, SADD8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f90, A1, SADD8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf000, T1, SASX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f30, A1, SASX),
|
||||
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf160, 0x0000, T1, SBC_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x02c0, 0x0000, A1, SBC_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4180, T1, SBC_REG),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xeb60, 0x0000, T2, SBC_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x00c0, 0x0000, A1, SBC_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x00c0, 0x0010, A1, SBC_RSR),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x8020, 0xf340, 0x0000, T1, SBFX),
|
||||
ARMv7_OP4(0x0fe0, 0x0070, 0x07a0, 0x0050, A1, SBFX),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfb90, 0xf0f0, T1, SDIV), // ???
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf080, T1, SEL),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0680, 0x0fb0, A1, SEL),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf020, T1, SHADD16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f10, A1, SHADD16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf020, T1, SHADD8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f90, A1, SHADD8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf020, T1, SHASX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f30, A1, SHASX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf020, T1, SHSAX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f50, A1, SHSAX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf020, T1, SHSUB16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0f70, A1, SHSUB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf020, T1, SHSUB8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0630, 0x0ff0, A1, SHSUB8),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x00c0, 0xfb10, 0x0000, T1, SMLA__),
|
||||
ARMv7_OP4(0x0ff0, 0x0090, 0x0100, 0x0080, A1, SMLA__),
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfb20, 0x0000, T1, SMLAD),
|
||||
ARMv7_OP4(0x0ff0, 0x00d0, 0x0700, 0x0010, A1, SMLAD),
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfbc0, 0x0000, T1, SMLAL),
|
||||
ARMv7_OP4(0x0fe0, 0x00f0, 0x00e0, 0x0090, A1, SMLAL),//???
|
||||
ARMv7_OP4(0xfff0, 0x00c0, 0xfbc0, 0x0080, T1, SMLAL__),
|
||||
ARMv7_OP4(0x0ff0, 0x0090, 0x0140, 0x0080, A1, SMLAL__),
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfbc0, 0x00c0, T1, SMLALD),
|
||||
ARMv7_OP4(0x0ff0, 0x00d0, 0x0740, 0x0010, A1, SMLALD),
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfb30, 0x0000, T1, SMLAW_),
|
||||
ARMv7_OP4(0x0ff0, 0x00b0, 0x0120, 0x0080, A1, SMLAW_),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfb40, 0x0000, T1, SMLSD),
|
||||
ARMv7_OP4(0x0ff0, 0x00d0, 0x0700, 0x0050, A1, SMLSD),
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfbd0, 0x00c0, T1, SMLSLD),
|
||||
ARMv7_OP4(0x0ff0, 0x00d0, 0x0740, 0x0050, A1, SMLSLD),
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfb50, 0x0000, T1, SMMLA),
|
||||
ARMv7_OP4(0x0ff0, 0x00d0, 0x0750, 0x0010, A1, SMMLA),
|
||||
ARMv7_OP4(0xfff0, 0x00e0, 0xfb60, 0x0000, T1, SMMLS),
|
||||
ARMv7_OP4(0x0ff0, 0x00d0, 0x0750, 0x00d0, A1, SMMLS),
|
||||
ARMv7_OP4(0xfff0, 0xf0e0, 0xfb50, 0xf000, T1, SMMUL),
|
||||
ARMv7_OP4(0x0ff0, 0xf0d0, 0x0750, 0xf010, A1, SMMUL),
|
||||
ARMv7_OP4(0xfff0, 0xf0e0, 0xfb20, 0xf000, T1, SMUAD),
|
||||
ARMv7_OP4(0x0ff0, 0xf0d0, 0x0700, 0xf010, A1, SMUAD),
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfb10, 0xf000, T1, SMUL__),
|
||||
ARMv7_OP4(0x0ff0, 0xf090, 0x0160, 0x0080, A1, SMUL__),//???
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfb80, 0x0000, T1, SMULL),
|
||||
ARMv7_OP4(0x0fe0, 0x00f0, 0x00c0, 0x0090, A1, SMULL),
|
||||
ARMv7_OP4(0xfff0, 0xf0e0, 0xfb30, 0xf000, T1, SMULW_),
|
||||
ARMv7_OP4(0x0ff0, 0xf0b0, 0x0120, 0x00a0, A1, SMULW_),//???
|
||||
ARMv7_OP4(0xfff0, 0xf0e0, 0xfb40, 0xf000, T1, SMUSD),
|
||||
ARMv7_OP4(0x0ff0, 0xf0d0, 0x0700, 0xf050, A1, SMUSD),
|
||||
ARMv7_OP4(0xffd0, 0x8020, 0xf300, 0x0000, T1, SSAT),
|
||||
ARMv7_OP4(0x0fe0, 0x0030, 0x06a0, 0x0010, A1, SSAT),
|
||||
ARMv7_OP4(0xfff0, 0xf0e0, 0xf320, 0x0000, T1, SSAT16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x06a0, 0x0f30, A1, SSAT16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf000, T1, SSAX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f50, A1, SSAX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf000, T1, SSUB16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0f70, A1, SSUB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf000, T1, SSUB8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0610, 0x0ff0, A1, SSUB8),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0x0000, 0xe840, 0x0000, T1, STREX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0180, 0x0f90, A1, STREX),
|
||||
ARMv7_OP4(0xfff0, 0x0ff0, 0xe8c0, 0x0f40, T1, STREXB),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x01c0, 0x0f90, A1, STREXB),
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xe8c0, 0x0070, T1, STREXD),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x01a0, 0x0f90, A1, STREXD),
|
||||
ARMv7_OP4(0xfff0, 0x0ff0, 0xe8c0, 0x0f50, T1, STREXH),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x01e0, 0x0f90, A1, STREXH),
|
||||
|
||||
ARMv7_OP2(0xf800, 0xc000, T1, STM),
|
||||
ARMv7_OP4(0xffd0, 0xa000, 0xe880, 0x0000, T2, STM),
|
||||
ARMv7_OP4(0x0fd0, 0x0000, 0x0880, 0x0000, A1, STM),
|
||||
ARMv7_OP4(0x0fd0, 0x0000, 0x0800, 0x0000, A1, STMDA),
|
||||
ARMv7_OP4(0xffd0, 0xa000, 0xe900, 0x0000, T1, STMDB),
|
||||
ARMv7_OP4(0x0fd0, 0x0000, 0x0900, 0x0000, A1, STMDB),
|
||||
ARMv7_OP4(0x0fd0, 0x0000, 0x0980, 0x0000, A1, STMIB),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x6000, T1, STR_IMM),
|
||||
ARMv7_OP2(0xf800, 0x9000, T2, STR_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0000, 0xf8c0, 0x0000, T3, STR_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0800, 0xf840, 0x0800, T4, STR_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x0000, 0x0400, 0x0000, A1, STR_IMM),
|
||||
ARMv7_OP2(0xfe00, 0x5000, T1, STR_REG),
|
||||
ARMv7_OP4(0xfff0, 0x0fc0, 0xf840, 0x0000, T2, STR_REG),
|
||||
ARMv7_OP4(0x0e50, 0x0010, 0x0600, 0x0000, A1, STR_REG),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x7000, T1, STRB_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0000, 0xf880, 0x0000, T2, STRB_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0800, 0xf800, 0x0800, T3, STRB_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x0000, 0x0440, 0x0000, A1, STRB_IMM),
|
||||
ARMv7_OP2(0xfe00, 0x5400, T1, STRB_REG),
|
||||
ARMv7_OP4(0xfff0, 0x0fc0, 0xf800, 0x0000, T2, STRB_REG),
|
||||
ARMv7_OP4(0x0e50, 0x0010, 0x0640, 0x0000, A1, STRB_REG),
|
||||
|
||||
ARMv7_OP4(0xfe50, 0x0000, 0xe840, 0x0000, T1, STRD_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x00f0, 0x0040, 0x00f0, A1, STRD_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x0ff0, 0x0000, 0x00f0, A1, STRD_REG),
|
||||
|
||||
ARMv7_OP2(0xf800, 0x8000, T1, STRH_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0000, 0xf8a0, 0x0000, T2, STRH_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x0800, 0xf820, 0x0800, T3, STRH_IMM),
|
||||
ARMv7_OP4(0x0e50, 0x00f0, 0x0040, 0x00b0, A1, STRH_IMM),
|
||||
ARMv7_OP2(0xfe00, 0x5200, T1, STRH_REG),
|
||||
ARMv7_OP4(0xfff0, 0x0fc0, 0xf820, 0x0000, T2, STRH_REG),
|
||||
ARMv7_OP4(0x0e50, 0x0ff0, 0x0000, 0x00b0, A1, STRH_REG),
|
||||
|
||||
ARMv7_OP2(0xff80, 0xb080, T1, SUB_SPI),
|
||||
ARMv7_OP4(0xfbef, 0x8000, 0xf1ad, 0x0000, T2, SUB_SPI),
|
||||
ARMv7_OP4(0xfbff, 0x8000, 0xf2ad, 0x0000, T3, SUB_SPI),
|
||||
ARMv7_OP4(0x0fef, 0x0000, 0x024d, 0x0000, A1, SUB_SPI),
|
||||
ARMv7_OP4(0xffef, 0x8000, 0xebad, 0x0000, T1, SUB_SPR),
|
||||
ARMv7_OP4(0x0fef, 0x0010, 0x004d, 0x0000, A1, SUB_SPR),
|
||||
ARMv7_OP2(0xfe00, 0x1e00, T1, SUB_IMM),
|
||||
ARMv7_OP2(0xf800, 0x3800, T2, SUB_IMM),
|
||||
ARMv7_OP4(0xfbe0, 0x8000, 0xf1a0, 0x0000, T3, SUB_IMM),
|
||||
ARMv7_OP4(0xfbf0, 0x8000, 0xf2a0, 0x0000, T4, SUB_IMM),
|
||||
ARMv7_OP4(0x0fe0, 0x0000, 0x0240, 0x0000, A1, SUB_IMM),
|
||||
ARMv7_OP2(0xfe00, 0x1a00, T1, SUB_REG),
|
||||
ARMv7_OP4(0xffe0, 0x8000, 0xeba0, 0x0000, T2, SUB_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0010, 0x0040, 0x0000, A1, SUB_REG),
|
||||
ARMv7_OP4(0x0fe0, 0x0090, 0x0040, 0x0010, A1, SUB_RSR),
|
||||
|
||||
ARMv7_OP2(0xff00, 0xdf00, T1, SVC),
|
||||
ARMv7_OP4(0x0f00, 0x0000, 0x0f00, 0x0000, A1, SVC),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfa40, 0xf080, T1, SXTAB),
|
||||
ARMv7_OP4(0x0ff0, 0x03f0, 0x06a0, 0x0070, A1, SXTAB),
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfa20, 0xf080, T1, SXTAB16),
|
||||
ARMv7_OP4(0x0ff0, 0x03f0, 0x0680, 0x0070, A1, SXTAB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfa00, 0xf080, T1, SXTAH),
|
||||
ARMv7_OP4(0x0ff0, 0x03f0, 0x06b0, 0x0070, A1, SXTAH),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0xb240, T1, SXTB),
|
||||
ARMv7_OP4(0xffff, 0xf0c0, 0xfa4f, 0xf080, T2, SXTB),
|
||||
ARMv7_OP4(0x0fff, 0x03f0, 0x06af, 0x0070, A1, SXTB),
|
||||
|
||||
ARMv7_OP4(0xffff, 0xf0c0, 0xfa2f, 0xf080, T1, SXTB16),
|
||||
ARMv7_OP4(0x0fff, 0x03f0, 0x068f, 0x0070, A1, SXTB16),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0xb200, T1, SXTH),
|
||||
ARMv7_OP4(0xffff, 0xf0c0, 0xfa0f, 0xf080, T2, SXTH),
|
||||
ARMv7_OP4(0x0fff, 0x03f0, 0x06bf, 0x0070, A1, SXTH),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xffe0, 0xe8d0, 0xf000, T1, TB_),
|
||||
|
||||
ARMv7_OP4(0xfbf0, 0x8f00, 0xf090, 0x0f00, T1, TEQ_IMM),
|
||||
ARMv7_OP4(0x0ff0, 0xf000, 0x0330, 0x0000, A1, TEQ_IMM),
|
||||
ARMv7_OP4(0xfff0, 0x8f00, 0xea90, 0x0f00, T1, TEQ_REG),
|
||||
ARMv7_OP4(0x0ff0, 0xf010, 0x0130, 0x0000, A1, TEQ_REG),
|
||||
ARMv7_OP4(0x0ff0, 0xf090, 0x0130, 0x0010, A1, TEQ_RSR),
|
||||
|
||||
ARMv7_OP4(0xfbf0, 0x8f00, 0xf010, 0x0f00, T1, TST_IMM),
|
||||
ARMv7_OP4(0x0ff0, 0xf000, 0x0310, 0x0000, A1, TST_IMM),
|
||||
ARMv7_OP2(0xffc0, 0x4200, T1, TST_REG),
|
||||
ARMv7_OP4(0xfff0, 0x8f00, 0xea10, 0x0f00, T2, TST_REG),
|
||||
ARMv7_OP4(0x0ff0, 0xf010, 0x0110, 0x0000, A1, TST_REG),
|
||||
ARMv7_OP4(0x0ff0, 0xf090, 0x0110, 0x0010, A1, TST_RSR),
|
||||
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf040, T1, UADD16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f10, A1, UADD16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf040, T1, UADD8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f90, A1, UADD8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf040, T1, UASX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f30, A1, UASX),
|
||||
ARMv7_OP4(0xfff0, 0x8020, 0xf3c0, 0x0000, T1, UBFX),
|
||||
ARMv7_OP4(0x0fe0, 0x0070, 0x07e0, 0x0050, A1, UBFX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfbb0, 0xf0f0, T1, UDIV),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf060, T1, UHADD16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f10, A1, UHADD16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf060, T1, UHADD8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f90, A1, UHADD8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf060, T1, UHASX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f30, A1, UHASX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf060, T1, UHSAX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f50, A1, UHSAX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf060, T1, UHSUB16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0f70, A1, UHSUB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf060, T1, UHSUB8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0670, 0x0ff0, A1, UHSUB8),
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfbe0, 0x0060, T1, UMAAL),
|
||||
ARMv7_OP4(0x0ff0, 0x00f0, 0x0040, 0x0090, A1, UMAAL),
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfbe0, 0x0000, T1, UMLAL),
|
||||
ARMv7_OP4(0x0fe0, 0x00f0, 0x00a0, 0x0090, A1, UMLAL),
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfba0, 0x0000, T1, UMULL),
|
||||
ARMv7_OP4(0x0fe0, 0x00f0, 0x0080, 0x0090, A1, UMULL),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa90, 0xf050, T1, UQADD16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f10, A1, UQADD16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfa80, 0xf050, T1, UQADD8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f90, A1, UQADD8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfaa0, 0xf050, T1, UQASX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f30, A1, UQASX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf050, T1, UQSAX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f50, A1, UQSAX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf050, T1, UQSUB16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0f70, A1, UQSUB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf050, T1, UQSUB8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0660, 0x0ff0, A1, UQSUB8),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfb70, 0xf000, T1, USAD8),
|
||||
ARMv7_OP4(0x0ff0, 0xf0f0, 0x0780, 0xf010, A1, USAD8),
|
||||
ARMv7_OP4(0xfff0, 0x00f0, 0xfb70, 0x0000, T1, USADA8),
|
||||
ARMv7_OP4(0x0ff0, 0x00f0, 0x0780, 0x0010, A1, USADA8),
|
||||
ARMv7_OP4(0xffd0, 0x8020, 0xf380, 0x0000, T1, USAT),
|
||||
ARMv7_OP4(0x0fe0, 0x0030, 0x06e0, 0x0010, A1, USAT),
|
||||
ARMv7_OP4(0xfff0, 0xf0e0, 0xf3a0, 0x0000, T1, USAT16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x06e0, 0x0f30, A1, USAT16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfae0, 0xf040, T1, USAX),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f50, A1, USAX),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfad0, 0xf040, T1, USUB16),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0f70, A1, USUB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0f0, 0xfac0, 0xf040, T1, USUB8),
|
||||
ARMv7_OP4(0x0ff0, 0x0ff0, 0x0650, 0x0ff0, A1, USUB8),
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfa50, 0xf080, T1, UXTAB),
|
||||
ARMv7_OP4(0x0ff0, 0x03f0, 0x06e0, 0x0070, A1, UXTAB),
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfa30, 0xf080, T1, UXTAB16),
|
||||
ARMv7_OP4(0x0ff0, 0x03f0, 0x06c0, 0x0070, A1, UXTAB16),
|
||||
ARMv7_OP4(0xfff0, 0xf0c0, 0xfa10, 0xf080, T1, UXTAH),
|
||||
ARMv7_OP4(0x0ff0, 0x03f0, 0x06f0, 0x0070, A1, UXTAH),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0xb2c0, T1, UXTB),
|
||||
ARMv7_OP4(0xffff, 0xf0c0, 0xfa5f, 0xf080, T2, UXTB),
|
||||
ARMv7_OP4(0x0fff, 0x03f0, 0x06ef, 0x0070, A1, UXTB),
|
||||
|
||||
ARMv7_OP4(0xffff, 0xf0c0, 0xfa3f, 0xf080, T1, UXTB16),
|
||||
ARMv7_OP4(0x0fff, 0x03f0, 0x06cf, 0x0070, A1, UXTB16),
|
||||
|
||||
ARMv7_OP2(0xffc0, 0xb280, T1, UXTH),
|
||||
ARMv7_OP4(0xffff, 0xf0c0, 0xfa1f, 0xf080, T2, UXTH),
|
||||
ARMv7_OP4(0x0fff, 0x03f0, 0x06ff, 0x0070, A1, UXTH),
|
||||
|
||||
ARMv7_OP4(0xef80, 0x0f10, 0xef00, 0x0710, T1, VABA_),
|
||||
ARMv7_OP4(0xfe80, 0x0f10, 0xf200, 0x0710, A1, VABA_),
|
||||
ARMv7_OP4(0xef80, 0x0f50, 0xef80, 0x0500, T2, VABA_),
|
||||
ARMv7_OP4(0xfe80, 0x0f50, 0xf280, 0x0500, A2, VABA_),
|
||||
|
||||
// TODO: vector instructions
|
||||
|
||||
ARMv7_OP2(0xffff, 0xbf20, T1, WFE),
|
||||
ARMv7_OP4(0xffff, 0xffff, 0xf3af, 0x8002, T2, WFE),
|
||||
ARMv7_OP4(0x0fff, 0xffff, 0x0320, 0xf002, A1, WFE),
|
||||
ARMv7_OP2(0xffff, 0xbf30, T1, WFI),
|
||||
ARMv7_OP4(0xffff, 0xffff, 0xf3af, 0x8003, T2, WFI),
|
||||
ARMv7_OP4(0x0fff, 0xffff, 0x0320, 0xf003, A1, WFI),
|
||||
ARMv7_OP2(0xffff, 0xbf10, T1, YIELD),
|
||||
ARMv7_OP4(0xffff, 0xffff, 0xf3af, 0x8001, T2, YIELD),
|
||||
ARMv7_OP4(0x0fff, 0xffff, 0x0320, 0xf001, A1, YIELD),
|
||||
};
|
||||
|
||||
#undef ARMv7_OP2
|
||||
#undef ARMv7_OP4
|
||||
|
||||
@ -2,8 +2,6 @@
|
||||
|
||||
#include "Emu/ARMv7/ARMv7Thread.h"
|
||||
#include "Emu/ARMv7/ARMv7Interpreter.h"
|
||||
//#include "Emu/System.h"
|
||||
//#include "Utilities/Log.h"
|
||||
|
||||
static const char* g_arm_reg_name[16] =
|
||||
{
|
||||
@ -12,7 +10,7 @@ static const char* g_arm_reg_name[16] =
|
||||
"r8", "r9", "r10", "r11",
|
||||
"r12", "sp", "lr", "pc",
|
||||
};
|
||||
|
||||
#if 0
|
||||
using namespace ARMv7_instrs;
|
||||
|
||||
struct ARMv7_Instruction
|
||||
@ -23,8 +21,6 @@ struct ARMv7_Instruction
|
||||
const char* name;
|
||||
};
|
||||
|
||||
#if 0
|
||||
|
||||
#define ARMv7_OP_2(func, type) { func, 2, type, #func "_" #type }
|
||||
#define ARMv7_OP_4(func, type) { func, 4, type, #func "_" #type }
|
||||
#define ARMv7_NULL_OP { NULL_OP, 2, T1, "NULL_OP" }
|
||||
|
||||
@ -52,6 +52,7 @@
|
||||
<ClCompile Include="Crypto\unpkg.cpp" />
|
||||
<ClCompile Include="Crypto\unself.cpp" />
|
||||
<ClCompile Include="Crypto\utils.cpp" />
|
||||
<ClCompile Include="Emu\ARMv7\ARMv7Decoder.cpp" />
|
||||
<ClCompile Include="Emu\ARMv7\ARMv7DisAsm.cpp" />
|
||||
<ClCompile Include="Emu\ARMv7\ARMv7Interpreter.cpp" />
|
||||
<ClCompile Include="Emu\ARMv7\ARMv7Thread.cpp" />
|
||||
|
||||
@ -662,6 +662,9 @@
|
||||
<ClCompile Include="Emu\Audio\XAudio2\XAudio2Thread.cpp">
|
||||
<Filter>Emu\Audio\XAudio2</Filter>
|
||||
</ClCompile>
|
||||
<ClCompile Include="Emu\ARMv7\ARMv7Decoder.cpp">
|
||||
<Filter>Emu\CPU\ARMv7</Filter>
|
||||
</ClCompile>
|
||||
</ItemGroup>
|
||||
<ItemGroup>
|
||||
<ClInclude Include="Crypto\aes.h">
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user