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SPU LLVM: refactor halt instructions
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a0bf103e8b
commit
513bac0304
@ -3812,80 +3812,55 @@ public:
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set_vr(op.rt, r);
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}
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void make_halt(llvm::BasicBlock* next)
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void make_halt(value_t<bool> cond)
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{
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const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
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const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
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m_ir->CreateCondBr(cond.value, halt, next);
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m_ir->SetInsertPoint(halt);
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const auto pstatus = spu_ptr<u32>(&SPUThread::status);
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const auto chalt = m_ir->getInt32(SPU_STATUS_STOPPED_BY_HALT);
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m_ir->CreateAtomicRMW(llvm::AtomicRMWInst::Or, pstatus, chalt, llvm::AtomicOrdering::Release)->setVolatile(true);
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const auto ptr = m_ir->CreateIntToPtr(m_ir->getInt64(reinterpret_cast<u64>(vm::base(0xffdead00))), get_type<u32*>());
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m_ir->CreateStore(m_ir->getInt32("HALT"_u32), ptr)->setVolatile(true);
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m_ir->CreateBr(next);
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m_ir->SetInsertPoint(next);
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}
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void HGT(spu_opcode_t op) //
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{
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const auto cond = eval(extract(get_vr<s32[4]>(op.ra), 3) > extract(get_vr<s32[4]>(op.rb), 3));
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const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
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const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
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m_ir->CreateCondBr(cond.value, halt, next);
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m_ir->SetInsertPoint(halt);
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make_halt(next);
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m_ir->SetInsertPoint(next);
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make_halt(cond);
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}
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void HEQ(spu_opcode_t op) //
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{
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const auto cond = eval(extract(get_vr(op.ra), 3) == extract(get_vr(op.rb), 3));
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const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
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const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
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m_ir->CreateCondBr(cond.value, halt, next);
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m_ir->SetInsertPoint(halt);
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make_halt(next);
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m_ir->SetInsertPoint(next);
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make_halt(cond);
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}
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void HLGT(spu_opcode_t op) //
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{
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const auto cond = eval(extract(get_vr(op.ra), 3) > extract(get_vr(op.rb), 3));
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const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
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const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
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m_ir->CreateCondBr(cond.value, halt, next);
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m_ir->SetInsertPoint(halt);
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make_halt(next);
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m_ir->SetInsertPoint(next);
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make_halt(cond);
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}
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void HGTI(spu_opcode_t op) //
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{
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const auto cond = eval(extract(get_vr<s32[4]>(op.ra), 3) > op.si10);
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const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
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const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
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m_ir->CreateCondBr(cond.value, halt, next);
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m_ir->SetInsertPoint(halt);
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make_halt(next);
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m_ir->SetInsertPoint(next);
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make_halt(cond);
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}
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void HEQI(spu_opcode_t op) //
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{
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const auto cond = eval(extract(get_vr(op.ra), 3) == op.si10);
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const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
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const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
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m_ir->CreateCondBr(cond.value, halt, next);
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m_ir->SetInsertPoint(halt);
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make_halt(next);
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m_ir->SetInsertPoint(next);
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make_halt(cond);
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}
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void HLGTI(spu_opcode_t op) //
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{
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const auto cond = eval(extract(get_vr(op.ra), 3) > op.si10);
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const auto next = llvm::BasicBlock::Create(m_context, "", m_function);
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const auto halt = llvm::BasicBlock::Create(m_context, "", m_function);
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m_ir->CreateCondBr(cond.value, halt, next);
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m_ir->SetInsertPoint(halt);
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make_halt(next);
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m_ir->SetInsertPoint(next);
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make_halt(cond);
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}
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void HBR(spu_opcode_t op) //
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