From 43302f937cf07849f54ee3ca31f7418a50962d5f Mon Sep 17 00:00:00 2001
From: Eladash <elad3356p@gmail.com>
Date: Sat, 16 Oct 2021 10:36:00 +0300
Subject: [PATCH] PPUDisAsm: Fixup SC printing, support LV1 syscalls

---
 rpcs3/Emu/Cell/PPUDisAsm.cpp | 37 +++++++++++++++++++++++++++++++-----
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/rpcs3/Emu/Cell/PPUDisAsm.cpp b/rpcs3/Emu/Cell/PPUDisAsm.cpp
index 21398ee57a..5c690b7f2d 100644
--- a/rpcs3/Emu/Cell/PPUDisAsm.cpp
+++ b/rpcs3/Emu/Cell/PPUDisAsm.cpp
@@ -1347,19 +1347,46 @@ void PPUDisAsm::BC(ppu_opcode_t op)
 
 void PPUDisAsm::SC(ppu_opcode_t op)
 {
-	if (op.opcode != ppu_instructions::SC(0))
+	if (op.opcode != ppu_instructions::SC(0) && op.opcode != ppu_instructions::SC(1))
 	{
 		return UNK(op);
 	}
 
-	// Try to get constant syscall index
-	if (auto [is_const, index] = try_get_const_gpr_value(11); is_const && index < 1024u)
+	fmt::append(last_opcode, "%-*s ", PadOp(), "sc");
+
+	if (op.lev)
+	{
+		fmt::append(last_opcode, "%u ", op.lev);
+	}
+
+	// Try to get constant syscall index
+	auto [is_const, index] = try_get_const_gpr_value(11);
+
+	if (!is_const)
 	{
-		fmt::append(last_opcode, "%-*s #%s", PadOp(), ppu_syscall_code{index});
 		return;
 	}
 
-	last_opcode += "sc";
+	switch (op.lev)
+	{
+	case 0:
+	{
+		// Lv2 syscall
+		if (index < 1024u)
+		{
+			fmt::append(last_opcode, "#%s", ppu_syscall_code{index});
+		}
+
+		return;
+	}
+	case 1:
+	{
+		// Lv1 syscall
+		fmt::append(last_opcode, "#lv1_syscall_%u", index);
+		return;
+	}
+	default: return;
+	}
 }
 
 void PPUDisAsm::B(ppu_opcode_t op)