From 3c762750a0def0c2591d0deb0ac7ba033aa2d7d3 Mon Sep 17 00:00:00 2001
From: Magn3s1um <sodroski@bu.edu>
Date: Fri, 8 Nov 2013 17:17:44 -0800
Subject: [PATCH] -Added SPR registers -Implemented MTSPR

---
 rpcs3/Emu/Cell/SPUDisAsm.h      |  2 +-
 rpcs3/Emu/Cell/SPUInterpreter.h | 14 ++++++++++--
 rpcs3/Emu/Cell/SPUThread.h      | 39 +++++++++++++++++++++++++++++++++
 3 files changed, 52 insertions(+), 3 deletions(-)

diff --git a/rpcs3/Emu/Cell/SPUDisAsm.h b/rpcs3/Emu/Cell/SPUDisAsm.h
index ac1008273f..6c4dc82cd9 100644
--- a/rpcs3/Emu/Cell/SPUDisAsm.h
+++ b/rpcs3/Emu/Cell/SPUDisAsm.h
@@ -94,7 +94,7 @@ private:
 	}
 	void MFSPR(u32 rt, u32 sa)
 	{
-		DisAsm("mfspr", spu_reg_name[rt], spu_reg_name[sa]);   // Are SPR mapped on the GPR or are there 128 additional registers ?
+		DisAsm("mfspr", spu_reg_name[rt], spu_reg_name[sa]);   // Are SPR mapped on the GPR or are there 128 additional registers ? Yes, there are also 128 SPR making 256 registers total
 	}
 	void RDCH(u32 rt, u32 ra)
 	{
diff --git a/rpcs3/Emu/Cell/SPUInterpreter.h b/rpcs3/Emu/Cell/SPUInterpreter.h
index 0926dae80d..88e73ade2d 100644
--- a/rpcs3/Emu/Cell/SPUInterpreter.h
+++ b/rpcs3/Emu/Cell/SPUInterpreter.h
@@ -44,7 +44,17 @@ private:
 	}
 	void MFSPR(u32 rt, u32 sa)
 	{
-		UNIMPLEMENTED();
+		//If register is a dummy register (register labeled 0x0)
+		if(sa == 0)
+		{
+			CPU.GPR[rt]._u128.hi = 0x0;
+			CPU.GPR[rt]._u128.lo = 0x0;
+		}
+		else
+		{
+			CPU.GPR[rt]._u128.hi =  CPU.SPR[sa]._u128.hi;
+			CPU.GPR[rt]._u128.lo =  CPU.SPR[sa]._u128.lo;
+		}
 	}
 	void RDCH(u32 rt, u32 ra)
 	{
@@ -890,7 +900,7 @@ private:
 	void MPYU(u32 rt, u32 ra, u32 rb)
 	{
 		for (int w = 0; w < 4; w++)
-			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u16[w*2 + 1] * CPU.GPR[rb]._u16[w*2 + 1];
+			CPU.GPR[rt]._u32[w] = CPU.GPR[ra]._u16[w*2] * CPU.GPR[rb]._u16[w];
 	}
 	void CEQB(u32 rt, u32 ra, u32 rb)
 	{
diff --git a/rpcs3/Emu/Cell/SPUThread.h b/rpcs3/Emu/Cell/SPUThread.h
index 7f9d58c13c..40c14a09f1 100644
--- a/rpcs3/Emu/Cell/SPUThread.h
+++ b/rpcs3/Emu/Cell/SPUThread.h
@@ -22,6 +22,25 @@ static const wxString spu_reg_name[128] =
 	"$112", "$113", "$114", "$115", "$116", "$117", "$118", "$119",
 	"$120", "$121", "$122", "$123", "$124", "$125", "$126", "$127",
 };
+//SPU reg $0 is a dummy reg, and is used for certain instructions.
+static const wxString spu_specialreg_name[129] = {
+	"$0",  "$1",  "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
+	"$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
+	"$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
+	"$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
+	"$32",  "$33",  "$34",  "$35",  "$36",  "$37",  "$38",  "$39",
+	"$40",  "$41",  "$42",  "$43",  "$44",  "$45",  "$46",  "$47",
+	"$48",  "$49",  "$50",  "$51",  "$52",  "$53",  "$54",  "$55",
+	"$56",  "$57",  "$58",  "$59",  "$60",  "$61",  "$62",  "$63",
+	"$64",  "$65",  "$66",  "$67",  "$68",  "$69",  "$70",  "$71",
+	"$72",  "$73",  "$74",  "$75",  "$76",  "$77",  "$78",  "$79",
+	"$80",  "$81",  "$82",  "$83",  "$84",  "$85",  "$86",  "$87",
+	"$88",  "$89",  "$90",  "$91",  "$92",  "$93",  "$94",  "$95",
+	"$96",  "$97",  "$98",  "$99",  "$100", "$101", "$102", "$103",
+	"$104", "$105", "$106", "$107", "$108", "$109", "$110", "$111",
+	"$112", "$113", "$114", "$115", "$116", "$117", "$118", "$119",
+	"$120", "$121", "$122", "$123", "$124", "$125", "$126", "$127", "$128",
+};
 
 static const wxString spu_ch_name[128] =
 {
@@ -126,10 +145,30 @@ union SPU_GPR_hdr
 	}
 };
 
+union SPU_SPR_hdr
+{
+	u128 _u128;
+	s128 _i128;
+	
+
+	SPU_SPR_hdr() {}
+
+	wxString ToString() const
+	{
+		return wxString::Format("%16%16", _u128.hi, _u128.lo);
+	}
+
+	void Reset()
+	{
+		memset(this, 0, sizeof(*this));
+	}
+};
+
 class SPUThread : public PPCThread
 {
 public:
 	SPU_GPR_hdr GPR[128]; //General-Purpose Register
+	SPU_SPR_hdr SPR[128]; //Special-Purpose Registers
 
 	template<size_t _max_count>
 	class Channel