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SPU Fixes 3.1
Small fixes
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1cfcc742d8
commit
38fabf7cd2
@ -287,12 +287,12 @@ private:
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}
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}
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void BIHZ(u32 rt, u32 ra)
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void BIHZ(u32 rt, u32 ra)
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{
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{
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if(CPU.GPR[rt]._u16[7] == 0)
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if(CPU.GPR[rt]._u16[6] == 0)
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CPU.SetBranch(branchTarget(CPU.GPR[ra]._u32[3], 0));
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CPU.SetBranch(branchTarget(CPU.GPR[ra]._u32[3], 0));
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}
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}
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void BIHNZ(u32 rt, u32 ra)
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void BIHNZ(u32 rt, u32 ra)
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{
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{
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if(CPU.GPR[rt]._u16[7] != 0)
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if(CPU.GPR[rt]._u16[6] != 0)
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CPU.SetBranch(branchTarget(CPU.GPR[ra]._u32[3], 0));
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CPU.SetBranch(branchTarget(CPU.GPR[ra]._u32[3], 0));
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}
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}
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void STOPD(u32 rc, u32 ra, u32 rb)
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void STOPD(u32 rc, u32 ra, u32 rb)
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@ -512,9 +512,9 @@ private:
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}
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}
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void ORX(u32 rt, u32 ra)
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void ORX(u32 rt, u32 ra)
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{
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{
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const SPU_GPR_hdr temp = CPU.GPR[ra];
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CPU.GPR[rt]._u32[3] = CPU.GPR[ra]._u32[0] | CPU.GPR[ra]._u32[1] | CPU.GPR[ra]._u32[2] | CPU.GPR[ra]._u32[3];
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CPU.GPR[rt].Reset();
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CPU.GPR[rt]._u32[2] = 0;
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CPU.GPR[rt]._u32[3] = temp._u32[0] | temp._u32[1] | temp._u32[2] | temp._u32[3];
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CPU.GPR[rt]._u64[0] = 0;
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}
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}
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void CBD(u32 rt, u32 ra, s32 i7)
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void CBD(u32 rt, u32 ra, s32 i7)
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{
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{
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@ -1022,12 +1022,12 @@ private:
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}
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}
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void BRHZ(u32 rt, s32 i16)
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void BRHZ(u32 rt, s32 i16)
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{
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{
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if (CPU.GPR[rt]._u16[7] == 0)
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if (CPU.GPR[rt]._u16[6] == 0)
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CPU.SetBranch(branchTarget(CPU.PC, i16));
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CPU.SetBranch(branchTarget(CPU.PC, i16));
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}
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}
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void BRHNZ(u32 rt, s32 i16)
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void BRHNZ(u32 rt, s32 i16)
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{
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{
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if (CPU.GPR[rt]._u16[7] != 0)
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if (CPU.GPR[rt]._u16[6] != 0)
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CPU.SetBranch(branchTarget(CPU.PC, i16));
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CPU.SetBranch(branchTarget(CPU.PC, i16));
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}
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}
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void STQR(u32 rt, s32 i16)
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void STQR(u32 rt, s32 i16)
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